嵌入式误码测试仪的设计
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摘要
在分析了嵌入式误码测试仪的使用需求和设计原理后,提出了一种基于FPGA的嵌入式误码测试仪的实现方法。通过对该实现方法的同步性能、误码计算方式进行分析、仿真,证明本方法具有可靠的同步特性,同时能够保证误码计算的实时性和连续性。嵌入式误码仪的实现使终端本身具有了误码测试功能,便于终端的自检测试及辅助系统故障定位。
After analyzing the requirements and design theory of embedded bit error ratio tester (BERT), a method of embedded BER tester based on FPGA is put forward. The analysis and simulation results show that this method has reliable synchronization performance and can ensure real-time and continuous calculation of bit error ratio. The realization of embedded BERT makes a terminal have the function of bit error ratio testing, which can be convenient for self-testing of the terminal and fault location of the auxiliary system.
After analyzing the requirements and design theory of embedded bit error ratio tester (BERT), a method of embedded BER tester based on FPGA is put forward. The analysis and simulation results show that this method has reliable synchronization performance and can ensure real-time and continuous calculation of bit error ratio. The realization of embedded BERT makes a terminal have the function of bit error ratio testing, which can be convenient for self-testing of the terminal and fault location of the auxiliary system.
引文
[1] 樊昌信.通信原理[M].北京:国防工业出版社,2006．
[2] 黄进,钟立人.智能误码测试仪[J].地震地磁观测与研究,2002,23(4) :72-76．
[3] 王登,常青,梅顺良.一种基于FPGA的误码性能测试方案[J].电子技术应用,2003,29(5) :54-55．
[4] 卢艳萍,陶成.基于FPGA的误码测试仪[J].电子产品世界,2004(04A):79-86．
[2] 黄进,钟立人.智能误码测试仪[J].地震地磁观测与研究,2002,23(4) :72-76．
[3] 王登,常青,梅顺良.一种基于FPGA的误码性能测试方案[J].电子技术应用,2003,29(5) :54-55．
[4] 卢艳萍,陶成.基于FPGA的误码测试仪[J].电子产品世界,2004(04A):79-86．
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