ARMv4指令集仿真平台设计
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摘要
现在,下一代嵌入式微处理器和软件面临着不断减小的产品寿命。而由此产生的缩短的研发周期则要求设计者能够在更短的时间内开发出更为复杂的处理器和软件。为了解决这个问题,指令集仿真器逐渐成为在新的可编程结构的开发中必不可少的工具。这样,仿真器的性能成为影响整个设计效率的重要因素。由于普遍使用的解释型仿真器的性能较低,从10年前开始,人们就开始了对编译型指令集仿真器的研究。但是,由于编译技术的限制,它从来没有能够在商业产品中推广。本文将ARMv4指令集作为目标指令集,设计了其仿真平台,给出了一种结合了解释和编译技术优点的仿真机。
我们首先介绍了ARMv4指令集的编程模型,包括目标指令集支持的处理器的模式、寄存器和存储器的组织和异常行为。
其次建立了仿真平台。在平台的建立过程中,设计了结合编译技术速度和解释技术灵活性的仿真机;完成了ARMv4指令集体系结构的描述;实现了存储器接口,从而可以满足目标指令集对存储器的访问要求;介绍了ELF文件格式,并设计了将ELF文件中的指令和数据装入存储器的装载程序。
最后对仿真平台进行了功能和性能的验证。在功能验证中,覆盖了普通指令的功能和异常行为。在性能验证中,利用ADPCM和GSM程序测试了平台采用的仿真机对性能的提升。
Today, designers of next-generation embedded processors and software are increasingly faced with short product lifetimes. The resulting time-to-market constrains are contradicting the continually growing processor complexity. In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Motivated by the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. In this paper, a simulation platform for ARMv4 instruction set is developed, which includes a simulation engine that combine the benefits of both compiled and interpretive simulation.
First, we introduce the programming model of the ARMv4 instruction set, including the processor modes supported, the register organization, the memory organization and the exception behaviors.
Then the simulation platform is built, in which part we design the simulation engine that combines the performance of compiled simulators with the flexibility of interpretive simulators; accomplish the description of the ARMv4 instruction set; implement the memory interface that meets the request of the objective instruction set to access memory; introduce the format of the ELF files and design a load program to load the instruction words and data words in the ELF files into memory.
Finally, the functions and the performance of the simulation platform are verified. In the functional verification, instruction functions and exception behaviors are verified. In the performance verification, ADPCM program and GSM program are used as benchmarks to indicate the performance improvement achieved by using our simulation engine.
我们首先介绍了ARMv4指令集的编程模型,包括目标指令集支持的处理器的模式、寄存器和存储器的组织和异常行为。
其次建立了仿真平台。在平台的建立过程中,设计了结合编译技术速度和解释技术灵活性的仿真机;完成了ARMv4指令集体系结构的描述;实现了存储器接口,从而可以满足目标指令集对存储器的访问要求;介绍了ELF文件格式,并设计了将ELF文件中的指令和数据装入存储器的装载程序。
最后对仿真平台进行了功能和性能的验证。在功能验证中,覆盖了普通指令的功能和异常行为。在性能验证中,利用ADPCM和GSM程序测试了平台采用的仿真机对性能的提升。
Today, designers of next-generation embedded processors and software are increasingly faced with short product lifetimes. The resulting time-to-market constrains are contradicting the continually growing processor complexity. In the last decade, instruction-set simulators have become an essential development tool for the design of new programmable architectures. Consequently, the simulator performance is a key factor for the overall design efficiency. Motivated by the extremely poor performance of commonly used interpretive simulators, research work on fast compiled instruction-set simulation was started ten years ago. However, due to the restrictiveness of the compiled technique, it has not been able to push through in commercial products. In this paper, a simulation platform for ARMv4 instruction set is developed, which includes a simulation engine that combine the benefits of both compiled and interpretive simulation.
First, we introduce the programming model of the ARMv4 instruction set, including the processor modes supported, the register organization, the memory organization and the exception behaviors.
Then the simulation platform is built, in which part we design the simulation engine that combines the performance of compiled simulators with the flexibility of interpretive simulators; accomplish the description of the ARMv4 instruction set; implement the memory interface that meets the request of the objective instruction set to access memory; introduce the format of the ELF files and design a load program to load the instruction words and data words in the ELF files into memory.
Finally, the functions and the performance of the simulation platform are verified. In the functional verification, instruction functions and exception behaviors are verified. In the performance verification, ADPCM program and GSM program are used as benchmarks to indicate the performance improvement achieved by using our simulation engine.
引文
1 Steve Furber. ARM SOC 体系结构. 田泽, 于敦山, 盛事敏. 第二版. 北京航空航天大学出版社, 2002: 1~5
2 刘振兴, 李宗福, 刘林辉. ARM 嵌入式技术实践教程. 北京航空航天大学出版社, 2005: 3~20
3 刑文峰, 姚庆栋, 史册, 高磊. 一种高速灵活的指令仿真器. 计算机工程. 2004, 30(22): 74~76
4 严迎建, 刘明业. ARMv4 指令集模拟器设计及优化技术. 小型微型计算机系统. 2005, 26(2): 315~317
5 陶峰峰, 付宇卓. DSP 指令集仿真器的设计与实现. 计算机仿真. 2005, 22(9): 225~228
6 钱斌, 付宇卓. 一种基于虚指令集技术构建快速的可重用的指令集仿真器的方法. 计算机工程与应用. 2005, (12): 95~97
7 王晓红, 王旭, 王雷, 金茂忠. 指令集仿真器自动生成技术的研究. 计算机工程与应用. 2003, (2): 129~131
8 D.Burger, T.M.Austin. The Simplescalar Tool Set, Version 2.0. Computer Architecture News. 1997, (2): 13~25
9 S. Sutarwala, P. Paulin, Y. Kumar. Insulin: an Instruction Set Simulation Environment. CHDL, Ottawa Canada, 1993: 355~362
10 Jianwen Zhm, Daniel D. Gajski. A Retargetable, Ultra-fast Instruction Set Simulator. Design Automation and Test in Europe Conference and Exhibition, Munich, 1999: 298~302
11 C. Mills, S. C. Ahalt, J. Fowler. Compiled Instruction Set Simulation. Software-Practice Exper. 1991, 21(8): 877~889
12 Z. Barzilai et al. HSS-A high-speed simulator. IEEE Transaction on Computer-Aided Design. 1987, 6(4): 601~616
13 Peter M. Maurer. Is Compiled Simulation Really Faster than Interpretive Simulation. International Conference on VLSI Design, Bangalore India, 1996: 303~306
14 N. Ramsey, M.F. Fernandez. Specifying Representations of Machine Instruction.ACM Transaction of Programming Languages and Systems. 1997, 19(3): 492~524
15 A. Fauth, J.Van Praet, M. Freericks. Describing Instruction Set Processors Using nML. European Design and Test Conference, Paris, 1995: 503~507
16 A. Fauth. Beyond Tool-Specific Machine Description. Code Generation for Embedded Processors. 1997, (5): 138~152
17 G. Hadjiyiannis, S. Hanono, S. Devadas. ISDL: an Instruction Set Description Language for Retargetability. Design Automation Conference, Anaheim California, 1997: 299~302
18 S. Chandra, R. Moona. Retargetable Functional Simulator Using High Level Processor Models. International Conference on VLSI Design, Calcutta, 2000: 424~429
19 V.Rajesh. A Generic Approach to Performance Modeling and Its Application to Simulator Generator. Master’s thesis, Department of Computer Science and Engineering, Indian Institute of Technology Kanpur. 1998: 13~30
20 A. Halambi, P. Grun, V.Ganesh, A. Khare, N. Dutt, A. Nicolau. EXPRESSION: a Language for Architecture Exploration through Compiler/Simulator Retargetability. Design, Automation and Test in Europe Conference and Exhibition, Munich, 1999: 485~490
21 S. Pees, A. Hoffmann, H. Meyr. Retargetable Compiled Simulation of Embedded Processors Using a Machine Description Language. ACM Transaction on Design Automation of Electronic Systems. 2000, 5(4): 815~834
22 Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr. LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architecture. Design Automation Conference, New Orleans, 1999: 933~938
23 R. Leupers et al. Generation of Interpretive and Compiled Instruction Set Simulators. Asia South Pacific Design Automation Conference, WanChai, 1999: 339~342
24 W.S. Mong et al. A Retargetable Micro-architecture Simulator. Conference on Design Automation, Anaheim California, 2003: 752~757
25 R.Leupers, P.Marwedel. Retargetable Code Generation Based on Structural Processor Description. Design Automation for Embedded Systems. 1998, 3(1): 75~108
26 Mehrdad Reashadi, Nikhil Bansal, Prabhat Mishra, Nikil Dutt. An Efficient Retargetable Framework for Instruction-Set Simulation. International Symposium on Hardware/Software Co-design and System Synthesis, California, 2003: 13~18
27 Francesco Papariello, Gabriele Luculli. Optimization of a Retargetable Functional Simulator for Embedded Processors. Annual IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, Lund, 2002: 203~210
28 Vojin Zivojnvic, Steven Tjiang, Heinrich Meyr. Compiled Simulation of Programmable DSP Architectures. IEEE Workshop on VLSI Signal Processing, Sakai Japan, 1995: 187~196
29 G. Braun, A. Hoffmann, A.Nohl, H. Meyr. Using static Scheduling Techniques for the Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description. International Symposium on System Synthesis, Montreal Canada, 2001: 57~62
30 V. Zivojaovc, A. Ropers, H.Meyr. Fast simulation of the TI TMS320C54X DSP. International Conference on Signal Processing Application and Technology, San Diego, 1997: 995~999
31 E. Witchel, M. Rosenblum. Embra: Fast and Flexible Machine Simulation. SIGMETRICS Conference on Measurement and Modeling of Computer Systems, Philadelphia, 1996: 68~79
32 B. Cmelik, D.Keppel. Shade: a Fast Instruction-Set Simulator for Execution Profiling. ACM SIGMETRICS Perform. 1994, 22(1): 128~137
33 E. Schnarr, M.D. Hill, J.R. Larus. Facile: a Language and Compiler for High-Performance Processor Simulators. International Conference on Program Languages and Design Implementation, Santa Cruz California, 1998: 321~331
34 M. Reshadi et al. Instruction-Set Compiled Simulation: A Technique for Fast Flexible Instruction Set Simulation. Design Automation Conference, Anaheim California, 2003: 758~763
35 Mehrdad Reshadi, Nikil Dutt. Reducing Compilation Time Overhead in Compiled Simulators. International Conference on Computer Design, San Jose California, 2003: 151~153
36 Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo.Optimization for Compiled Simulation Using Instruction Type Information. Symposium on Computer Architecture and High Performance Computing, Foz do Iguacu Brazil, 2004: 74~81
37 Moo-Kyoung Chung, Chong-Min Kyung. Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time. IEEE International Workshop on Rapid System Prototyping, Geneva Switzerland, 2004: 38~44
38 Wai Sum Mong, Jianwen Zhu. Dynamosim: A Trace-based Dynamically Compiled Instruction Set Simulator. IEEE/ACM International Conference on Computer Aided Design, San Jose California, 2004: 131~136
39 Candice Bechem, Jonathan Combs, Noppanunt, Utamaphethai, Bryan Black, R.D. Shawn Blanton, John Paul Shen. An Integrated Functional Performace Simulaotr. IEEE Micro. 1999, (1): 2~11
40 马忠梅, 马广云, 徐英慧, 田泽. ARM 嵌入式处理器结构与应用基础. 北京航空航天大学出版社, 2002: 20~25
41 Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr. A Universal Technique for Fast and Flexible Instruction-set Architecture Simulation. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(12): 1625~1639
42 Rajat Moona. Processor Models for Retargetable Tools. International Workshop on Rapid System Prototyping, Paris, 2000: 34~39
43 M. Bartholomeu, S.Rigo, R. Azevedo, G. Araujo. Emulating Operting System Calls in Retargetable ISA Simulators. Technical Report IC-03029, Institute of Computing, University of Campinas, 2003: 10~17
44 M.R. Guthaus, J.S. Ringenberg, D.Ernst, T.M. Austin, T. Mudge, R.B.Brown. Mibench: a Free, Commercially Representative Embedded Benchmark Suite. IEEE Annual Workshop on Workload Characterization, Austin Texas, 2001: 3~14
45 王旭. 计算机指令集仿真器的时间仿真技术研究. 计算机应用与软件. 2005, 22(8): 89~91
2 刘振兴, 李宗福, 刘林辉. ARM 嵌入式技术实践教程. 北京航空航天大学出版社, 2005: 3~20
3 刑文峰, 姚庆栋, 史册, 高磊. 一种高速灵活的指令仿真器. 计算机工程. 2004, 30(22): 74~76
4 严迎建, 刘明业. ARMv4 指令集模拟器设计及优化技术. 小型微型计算机系统. 2005, 26(2): 315~317
5 陶峰峰, 付宇卓. DSP 指令集仿真器的设计与实现. 计算机仿真. 2005, 22(9): 225~228
6 钱斌, 付宇卓. 一种基于虚指令集技术构建快速的可重用的指令集仿真器的方法. 计算机工程与应用. 2005, (12): 95~97
7 王晓红, 王旭, 王雷, 金茂忠. 指令集仿真器自动生成技术的研究. 计算机工程与应用. 2003, (2): 129~131
8 D.Burger, T.M.Austin. The Simplescalar Tool Set, Version 2.0. Computer Architecture News. 1997, (2): 13~25
9 S. Sutarwala, P. Paulin, Y. Kumar. Insulin: an Instruction Set Simulation Environment. CHDL, Ottawa Canada, 1993: 355~362
10 Jianwen Zhm, Daniel D. Gajski. A Retargetable, Ultra-fast Instruction Set Simulator. Design Automation and Test in Europe Conference and Exhibition, Munich, 1999: 298~302
11 C. Mills, S. C. Ahalt, J. Fowler. Compiled Instruction Set Simulation. Software-Practice Exper. 1991, 21(8): 877~889
12 Z. Barzilai et al. HSS-A high-speed simulator. IEEE Transaction on Computer-Aided Design. 1987, 6(4): 601~616
13 Peter M. Maurer. Is Compiled Simulation Really Faster than Interpretive Simulation. International Conference on VLSI Design, Bangalore India, 1996: 303~306
14 N. Ramsey, M.F. Fernandez. Specifying Representations of Machine Instruction.ACM Transaction of Programming Languages and Systems. 1997, 19(3): 492~524
15 A. Fauth, J.Van Praet, M. Freericks. Describing Instruction Set Processors Using nML. European Design and Test Conference, Paris, 1995: 503~507
16 A. Fauth. Beyond Tool-Specific Machine Description. Code Generation for Embedded Processors. 1997, (5): 138~152
17 G. Hadjiyiannis, S. Hanono, S. Devadas. ISDL: an Instruction Set Description Language for Retargetability. Design Automation Conference, Anaheim California, 1997: 299~302
18 S. Chandra, R. Moona. Retargetable Functional Simulator Using High Level Processor Models. International Conference on VLSI Design, Calcutta, 2000: 424~429
19 V.Rajesh. A Generic Approach to Performance Modeling and Its Application to Simulator Generator. Master’s thesis, Department of Computer Science and Engineering, Indian Institute of Technology Kanpur. 1998: 13~30
20 A. Halambi, P. Grun, V.Ganesh, A. Khare, N. Dutt, A. Nicolau. EXPRESSION: a Language for Architecture Exploration through Compiler/Simulator Retargetability. Design, Automation and Test in Europe Conference and Exhibition, Munich, 1999: 485~490
21 S. Pees, A. Hoffmann, H. Meyr. Retargetable Compiled Simulation of Embedded Processors Using a Machine Description Language. ACM Transaction on Design Automation of Electronic Systems. 2000, 5(4): 815~834
22 Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr. LISA-Machine Description Language for Cycle-Accurate Models of Programmable DSP Architecture. Design Automation Conference, New Orleans, 1999: 933~938
23 R. Leupers et al. Generation of Interpretive and Compiled Instruction Set Simulators. Asia South Pacific Design Automation Conference, WanChai, 1999: 339~342
24 W.S. Mong et al. A Retargetable Micro-architecture Simulator. Conference on Design Automation, Anaheim California, 2003: 752~757
25 R.Leupers, P.Marwedel. Retargetable Code Generation Based on Structural Processor Description. Design Automation for Embedded Systems. 1998, 3(1): 75~108
26 Mehrdad Reashadi, Nikhil Bansal, Prabhat Mishra, Nikil Dutt. An Efficient Retargetable Framework for Instruction-Set Simulation. International Symposium on Hardware/Software Co-design and System Synthesis, California, 2003: 13~18
27 Francesco Papariello, Gabriele Luculli. Optimization of a Retargetable Functional Simulator for Embedded Processors. Annual IEEE International Conference and Workshop on the Engineering of Computer-Based Systems, Lund, 2002: 203~210
28 Vojin Zivojnvic, Steven Tjiang, Heinrich Meyr. Compiled Simulation of Programmable DSP Architectures. IEEE Workshop on VLSI Signal Processing, Sakai Japan, 1995: 187~196
29 G. Braun, A. Hoffmann, A.Nohl, H. Meyr. Using static Scheduling Techniques for the Retargeting of High Speed, Compiled Simulators for Embedded Processors from an Abstract Machine Description. International Symposium on System Synthesis, Montreal Canada, 2001: 57~62
30 V. Zivojaovc, A. Ropers, H.Meyr. Fast simulation of the TI TMS320C54X DSP. International Conference on Signal Processing Application and Technology, San Diego, 1997: 995~999
31 E. Witchel, M. Rosenblum. Embra: Fast and Flexible Machine Simulation. SIGMETRICS Conference on Measurement and Modeling of Computer Systems, Philadelphia, 1996: 68~79
32 B. Cmelik, D.Keppel. Shade: a Fast Instruction-Set Simulator for Execution Profiling. ACM SIGMETRICS Perform. 1994, 22(1): 128~137
33 E. Schnarr, M.D. Hill, J.R. Larus. Facile: a Language and Compiler for High-Performance Processor Simulators. International Conference on Program Languages and Design Implementation, Santa Cruz California, 1998: 321~331
34 M. Reshadi et al. Instruction-Set Compiled Simulation: A Technique for Fast Flexible Instruction Set Simulation. Design Automation Conference, Anaheim California, 2003: 758~763
35 Mehrdad Reshadi, Nikil Dutt. Reducing Compilation Time Overhead in Compiled Simulators. International Conference on Computer Design, San Jose California, 2003: 151~153
36 Marcus Bartholomeu, Rodolfo Azevedo, Sandro Rigo, Guido Araujo.Optimization for Compiled Simulation Using Instruction Type Information. Symposium on Computer Architecture and High Performance Computing, Foz do Iguacu Brazil, 2004: 74~81
37 Moo-Kyoung Chung, Chong-Min Kyung. Improvement of Compiled Instruction Set Simulator by Increasing Flexibility and Reducing Compile Time. IEEE International Workshop on Rapid System Prototyping, Geneva Switzerland, 2004: 38~44
38 Wai Sum Mong, Jianwen Zhu. Dynamosim: A Trace-based Dynamically Compiled Instruction Set Simulator. IEEE/ACM International Conference on Computer Aided Design, San Jose California, 2004: 131~136
39 Candice Bechem, Jonathan Combs, Noppanunt, Utamaphethai, Bryan Black, R.D. Shawn Blanton, John Paul Shen. An Integrated Functional Performace Simulaotr. IEEE Micro. 1999, (1): 2~11
40 马忠梅, 马广云, 徐英慧, 田泽. ARM 嵌入式处理器结构与应用基础. 北京航空航天大学出版社, 2002: 20~25
41 Gunnar Braun, Achim Nohl, Andreas Hoffmann, Oliver Schliebusch, Rainer Leupers, Heinrich Meyr. A Universal Technique for Fast and Flexible Instruction-set Architecture Simulation. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems. 2004, 23(12): 1625~1639
42 Rajat Moona. Processor Models for Retargetable Tools. International Workshop on Rapid System Prototyping, Paris, 2000: 34~39
43 M. Bartholomeu, S.Rigo, R. Azevedo, G. Araujo. Emulating Operting System Calls in Retargetable ISA Simulators. Technical Report IC-03029, Institute of Computing, University of Campinas, 2003: 10~17
44 M.R. Guthaus, J.S. Ringenberg, D.Ernst, T.M. Austin, T. Mudge, R.B.Brown. Mibench: a Free, Commercially Representative Embedded Benchmark Suite. IEEE Annual Workshop on Workload Characterization, Austin Texas, 2001: 3~14
45 王旭. 计算机指令集仿真器的时间仿真技术研究. 计算机应用与软件. 2005, 22(8): 89~91
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