亚微米MOS器件的热载流子效应研究
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摘要
随着微电子技术的迅速发展,MOS器件特征尺寸不断按比例减小,导致热载流子效应日益严重。近三十年来,MOS器件热载流子效应的研究已经成为了集成电路可靠性问题的重要研究课题。本论文中,根据MOS器件热载流子退化的基本过程,对亚微米MOS器件热载流子应力下的缺陷,器件退化特性和物理机制等可靠性问题进行了研究。热载流子退化主要归于电子俘获、空穴俘获和界面态产生。热载流子退化过程非常复杂并且依赖于应力条件、器件结构、栅氧化层质量。
介绍了近年来MOSFET的热载流子效应研究现状以及测量技术,总结了器件会遇到四种类型的热载流子,还详细讨论了N沟道和P沟道MOS器件热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种应力条件的关系。并且对界面陷阱和氧化层电荷的产生机制做进一步研究。
针对于从加工工艺上提高热载流子注入效应,从改善栅氧化层内的电荷和降低横向电场两个方面出发,一是利用栅氧化工艺来提高栅氧化层的质量,另一个是利用LDD工艺来降低横向电场。实验结果显示在氧化后热退火掺入氮元素可以有效的减少热载流子的注入效应,LDD结构通过两条途径来抑制热载流子效应:弱化漏端电场和使得漏端最大电场远离栅极。
One of the most critical problems facing the aggressive downscaling of CMOS transistors is the reliability due to hot-carrier effects. This thesis attempts to provide accurate reliability characterization and deep understanding of the hot-carrier degradation mechanism of Sub-Micron MOS. Carrier degradation mainly due to electron and hole capture and interface states generated. Hot carrier degradation process is very complex, and depends on the stress conditions, device structure, gate oxide quality.
We introduced hot carrier effect MOSFET current research and measurement techniques in recent years, Summarizes the device will encounter four types of hot carrier, also discussed the relations between generation and injection of channel hot carriers and three kinds of main bias conditions : the high voltage , the medium voltage and the low voltage are investigated . Further study for interface traps and oxide charge generation mechanism.
Processing technology for the increase from the hot carrier injection effect, Improve the gate oxide layer from the charge and reduce the transverse electric field should follow two ways: First, they use technology to improve gate oxide quality of gate oxide, another is the use of LDD process to reduce the transverse electric field. Experimental results show that incorporation of oxidized nitrogen thermal annealing can effectively reduce the hot carrier injection effects, LDD structure of two ways to suppress hot carrier effect: Weaken the drain side electric field and makes the maximum electric field away from the drain-side gate
介绍了近年来MOSFET的热载流子效应研究现状以及测量技术,总结了器件会遇到四种类型的热载流子,还详细讨论了N沟道和P沟道MOS器件热载流子的产生和注入以及与器件工作在高栅压、中栅压和低栅压三种应力条件的关系。并且对界面陷阱和氧化层电荷的产生机制做进一步研究。
针对于从加工工艺上提高热载流子注入效应,从改善栅氧化层内的电荷和降低横向电场两个方面出发,一是利用栅氧化工艺来提高栅氧化层的质量,另一个是利用LDD工艺来降低横向电场。实验结果显示在氧化后热退火掺入氮元素可以有效的减少热载流子的注入效应,LDD结构通过两条途径来抑制热载流子效应:弱化漏端电场和使得漏端最大电场远离栅极。
One of the most critical problems facing the aggressive downscaling of CMOS transistors is the reliability due to hot-carrier effects. This thesis attempts to provide accurate reliability characterization and deep understanding of the hot-carrier degradation mechanism of Sub-Micron MOS. Carrier degradation mainly due to electron and hole capture and interface states generated. Hot carrier degradation process is very complex, and depends on the stress conditions, device structure, gate oxide quality.
We introduced hot carrier effect MOSFET current research and measurement techniques in recent years, Summarizes the device will encounter four types of hot carrier, also discussed the relations between generation and injection of channel hot carriers and three kinds of main bias conditions : the high voltage , the medium voltage and the low voltage are investigated . Further study for interface traps and oxide charge generation mechanism.
Processing technology for the increase from the hot carrier injection effect, Improve the gate oxide layer from the charge and reduce the transverse electric field should follow two ways: First, they use technology to improve gate oxide quality of gate oxide, another is the use of LDD process to reduce the transverse electric field. Experimental results show that incorporation of oxidized nitrogen thermal annealing can effectively reduce the hot carrier injection effects, LDD structure of two ways to suppress hot carrier effect: Weaken the drain side electric field and makes the maximum electric field away from the drain-side gate
引文
[1] S. K. Lai,“Two-carrier nature of interface-state generation in hole trapping and radiation damage,”Appl. Phys. Lett., 1981. vol. 39, no. 1, pp. 58–60.
[2] J.Wang-Ratkovic, C.R.Lacoe, P.K.MacWilliams, M.Song, S.Brown, and G.Yabiku,“New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures,”Microelectronics and Reliability, 1997, vol. 37, pp.1747-1754.
[3] E.Li, E.Rosenbaum, J.Tao, P.Fang,“Projecting lifetime of deep submicron MOSFETs,”IEEE Transactions on Electron Devices, 2001, vol. 48, pp. 671-678.
[4] E.Li, E.Rosenbaum, J.Tao, G.C.-F.Yeap, M.-R.Lin, P.Fang,“Hot carrier effects in nMOSFETs in 0.1μm CMOS technology,”Annual Proceedings - Reliability Physics (Symposium), 1999, pp.253-258.
[5] E.E.King, R.C.Lacoe, J.W-Ratkovic,“Role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices,”Annual Proceedings - Reliability Physics(Symposium), 2000, pp.83-92.
[6] K.Hess, et al.“Impact of nanostructure research on conventional solid-state electronics: the giant isotope effect in hydrogen desorption and CMOS lifetime,”Physica E 3, 1998, pp.1-,.
[7] Y.hirtua, K.Maeguchi, and K.Kanzaki,“Impact of hot electron trapping on half-micron p-MOSFET’s with p+ poly Si gates,”in IEDM Proc., 1986, pp.718-721.
[8] B.S.Doyle and K.R.Mistry,“A lifetime prediction method for hot-carrier degradation in surface-channel p-MOS devices,”IEEE trans. Electron devices, 1990, vol.37, pp.1301-1307.
[9] P.Heremans, J.Witters, G.Groeseneken, H.E.Maes,“Analysis of the charge pumping technique andits application for the evaluation of MOSFET degradation,”IEEE Transactions on Electron Devices, Jul, 1989, v36, n 7, p 1318-1335.
[10] A. Neugroschel, C. T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J.T.111-113.
[20] R. Ghodsi, Y-T Yeow, C. H. Ling, and M. K. Alam,“Arriving at a unified model for hot-carrier degradation in MOSFET’s through gate-to-drain capacitance measurement,”IEEE, ED-41 (12), 1994, pp. 2423-2429.
[21] M.P.Pagey, et al.,“A hydrogen-transport-based interface trap generation model for hot carrier reliability prediction,”IEEE electron device lett. Vol.22, pp.290-292, 2001.
[22] J.Maserjian, and N.Zamani,“Observation of positively charged state generation near the Si/SiO2 interface during fowler-Nordheim tunneling,”J.Vac. Sci. Technol., 1982, vol.20, pp.743-746,
[23] R.Rofan, and C.Hu,“stress-induced oxide leakage,”IEEE Electron device letters, 1991, vol.12,pp.632-634.
[24] P.Olivio, T.Nguyen, and B.Ricco,“High field induced degradation in ultra-thin SiO2 films,”IEEE Trans. Electron devices, 1988, vol.35, pp.2259-2265.
[25] M.Yuichiro, et al., "Suppression of Stress-Induced Leakage current after Fowler-Nordeim stressing by Deuteriun Pyrogenic Oxideation and Deuterated Poly-Si Deposition", IEEE Trans. Electron Devices, July 2002, vol.49, pp1192-1197.
[26] M.Yuichiro, et al., "Experimental Evidence of Hydrogen-Related SILC Generation in Thin Gate Oxide," IEEE IEDM Tech. Dig., 2001, pp129-132
[27] D.Esseni, et al., "On Interface and Oxide Degradation in VLSI MOSFETs-Part I: Deuterium effect in CHE Stress Regime," IEEE Trans. Electron Devices, Feb. 2002, vol.49, pp.247-253.
[28] D.Esseni, et al., "On Interface and Oxide Degradation in VLSI MOSFETs-Part II: Fowler-Nordheim Stress Regime," IEEE Trans. Electron Devices, Feb. 2002, vol.49, pp.254-263.
[29] Goguenheim D., et al.“A Coupled I(V) and Charge-Pumping Analysis of Stress Induced Leakage Currents in 5nm-Thick Gate Oxides,”Microelectronic Engineering, 1997,vol. 36, pp141-144.
[2] J.Wang-Ratkovic, C.R.Lacoe, P.K.MacWilliams, M.Song, S.Brown, and G.Yabiku,“New understanding of LDD NMOS hot-carrier degradation and device lifetime at cryogenic temperatures,”Microelectronics and Reliability, 1997, vol. 37, pp.1747-1754.
[3] E.Li, E.Rosenbaum, J.Tao, P.Fang,“Projecting lifetime of deep submicron MOSFETs,”IEEE Transactions on Electron Devices, 2001, vol. 48, pp. 671-678.
[4] E.Li, E.Rosenbaum, J.Tao, G.C.-F.Yeap, M.-R.Lin, P.Fang,“Hot carrier effects in nMOSFETs in 0.1μm CMOS technology,”Annual Proceedings - Reliability Physics (Symposium), 1999, pp.253-258.
[5] E.E.King, R.C.Lacoe, J.W-Ratkovic,“Role of the spacer oxide in determining worst-case hot-carrier stress conditions for NMOS LDD devices,”Annual Proceedings - Reliability Physics(Symposium), 2000, pp.83-92.
[6] K.Hess, et al.“Impact of nanostructure research on conventional solid-state electronics: the giant isotope effect in hydrogen desorption and CMOS lifetime,”Physica E 3, 1998, pp.1-,.
[7] Y.hirtua, K.Maeguchi, and K.Kanzaki,“Impact of hot electron trapping on half-micron p-MOSFET’s with p+ poly Si gates,”in IEDM Proc., 1986, pp.718-721.
[8] B.S.Doyle and K.R.Mistry,“A lifetime prediction method for hot-carrier degradation in surface-channel p-MOS devices,”IEEE trans. Electron devices, 1990, vol.37, pp.1301-1307.
[9] P.Heremans, J.Witters, G.Groeseneken, H.E.Maes,“Analysis of the charge pumping technique andits application for the evaluation of MOSFET degradation,”IEEE Transactions on Electron Devices, Jul, 1989, v36, n 7, p 1318-1335.
[10] A. Neugroschel, C. T. Sah, K. M. Han, M. S. Carroll, T. Nishida, J.T.111-113.
[20] R. Ghodsi, Y-T Yeow, C. H. Ling, and M. K. Alam,“Arriving at a unified model for hot-carrier degradation in MOSFET’s through gate-to-drain capacitance measurement,”IEEE, ED-41 (12), 1994, pp. 2423-2429.
[21] M.P.Pagey, et al.,“A hydrogen-transport-based interface trap generation model for hot carrier reliability prediction,”IEEE electron device lett. Vol.22, pp.290-292, 2001.
[22] J.Maserjian, and N.Zamani,“Observation of positively charged state generation near the Si/SiO2 interface during fowler-Nordheim tunneling,”J.Vac. Sci. Technol., 1982, vol.20, pp.743-746,
[23] R.Rofan, and C.Hu,“stress-induced oxide leakage,”IEEE Electron device letters, 1991, vol.12,pp.632-634.
[24] P.Olivio, T.Nguyen, and B.Ricco,“High field induced degradation in ultra-thin SiO2 films,”IEEE Trans. Electron devices, 1988, vol.35, pp.2259-2265.
[25] M.Yuichiro, et al., "Suppression of Stress-Induced Leakage current after Fowler-Nordeim stressing by Deuteriun Pyrogenic Oxideation and Deuterated Poly-Si Deposition", IEEE Trans. Electron Devices, July 2002, vol.49, pp1192-1197.
[26] M.Yuichiro, et al., "Experimental Evidence of Hydrogen-Related SILC Generation in Thin Gate Oxide," IEEE IEDM Tech. Dig., 2001, pp129-132
[27] D.Esseni, et al., "On Interface and Oxide Degradation in VLSI MOSFETs-Part I: Deuterium effect in CHE Stress Regime," IEEE Trans. Electron Devices, Feb. 2002, vol.49, pp.247-253.
[28] D.Esseni, et al., "On Interface and Oxide Degradation in VLSI MOSFETs-Part II: Fowler-Nordheim Stress Regime," IEEE Trans. Electron Devices, Feb. 2002, vol.49, pp.254-263.
[29] Goguenheim D., et al.“A Coupled I(V) and Charge-Pumping Analysis of Stress Induced Leakage Currents in 5nm-Thick Gate Oxides,”Microelectronic Engineering, 1997,vol. 36, pp141-144.
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