多核平台上支持推测并行化的事务存储体系结构性能优化
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摘要
随着多核平台的普及,如何利用多核加速串行应用的执行已成为学术界和工业界共同关注的热点研究问题。而传统的显式锁同步机制自身就有着高复杂性、易错性和性能保守等天然缺陷,从根本上限制了并行程序的可扩展性和编程效率,也限制了对多核资源的充分利用。为了开发更多的多核结构上可利用的线程级并行性,利用事务存储(Transactional Memory, TM)技术来解决并行程序正确性维护给并行编程带来的复杂性和对性能的制约问题,已成为学术界和工业界的共识。本文从有效开发应用中的线程级并行性入手,着眼于高效能、易编程和可兼容这三个目标,通过软硬件协同的优化方式对支持推测并行化的多核事务存储体系结构展开深入研究,使之既能提高多核芯片片上计算资源的有效利用率,又能有效降低并行编程难度,平滑移植传统应用软件。
本文从线程划分和线程执行两个方面,对软硬件协同支持推测并行化的多核事务存储体系结构性能优化开展了深入系统的研究,涉及结构模型、编程模型、性能分析模型、离线剖析指导线程划分机制和在线剖析指导线程执行机制等方面的内容。主要研究内容和成果包括：(1)对两种主流线程级推测并行技术的发展趋势进行了详细而深入的调研,通过对其软硬件支持机制的分析与比较,提出了一种新型的软硬件协同支持推测并行化的多核事务存储体系结构设汁方案。该系统在线程划分中采用软件线程级推测技术思想,而在线程执行时采用硬件事务存储技术支持,并通过离线剖析和在线剖析技术来协同各种软硬件因素,达到了同时提高程序性能和降低并行编程难度的双重目标。(2)在软件线程划分方面,从简化并行编程和提高并行执行性能的优化角度出发,提出了一套线程级推测并行性的判定准则、研究方法和剖析机制,确定了利用离线剖析技术来实现基于事务存储的线程划分方案。并依据该机制设计并实现了一套线程级推测并行性离线剖析工具集OpenPro。(3)利用OpenPro工具集,对桌面应用、多媒体应用和高性能计算应用中影响线程级推测并行性的关键因素进行剖析,从应用本身并行潜能的角度进行探讨,获得了诸如单个程序仅能有效利用16核的计算资源是当前多核技术路线的拐点等一些重要认识。(4)在线程执行支持机制方面,从可扩展性好和易于硬件实现这两个优化目标出发,提出了一种支持优先级判定的基于目录的高速缓存一致性协议,并在此基础上设计和完成了一种利用运行时库机制同时支持线程级推测和事务存储语义的分布式可扩展多核事务存储处理器PTT硬件模拟器。该处理器设计突破了以往类似方案中总线等集中式结构对硬件系统可扩展性的限制,同时实现了可扩展性好和易于硬件设计实现的目标；而这套采用积极版本管理和积极检测机制的分布式硬件事务存储机制会自动维护硬件系统的一致性,极大地减少了程序员在进行并行程序设计时的繁杂工作和复杂程度。这对于普及并行程序设计,提高并行程序生产力都有着非常重要的意义。(5)提出了一种针对线程级推测并行技术的PCL性能分析模型,并依据该模型提出了将在线剖析技术引入PTT硬件模拟平台的最终优化方案。同时通过对PTT系统多种软硬件手段实现机制的分析与协同,分别从正确性、有效性和灵活可配置性三个层次对其进行了充分的评测和分析。
本文的研究工作获得了如下一些重要的认识：(1)将线程级推测技术与事务存储技术结合起来,通过软硬件因素的合理协调,可以有效地开发出串行程序中潜在的线程级并行性,同时有效地降低并行编程的难度,极大地提高并行程序设计生产力。(2)在目前以传统超标量单核构造多核芯片的技术路线下,着眼于同时兼顾硬件的有效利用率和尽可能挖掘程序中固有的并行性,在加速单个串行应用时,部分依赖严重的应用(如SPEC和一些依赖严重的科学计算程序等)采用2-4核就已经足够；而多数多媒体应用和高性能计算应用采用8-16核来加速比较合适；一些特别适合的应用则可以有效利用64-128核及以上的计算资源。(3)虽然现在线程级推测并行技术在桌面应用这样一些程序中数据依赖严重的应用中效果不佳,但在部分拥有大计算量、推测线程粒度适中并且存在模糊依赖的多媒体和高性能计算应用中还是适宜采用的。线程级推测并行技术最大的优势是其兼容性与易编程性,只要在这两点上做好文章,实现多数经典应用软件到多核平台上的平滑移植,进一步解放程序员,线程级推测并行技术就会在体系结构研究中拥有重要的一席之地。
本文的研究工作和结果可用于指导共享存储的多核芯片体系结构及其并行编程环境的设计,以尽可能小的并行程序设计难度、系统软件复杂性和系统硬件代价,尽可能多地从串行程序中开发出多核芯片上可利用的线程级并行性。
With the popularity of multicore platforms, how to make use of multicore computing resources to accelerate the traditional serial applications has become a common concern problem. The traditional explicit lock synchronization mechanism has its natural defects in the complexity, fallibility and conservative performance, so that fundamentally limits the scalability and efficiency of parallel programing, but also limits the full use of the multicore resources. In order to develop more thread-level parallelism from multi-core architecture, using Transactional Memory (TM) technology to solve the traditional parallel programming complexity and its constraints on performance, has become academia and industry consensus. This paper takes how to develop effective thread-level parallelism from applications as the point of departure, aims at three goals of high-performance, easy programming and compatibility, and coordinates hardware and software to make depth research on multicore transactional memory architecture supporting speculative parallelization. It can raise the effective utilization of multicore computing resources, reduce the difficulty of parallel programming effectively, and make the smooth migration of traditional applications.
This dissertation carries out in-depth systematic study in the views of both thread partition and thread execution in the multicore transactional memory architecture supporting speculative parallelization, involving structural model, programming model, performance analysis model, thread partition guided by offline profiling and thread execution guided by online profiling aspects. The major research contributions include:(1) based on a survey on two main parallel speculative thread-level parallel technological trends in detail and a comparison between their software and hardware support mechanism, a novel hardware and software co-designed multicore transactional memory architecture is proposed. It uses software thread-level speculation ideas to guide the thread partition and hardware transactional memory technology to support thread execution, coordinates hardware and software elements by offline and online profiling technology, and achieves the goals of both improving applications'performance and reducing the parallel programming's difficulty. (2) In the optimization aspect of software thread partition, aiming at simpler parallel programming and improving the parallel execution performance, a set of criteria, research methods and profiling mechnisms for speculative thread-level parallelism are proposed. An offline profiling guiede thread partition scheme for transactional memory is determined. And a set of offline profling tools named Openpro is developed to exploring the thread-level parallelism based on the criteria. (3) It analyzes the key thread-level parallelism performance impacting factors in desktop, media and HPC fields and makes an investigation from the view of the applications' own parallelism potential. (4) In the aspect of hardware thread execution, aiming at good scalability and easy to implement, a priority determination supporting directory-based cache coherence protocol is proposed. Based on this, a scalable distributed multicore transactional memory processor hardware simulator PTT is developed. It can support both thread-level speculation and transctional memory semantics by run-time libraries supporting mechanisms. This design breakthrough the limitations on hardware scalability in the past brought by the centralized structure mechanisms, such as bus architecture, and achieve both of the good scalability and easy-to-hardware-design goals. It uses positive version management and active violation detection mechanism in this distribute transactional memory system, so that the system will automatically maintain the consistency of the hardware system and greatly reduce the complication and complexity of parallel programming work. It has very important meaning on improving parallel programming productivity and making parallel programming popular. (5) A speculative thread-level parallelism performance analysis model named PCL is proposed. According to the PCL model, the PTT system brings the online profiling techonology into the platform. At the same time, coordinating a variety of hardware and software mechanisms, a final evaluation and analysis on the PTT system is carried out from three levels:accuracy, effectiveness and flexibility.
Based on the work of this dissertation, some important conclusions are drawn as following:(1) it's reasonable to combine the benefits of the thread-level speculation and transactional memory technology through coordination of hardware and software mechanisms. It can effectively develop the potential thread-level parallelism form the serial program while effectively reduce the difficulty of parallel programming, and greatly improve parallel programming productivity. (2) In the present multicore chips' technology roadmap that they were made by some single superscalar cores, aiming at both of the effective utilization of hardware and exploring inherent parallelism as much as possible, the desktop applications can use 2 cores computing resources efficiently while lots of multimedia and HPC applications are suitable to use 8-16 cores'computing resources. And some particularly suitable applications can use 64-128 cores'computing resources effectively. (3) It showed that although speculative thread-level parallel technology didn't perform well in the desktop applications that have serious data dependence problem, it's suitable for most multimedia and HPC applications that have large calculation, moderate thread size, and fuzzy dependence but easy to resolve. The biggest advantage of speculative thread-level parallel technology is its compatibility and easy programming, making good use of the two points, the speculative thread-level parallel technology can have an important place in the computer architecture research.
All the works in this dissertation can be used to guide the designing of parallel programming model and compiler on the shared memory multicore processor architecture, to be helpful for the designing of high-performance on-chip multicore architecture, and to expose more parallelism from application with less hardware, software complexity and less hardness in parallel programming. v
本文从线程划分和线程执行两个方面,对软硬件协同支持推测并行化的多核事务存储体系结构性能优化开展了深入系统的研究,涉及结构模型、编程模型、性能分析模型、离线剖析指导线程划分机制和在线剖析指导线程执行机制等方面的内容。主要研究内容和成果包括：(1)对两种主流线程级推测并行技术的发展趋势进行了详细而深入的调研,通过对其软硬件支持机制的分析与比较,提出了一种新型的软硬件协同支持推测并行化的多核事务存储体系结构设汁方案。该系统在线程划分中采用软件线程级推测技术思想,而在线程执行时采用硬件事务存储技术支持,并通过离线剖析和在线剖析技术来协同各种软硬件因素,达到了同时提高程序性能和降低并行编程难度的双重目标。(2)在软件线程划分方面,从简化并行编程和提高并行执行性能的优化角度出发,提出了一套线程级推测并行性的判定准则、研究方法和剖析机制,确定了利用离线剖析技术来实现基于事务存储的线程划分方案。并依据该机制设计并实现了一套线程级推测并行性离线剖析工具集OpenPro。(3)利用OpenPro工具集,对桌面应用、多媒体应用和高性能计算应用中影响线程级推测并行性的关键因素进行剖析,从应用本身并行潜能的角度进行探讨,获得了诸如单个程序仅能有效利用16核的计算资源是当前多核技术路线的拐点等一些重要认识。(4)在线程执行支持机制方面,从可扩展性好和易于硬件实现这两个优化目标出发,提出了一种支持优先级判定的基于目录的高速缓存一致性协议,并在此基础上设计和完成了一种利用运行时库机制同时支持线程级推测和事务存储语义的分布式可扩展多核事务存储处理器PTT硬件模拟器。该处理器设计突破了以往类似方案中总线等集中式结构对硬件系统可扩展性的限制,同时实现了可扩展性好和易于硬件设计实现的目标；而这套采用积极版本管理和积极检测机制的分布式硬件事务存储机制会自动维护硬件系统的一致性,极大地减少了程序员在进行并行程序设计时的繁杂工作和复杂程度。这对于普及并行程序设计,提高并行程序生产力都有着非常重要的意义。(5)提出了一种针对线程级推测并行技术的PCL性能分析模型,并依据该模型提出了将在线剖析技术引入PTT硬件模拟平台的最终优化方案。同时通过对PTT系统多种软硬件手段实现机制的分析与协同,分别从正确性、有效性和灵活可配置性三个层次对其进行了充分的评测和分析。
本文的研究工作获得了如下一些重要的认识：(1)将线程级推测技术与事务存储技术结合起来,通过软硬件因素的合理协调,可以有效地开发出串行程序中潜在的线程级并行性,同时有效地降低并行编程的难度,极大地提高并行程序设计生产力。(2)在目前以传统超标量单核构造多核芯片的技术路线下,着眼于同时兼顾硬件的有效利用率和尽可能挖掘程序中固有的并行性,在加速单个串行应用时,部分依赖严重的应用(如SPEC和一些依赖严重的科学计算程序等)采用2-4核就已经足够；而多数多媒体应用和高性能计算应用采用8-16核来加速比较合适；一些特别适合的应用则可以有效利用64-128核及以上的计算资源。(3)虽然现在线程级推测并行技术在桌面应用这样一些程序中数据依赖严重的应用中效果不佳,但在部分拥有大计算量、推测线程粒度适中并且存在模糊依赖的多媒体和高性能计算应用中还是适宜采用的。线程级推测并行技术最大的优势是其兼容性与易编程性,只要在这两点上做好文章,实现多数经典应用软件到多核平台上的平滑移植,进一步解放程序员,线程级推测并行技术就会在体系结构研究中拥有重要的一席之地。
本文的研究工作和结果可用于指导共享存储的多核芯片体系结构及其并行编程环境的设计,以尽可能小的并行程序设计难度、系统软件复杂性和系统硬件代价,尽可能多地从串行程序中开发出多核芯片上可利用的线程级并行性。
With the popularity of multicore platforms, how to make use of multicore computing resources to accelerate the traditional serial applications has become a common concern problem. The traditional explicit lock synchronization mechanism has its natural defects in the complexity, fallibility and conservative performance, so that fundamentally limits the scalability and efficiency of parallel programing, but also limits the full use of the multicore resources. In order to develop more thread-level parallelism from multi-core architecture, using Transactional Memory (TM) technology to solve the traditional parallel programming complexity and its constraints on performance, has become academia and industry consensus. This paper takes how to develop effective thread-level parallelism from applications as the point of departure, aims at three goals of high-performance, easy programming and compatibility, and coordinates hardware and software to make depth research on multicore transactional memory architecture supporting speculative parallelization. It can raise the effective utilization of multicore computing resources, reduce the difficulty of parallel programming effectively, and make the smooth migration of traditional applications.
This dissertation carries out in-depth systematic study in the views of both thread partition and thread execution in the multicore transactional memory architecture supporting speculative parallelization, involving structural model, programming model, performance analysis model, thread partition guided by offline profiling and thread execution guided by online profiling aspects. The major research contributions include:(1) based on a survey on two main parallel speculative thread-level parallel technological trends in detail and a comparison between their software and hardware support mechanism, a novel hardware and software co-designed multicore transactional memory architecture is proposed. It uses software thread-level speculation ideas to guide the thread partition and hardware transactional memory technology to support thread execution, coordinates hardware and software elements by offline and online profiling technology, and achieves the goals of both improving applications'performance and reducing the parallel programming's difficulty. (2) In the optimization aspect of software thread partition, aiming at simpler parallel programming and improving the parallel execution performance, a set of criteria, research methods and profiling mechnisms for speculative thread-level parallelism are proposed. An offline profiling guiede thread partition scheme for transactional memory is determined. And a set of offline profling tools named Openpro is developed to exploring the thread-level parallelism based on the criteria. (3) It analyzes the key thread-level parallelism performance impacting factors in desktop, media and HPC fields and makes an investigation from the view of the applications' own parallelism potential. (4) In the aspect of hardware thread execution, aiming at good scalability and easy to implement, a priority determination supporting directory-based cache coherence protocol is proposed. Based on this, a scalable distributed multicore transactional memory processor hardware simulator PTT is developed. It can support both thread-level speculation and transctional memory semantics by run-time libraries supporting mechanisms. This design breakthrough the limitations on hardware scalability in the past brought by the centralized structure mechanisms, such as bus architecture, and achieve both of the good scalability and easy-to-hardware-design goals. It uses positive version management and active violation detection mechanism in this distribute transactional memory system, so that the system will automatically maintain the consistency of the hardware system and greatly reduce the complication and complexity of parallel programming work. It has very important meaning on improving parallel programming productivity and making parallel programming popular. (5) A speculative thread-level parallelism performance analysis model named PCL is proposed. According to the PCL model, the PTT system brings the online profiling techonology into the platform. At the same time, coordinating a variety of hardware and software mechanisms, a final evaluation and analysis on the PTT system is carried out from three levels:accuracy, effectiveness and flexibility.
Based on the work of this dissertation, some important conclusions are drawn as following:(1) it's reasonable to combine the benefits of the thread-level speculation and transactional memory technology through coordination of hardware and software mechanisms. It can effectively develop the potential thread-level parallelism form the serial program while effectively reduce the difficulty of parallel programming, and greatly improve parallel programming productivity. (2) In the present multicore chips' technology roadmap that they were made by some single superscalar cores, aiming at both of the effective utilization of hardware and exploring inherent parallelism as much as possible, the desktop applications can use 2 cores computing resources efficiently while lots of multimedia and HPC applications are suitable to use 8-16 cores'computing resources. And some particularly suitable applications can use 64-128 cores'computing resources effectively. (3) It showed that although speculative thread-level parallel technology didn't perform well in the desktop applications that have serious data dependence problem, it's suitable for most multimedia and HPC applications that have large calculation, moderate thread size, and fuzzy dependence but easy to resolve. The biggest advantage of speculative thread-level parallel technology is its compatibility and easy programming, making good use of the two points, the speculative thread-level parallel technology can have an important place in the computer architecture research.
All the works in this dissertation can be used to guide the designing of parallel programming model and compiler on the shared memory multicore processor architecture, to be helpful for the designing of high-performance on-chip multicore architecture, and to expose more parallelism from application with less hardware, software complexity and less hardness in parallel programming. v
引文
陈嘉.2006.一种基于事务存储模型多核结构上的编程模型设计和实现[D].硕士论文,中国科学技术大学,合肥.
郭锐.2009.支持推测并行化的可扩展事务存储体系结构设计与性能评价[D].硕士论文,中国科学技术大学,合肥.
何裕南.2006.一个支持事务存储的多核处理器结构设计[D].硕士论文,中国科学技术大学,合肥.
梁博.2007.多核结构上的线程级推测关键技术研究[D].博士论文,中国科学技术大学,合肥.
刘圆.2007.多核结构上高效的线程级推测及事务执行模型研究[D].博士论文,中国科学技术大学,合肥.
Microbench website www.cs.utexas.edu/cart/code/microbench.tgz
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