网络化MPSoC高能效设计技术研究
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摘要
片上系统(Systern-on-Chip，SoC)已广泛应用于网络通信、信号处理、多媒体等嵌入式电子产品中，但单处理器SoC无法满足应用领域日益增长的计算能力需求，MPSoC(Multiprocessor SoC)成为高性能嵌入式系统的实现平台。随着集成电路技术的快速发展，单个芯片上的晶体管数目将会达到数十亿个，可以集成数百个异构的IP核，传统的总线结构在可扩展性、通信效率、功耗等方面不再适用，通信成为MPSoC突出的性能瓶颈。片上网络(Network-on-Chip，NoC)作为解决复杂的片上多核通信问题的全新设计模式，为嵌入式系统设计方法学带来了新的机遇和挑战。同时，为延长电池使用时间、降低芯片封装和冷却费用、提高系统可靠性，高能效已成为基于NoC的MPSoC(简称网络化MPSoC)设计中的首要因素。
本文首先总结了嵌入式系统的设计方法，分析了NoC的设计特点，针对可重用的MPSoC／NoC平台，提出了一种高能效网络化MPSoC的系统级设计流程。在此基础上，面向低成本、硬实时、高性能、高可信的嵌入式应用，采取不同的能耗优化技术，重点解决了以下四个关键问题：(1)MPSoC计算平台的软硬件划分、(2)固网NoC平台的映射、(3)硬网NoC平台的路由与链路电压分配和(4)软网NoC平台的软硬件协同综合。
本文主要的贡献与创新之处包括：
(1)针对基于可重用组件的MPSoC软硬件划分问题，提出了一种采用自动波竞争神经网络的优化算法。首先将MPSoC软硬件划分转化为图论中的多约束最短路径问题，然后对神经网络中的自动波机制重新进行了设计，从组件库中为每个任务模块选择合适的软件构件或IP核，在系统成本和实时性约束下，使得MPSoC的功耗最优。本算法具有并行化、无参数、易于硬件实现等优点，可获得MPSoC软硬件划分问题的最优解。
(2)针对二维网格NoC中通信时延受限的低能耗映射问题，提出了一种改进的禁忌搜索算法TSNM。TSNM基于集中和分散机制，将RobustTabu Search与COHX交叉操作融合，具有搜索效率高和优化性能好的优点，适合于求解大规模NoC映射问题。
(3)针对树拓扑NoC中通信时延受限的低能耗映射问题，提出了一种递归的二路划分算法RPM。RPM采用分而治之策略，使用改进后的Kemighan-Lin算法实现IP核通信任务图的最小割划分，在较短的运行时间内获得了性能优异的NoC映射解，可用于获得高质量的优化结果或NoC设计空间探索的快速内部迭代。
(4)针对链路电压可调整的NoC平台，提出了一种可靠性感知的通信链路能耗优化算法。考虑了低电压对电路瞬时故障率的负面影响，将通信可靠性与能耗折中设计引入到NoC的路由和链路电压分配中，设计了一个新的能效变化率驱动的启发式电压分配算法，与基于禁忌搜索的路由分配相结合，在确保NoC通信可靠性和带宽约束的同时，可以有效降低链路的通信能耗。
(5)针对支持电压岛的层次化NoC平台，提出了一种基于嵌套遗传算法的软硬件协同综合算法。面向可信嵌入式实时MPSoC应用的完整设计流程，通过资源分配、任务指派、聚簇映射、任务调度以及电压调整等设计步骤，可以有效降低NoC系统的计算与通信能耗，实现能耗与可靠性的多目标优化，更适合于异构层次化NoC系统综合。
目前，国内外对MPSoC／NoC设计方法学的研究还处于初步发展阶段，存在许多有待解决的问题。本文提出的网络化MPSoC高能效设计方法和优化算法，为下一代基于NoC的嵌入式多核系统的设计自动化提供了新的技术和思路。
SoCs(System-on-Chips) have been widely applied in embedded electronic devicesfor communication,signal processing and multimedia.Since uniprocessor SoC couldnot satisfy the growing computation requirements of such applications,MPSoC(Multiprocessor SoC) platforms have emerged for high performance embedded systems.With the rapid development of IC technologies,there will be billions of transistors andhundreds of heterogeneous IP cores on a single chip.Due to poor scalability,communiction perfomance and energy efficiency,bus will not suite for MPSoCs,so theinterconnect subsystem will be the bottleneck of such complex MPSoCs.As a newparadigm,NoCs(Network-on-Chips) have been proposed to overcome the complexon-chip multi-core communication problems,providing opportunity and challenges todesign methodology of embedded systems.For the sake of extending the lifetime ofbatteries,reducing the cost of package and cooling,and improving reliability,energyefficiency have been the most important factor of NoC-based MPSoCs.
In this dissertation the design methodology of embedded systems is summarized,and the design methods of NoCs are analyzed.Then a novel system-level design flowfor energy efficient and NoC-based MPSoCs is presented.More precisely,in thefollowing chapters,4 key design problems are identified and solved for embeddedapplications with low cost,hard real-time,high performance and high dependabilityrequirements.These problems include:(1) hardware-software partitioning of MPSoCcomputation platform,(2) IP mapping of firm NoC platform,(3) routing path allocationand links voltage assignment of hard NoC platform,(4) hardware-software co-synthesisof soft NoC platforms.
In this dissertation,the main works and contributions are as follows:
(1) A hardware-software partitioning algorithm using Autowave CompetitionNeural Networks is proposed for MPSoCs based on reusable components.Thepartitioning problem is formulated as a multi-constrained shortest path problem.Theautowaves are designed specially to solve the shortest problems optimally.Finally,eachtask module of the system is allocated a software component or IP core from the components library,such that the power consumption of the MPSoC is minimizedsubject to cost and timing constraints.This algorithm could obtain globally optimalsolutions,and it's parallel and non-parameter.It's easy to implement the neural networkby VLSI.
(2) An improved Tabu Search algorithm,called TSNM,is proposed for low-energymapping problem of 2-D Mesh NoCs subject to communication latency constraints.Based on“intensification and diversification”mechanism,TSNM merges Robust TabuSearch and COHX crossover operator.Experimental results show that TSNM can givebetter quality solutions and smaller searching space,so it is more efficient to solvelarge-scale NoC mapping problems.
(3) A recursive bipartitioning algorithm,called RPM,is proposed for low-energymapping problem of tree based NoCs subject to communication latency constraints.RPM is an efficient divide-and-conquer approach and calls modified Kemighan-Linheuristic to perform mincut partintioning of IP core communication task graphs.Experimental results show that RPM obtains lower energy mapping solutions and it isvery fast.It is suited to both producing excellent results and quick NoC design spaceexploration by tuning the parameter of RPM.
(4) A reliability-aware energy optimization algorithm is proposed for NoC withvoltage scalable links.Considering the effect of reduced voltage on fault rates,thisapproach achieves energy/reliability trade-off when performing routing path allocationand links voltage assignment.A novel energy-efficiency gradient driven heuristic isdeveloped to assign the voltages for the links during Tabu Search based global designspace exploration of routing path allocation.Experimental results show that thepresented method can efficiently guarantee the communication reliability andbandwidth constraints,and obtain significant energy savings of communication links.
(5) A hardware-software co-synthesis algorithm is proposed for voltage islandsbased hierarchical NoC systems.A novel design framework based on iterated GeneticAlgorithm is developed for the complete co-synthesis flow of dependable embeddedreal-time MPSoC applications.The multi-objective optimization techniqueautomatically performs resource allocation,task assignment,cluster mapping,taskscheduling and voltage assignment to trade-off energy and reliability of NoC systems.Experimental results show that the proposed design technique performs significantly better than existing algorithms in both energy minimization and reliability.It is suitedfor system-level synthesis of heterogeneous hierarchical NoCs.
At present,the researches on MPSoC/NoC design methodology are in the stage ofinitial development,and there are many open problems left.The design methods andenergy optimization algorithms presented in this dissertation may provide some newtechniques and ideas to design automation of next-generation embedded multi-coresystems based on NoC.
本文首先总结了嵌入式系统的设计方法，分析了NoC的设计特点，针对可重用的MPSoC／NoC平台，提出了一种高能效网络化MPSoC的系统级设计流程。在此基础上，面向低成本、硬实时、高性能、高可信的嵌入式应用，采取不同的能耗优化技术，重点解决了以下四个关键问题：(1)MPSoC计算平台的软硬件划分、(2)固网NoC平台的映射、(3)硬网NoC平台的路由与链路电压分配和(4)软网NoC平台的软硬件协同综合。
本文主要的贡献与创新之处包括：
(1)针对基于可重用组件的MPSoC软硬件划分问题，提出了一种采用自动波竞争神经网络的优化算法。首先将MPSoC软硬件划分转化为图论中的多约束最短路径问题，然后对神经网络中的自动波机制重新进行了设计，从组件库中为每个任务模块选择合适的软件构件或IP核，在系统成本和实时性约束下，使得MPSoC的功耗最优。本算法具有并行化、无参数、易于硬件实现等优点，可获得MPSoC软硬件划分问题的最优解。
(2)针对二维网格NoC中通信时延受限的低能耗映射问题，提出了一种改进的禁忌搜索算法TSNM。TSNM基于集中和分散机制，将RobustTabu Search与COHX交叉操作融合，具有搜索效率高和优化性能好的优点，适合于求解大规模NoC映射问题。
(3)针对树拓扑NoC中通信时延受限的低能耗映射问题，提出了一种递归的二路划分算法RPM。RPM采用分而治之策略，使用改进后的Kemighan-Lin算法实现IP核通信任务图的最小割划分，在较短的运行时间内获得了性能优异的NoC映射解，可用于获得高质量的优化结果或NoC设计空间探索的快速内部迭代。
(4)针对链路电压可调整的NoC平台，提出了一种可靠性感知的通信链路能耗优化算法。考虑了低电压对电路瞬时故障率的负面影响，将通信可靠性与能耗折中设计引入到NoC的路由和链路电压分配中，设计了一个新的能效变化率驱动的启发式电压分配算法，与基于禁忌搜索的路由分配相结合，在确保NoC通信可靠性和带宽约束的同时，可以有效降低链路的通信能耗。
(5)针对支持电压岛的层次化NoC平台，提出了一种基于嵌套遗传算法的软硬件协同综合算法。面向可信嵌入式实时MPSoC应用的完整设计流程，通过资源分配、任务指派、聚簇映射、任务调度以及电压调整等设计步骤，可以有效降低NoC系统的计算与通信能耗，实现能耗与可靠性的多目标优化，更适合于异构层次化NoC系统综合。
目前，国内外对MPSoC／NoC设计方法学的研究还处于初步发展阶段，存在许多有待解决的问题。本文提出的网络化MPSoC高能效设计方法和优化算法，为下一代基于NoC的嵌入式多核系统的设计自动化提供了新的技术和思路。
SoCs(System-on-Chips) have been widely applied in embedded electronic devicesfor communication,signal processing and multimedia.Since uniprocessor SoC couldnot satisfy the growing computation requirements of such applications,MPSoC(Multiprocessor SoC) platforms have emerged for high performance embedded systems.With the rapid development of IC technologies,there will be billions of transistors andhundreds of heterogeneous IP cores on a single chip.Due to poor scalability,communiction perfomance and energy efficiency,bus will not suite for MPSoCs,so theinterconnect subsystem will be the bottleneck of such complex MPSoCs.As a newparadigm,NoCs(Network-on-Chips) have been proposed to overcome the complexon-chip multi-core communication problems,providing opportunity and challenges todesign methodology of embedded systems.For the sake of extending the lifetime ofbatteries,reducing the cost of package and cooling,and improving reliability,energyefficiency have been the most important factor of NoC-based MPSoCs.
In this dissertation the design methodology of embedded systems is summarized,and the design methods of NoCs are analyzed.Then a novel system-level design flowfor energy efficient and NoC-based MPSoCs is presented.More precisely,in thefollowing chapters,4 key design problems are identified and solved for embeddedapplications with low cost,hard real-time,high performance and high dependabilityrequirements.These problems include:(1) hardware-software partitioning of MPSoCcomputation platform,(2) IP mapping of firm NoC platform,(3) routing path allocationand links voltage assignment of hard NoC platform,(4) hardware-software co-synthesisof soft NoC platforms.
In this dissertation,the main works and contributions are as follows:
(1) A hardware-software partitioning algorithm using Autowave CompetitionNeural Networks is proposed for MPSoCs based on reusable components.Thepartitioning problem is formulated as a multi-constrained shortest path problem.Theautowaves are designed specially to solve the shortest problems optimally.Finally,eachtask module of the system is allocated a software component or IP core from the components library,such that the power consumption of the MPSoC is minimizedsubject to cost and timing constraints.This algorithm could obtain globally optimalsolutions,and it's parallel and non-parameter.It's easy to implement the neural networkby VLSI.
(2) An improved Tabu Search algorithm,called TSNM,is proposed for low-energymapping problem of 2-D Mesh NoCs subject to communication latency constraints.Based on“intensification and diversification”mechanism,TSNM merges Robust TabuSearch and COHX crossover operator.Experimental results show that TSNM can givebetter quality solutions and smaller searching space,so it is more efficient to solvelarge-scale NoC mapping problems.
(3) A recursive bipartitioning algorithm,called RPM,is proposed for low-energymapping problem of tree based NoCs subject to communication latency constraints.RPM is an efficient divide-and-conquer approach and calls modified Kemighan-Linheuristic to perform mincut partintioning of IP core communication task graphs.Experimental results show that RPM obtains lower energy mapping solutions and it isvery fast.It is suited to both producing excellent results and quick NoC design spaceexploration by tuning the parameter of RPM.
(4) A reliability-aware energy optimization algorithm is proposed for NoC withvoltage scalable links.Considering the effect of reduced voltage on fault rates,thisapproach achieves energy/reliability trade-off when performing routing path allocationand links voltage assignment.A novel energy-efficiency gradient driven heuristic isdeveloped to assign the voltages for the links during Tabu Search based global designspace exploration of routing path allocation.Experimental results show that thepresented method can efficiently guarantee the communication reliability andbandwidth constraints,and obtain significant energy savings of communication links.
(5) A hardware-software co-synthesis algorithm is proposed for voltage islandsbased hierarchical NoC systems.A novel design framework based on iterated GeneticAlgorithm is developed for the complete co-synthesis flow of dependable embeddedreal-time MPSoC applications.The multi-objective optimization techniqueautomatically performs resource allocation,task assignment,cluster mapping,taskscheduling and voltage assignment to trade-off energy and reliability of NoC systems.Experimental results show that the proposed design technique performs significantly better than existing algorithms in both energy minimization and reliability.It is suitedfor system-level synthesis of heterogeneous hierarchical NoCs.
At present,the researches on MPSoC/NoC design methodology are in the stage ofinitial development,and there are many open problems left.The design methods andenergy optimization algorithms presented in this dissertation may provide some newtechniques and ideas to design automation of next-generation embedded multi-coresystems based on NoC.
引文
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