数字集成电路测试方法研究
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摘要
数字集成电路功能的不断增加和规模的日益扩大,使集成电路的测试面临着巨大压力,不仅测试生成越来越困难,而且测试应用时间也越来越长,导致测试费用不断提高。而集成电路的测试问题关系到集成电路及相关产品的设计、生产、制造及应用开发等各个领域,因此,如何找到高效率、低成本、满足当前测试需求的数字集成电路测试方法越来越受到人们的广泛关注。本文以数字集成电路测试为背景,针对电路测试所面临的测试生成时间长、故障覆盖率低以及测试应用时间长的问题,分别对数字集成电路测试生成方法、测试质量提高方法和静态测试压缩方法进行了深入研究。
首先,对数字集成电路测试生成过程的关键技术进行了详细分析。建立被测电路的电路模型和故障模型并对被测电路目标故障集进行故障等价归并,精简故障集合,减少测试向量生成过程的计算量；根据电路可测性分析和计算方法,对被测电路进行可测性分析和计算,将计算结果注入电路链表结构,为测试向量生成过程选择最优路径；用并行故障模拟器选出最优的测试向量集合,保证故障覆盖率,提高测试生成效率。
其次,针对数字集成电路测试生成时间长和故障覆盖率低的问题,将性能较好的蚂蚁算法和遗传算法应用于基于模拟的集成电路测试生成过程,缩短测试生成时间；针对基于模拟的测试生成方法所面临的缺乏激活难测故障和传播相应故障响应所必需信息的问题,对电路引入扫描设计测试结构,提出了一种将基于模拟测试生成方法与扫描设计测试结构相结合的有限扫描测试生成方法,在基于模拟的测试生成方法基础上,通过将扫描电路的扫描输入端、扫描选择端和扫描输出端视为电路通用输入输出端,穿透扫描时钟周期和测试时钟周期之间的差异,提高故障覆盖率。国际基准电路实验及比对结果表明,提出方法有效减少了测试生成时间,提高了故障覆盖率。
再次,为了提高有限扫描测试序列对非模型化故障的故障覆盖率和故障隔离率,本文在详细分析现有测试质量评价方法基础上,对其在故障隔离评价方面的不足进行补充和完善。将完善后的测试质量评价方法扩展到有限扫描测试序列质量评价方法,并根据有限扫描测试序列自身特点,提出了两种提高测试质量的方法,通过随机确定测试序列含有的不确定值和修改测试序列内部扫描选择子序列数值的方法提高测试序列质量,基准电路实验结果表明,提出方法有效提高了测试序列对非模型化故障的故障覆盖率和故障隔离率。
最后,针对扫描设计测试结构生成的测试序列长,导致测试应用时间多的问题,对有限扫描测试序列进行了基于向量删除的静态测试压缩,去掉测试序列中的冗余向量；根据有限扫描测试序列的扫描特性,提出一种与基于向量删除静态测试压缩方法相结合的有限扫描静态测试压缩方法,在基于向量删除的静态测试压缩基础上,用较短的有限扫描操作代替较长的全扫描操作或有限扫描操作,合并候选测试向量,引入启发式方法降低计算复杂度,在保证不降低故障覆盖率的前提下,压缩测试序列长度,减少测试应用时间和测试数据存储容量。基准电路实验结果表明,提出方法在保证故障覆盖率不变的前提下,有效减少了有限扫描测试序列的测试应用时间和测试数据存储容量。
The increasing of functions and scale in VLSI made great pressure to VLSI test. Not only the test generation is more and more difficult, but also the test application time becomes longer and longer. This increases the test expense constantly. However, the VLSI test problem relates to designing, producing, manufacturing and application developing of VLSI and other relative products in many fields. Therefore, how to find a high affection, low expense VLSI testing method to fulfill current test need is more and more concentrated by people. According to the problem of test generation time long, fault coverage low and test application time long, this dissertation takes the VLSI testing as background, deeply study the VLSI test generation method, test quality improve method and static test compact method respectively.
First, the critical technologies of VLSI test generation are analyzed in detail. The circuit model and fault model of the circuit under test are established. The fault equivalence is done to the objective fault set to reduce the computation time of test generation procedure. According to the testability analysis and computing method of circuit, the testability of circuit under test is analyzed and computed. The computing result is input to the chain table structure to select the best path of test generation. The parallel fault simulator is used to select the best test set to ensure fault coverage and improve the test generation efficiency.
Secondly, according to the test generation time long and fault coverage low problem of VLSI test, the better capacity algorithm ant algorithm and genetic algorithm are applied to simulation based test generation procedure to reduce the test generation time. Since the simulation-based test generation is lack of information necessary to active the objective fault and to propagate the fault effect, scan design test structure is introduced. A limit scan test generation approach is proposed base on both. Base on the simulation-base test generation method, the scan input, scan select and scan out of scan circuit are regarded as common inputs and output. The difference between scan time cycle and test time cycle is penetrated to improve the fault coverage. Experimental result and comparison result of benchmark circuits'show that the proposed approach reduced the test generation time and improve the fault coverage effectively.
Thirdly, in order to improve the quality of the limit scan test sequence, and improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault, this dissertation analysis the current test quality evaluation method, and adds the fault isolate rate evaluation method to it. Then the new test quality evaluation method is applied to the limit scan test sequence. According to the characteristics of the limit scan test sequence, two test quality improvement approaches are proposed. By randomly specifying the unspecified value of test sequence and modifying the scan select subsequence of test sequence, the limit scan test sequence quality is improved. Experimental result of benchmark circuits show that the proposed method improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault effectively.
Finally, according to the test sequence generated by scan design test structure long, consumes more the test application time problem, the vector omission based static test compaction is applied to the limit scan test sequence to take out the redundant test vectors. According to the scan characteristic of limit scan test sequence, a limit scan static test compact approach is proposed base on the vector omission based static test compaction. Inside the result of the vector omission based static test compaction, shorter limited scan operations are used to take place of longer full scan operations and limited scan operations. The candidate test vectors are combined and the heuristic method is introduced to reduce the computation complexity of static test compaction. Experimental result of benchmark circuits show that the proposed approach reduces the test application time and test data storage effectively and keeps the fault coverage at the same time.
首先,对数字集成电路测试生成过程的关键技术进行了详细分析。建立被测电路的电路模型和故障模型并对被测电路目标故障集进行故障等价归并,精简故障集合,减少测试向量生成过程的计算量；根据电路可测性分析和计算方法,对被测电路进行可测性分析和计算,将计算结果注入电路链表结构,为测试向量生成过程选择最优路径；用并行故障模拟器选出最优的测试向量集合,保证故障覆盖率,提高测试生成效率。
其次,针对数字集成电路测试生成时间长和故障覆盖率低的问题,将性能较好的蚂蚁算法和遗传算法应用于基于模拟的集成电路测试生成过程,缩短测试生成时间；针对基于模拟的测试生成方法所面临的缺乏激活难测故障和传播相应故障响应所必需信息的问题,对电路引入扫描设计测试结构,提出了一种将基于模拟测试生成方法与扫描设计测试结构相结合的有限扫描测试生成方法,在基于模拟的测试生成方法基础上,通过将扫描电路的扫描输入端、扫描选择端和扫描输出端视为电路通用输入输出端,穿透扫描时钟周期和测试时钟周期之间的差异,提高故障覆盖率。国际基准电路实验及比对结果表明,提出方法有效减少了测试生成时间,提高了故障覆盖率。
再次,为了提高有限扫描测试序列对非模型化故障的故障覆盖率和故障隔离率,本文在详细分析现有测试质量评价方法基础上,对其在故障隔离评价方面的不足进行补充和完善。将完善后的测试质量评价方法扩展到有限扫描测试序列质量评价方法,并根据有限扫描测试序列自身特点,提出了两种提高测试质量的方法,通过随机确定测试序列含有的不确定值和修改测试序列内部扫描选择子序列数值的方法提高测试序列质量,基准电路实验结果表明,提出方法有效提高了测试序列对非模型化故障的故障覆盖率和故障隔离率。
最后,针对扫描设计测试结构生成的测试序列长,导致测试应用时间多的问题,对有限扫描测试序列进行了基于向量删除的静态测试压缩,去掉测试序列中的冗余向量；根据有限扫描测试序列的扫描特性,提出一种与基于向量删除静态测试压缩方法相结合的有限扫描静态测试压缩方法,在基于向量删除的静态测试压缩基础上,用较短的有限扫描操作代替较长的全扫描操作或有限扫描操作,合并候选测试向量,引入启发式方法降低计算复杂度,在保证不降低故障覆盖率的前提下,压缩测试序列长度,减少测试应用时间和测试数据存储容量。基准电路实验结果表明,提出方法在保证故障覆盖率不变的前提下,有效减少了有限扫描测试序列的测试应用时间和测试数据存储容量。
The increasing of functions and scale in VLSI made great pressure to VLSI test. Not only the test generation is more and more difficult, but also the test application time becomes longer and longer. This increases the test expense constantly. However, the VLSI test problem relates to designing, producing, manufacturing and application developing of VLSI and other relative products in many fields. Therefore, how to find a high affection, low expense VLSI testing method to fulfill current test need is more and more concentrated by people. According to the problem of test generation time long, fault coverage low and test application time long, this dissertation takes the VLSI testing as background, deeply study the VLSI test generation method, test quality improve method and static test compact method respectively.
First, the critical technologies of VLSI test generation are analyzed in detail. The circuit model and fault model of the circuit under test are established. The fault equivalence is done to the objective fault set to reduce the computation time of test generation procedure. According to the testability analysis and computing method of circuit, the testability of circuit under test is analyzed and computed. The computing result is input to the chain table structure to select the best path of test generation. The parallel fault simulator is used to select the best test set to ensure fault coverage and improve the test generation efficiency.
Secondly, according to the test generation time long and fault coverage low problem of VLSI test, the better capacity algorithm ant algorithm and genetic algorithm are applied to simulation based test generation procedure to reduce the test generation time. Since the simulation-based test generation is lack of information necessary to active the objective fault and to propagate the fault effect, scan design test structure is introduced. A limit scan test generation approach is proposed base on both. Base on the simulation-base test generation method, the scan input, scan select and scan out of scan circuit are regarded as common inputs and output. The difference between scan time cycle and test time cycle is penetrated to improve the fault coverage. Experimental result and comparison result of benchmark circuits'show that the proposed approach reduced the test generation time and improve the fault coverage effectively.
Thirdly, in order to improve the quality of the limit scan test sequence, and improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault, this dissertation analysis the current test quality evaluation method, and adds the fault isolate rate evaluation method to it. Then the new test quality evaluation method is applied to the limit scan test sequence. According to the characteristics of the limit scan test sequence, two test quality improvement approaches are proposed. By randomly specifying the unspecified value of test sequence and modifying the scan select subsequence of test sequence, the limit scan test sequence quality is improved. Experimental result of benchmark circuits show that the proposed method improve the fault coverage and fault isolate rate of limit scan test sequence in non-modeled fault effectively.
Finally, according to the test sequence generated by scan design test structure long, consumes more the test application time problem, the vector omission based static test compaction is applied to the limit scan test sequence to take out the redundant test vectors. According to the scan characteristic of limit scan test sequence, a limit scan static test compact approach is proposed base on the vector omission based static test compaction. Inside the result of the vector omission based static test compaction, shorter limited scan operations are used to take place of longer full scan operations and limited scan operations. The candidate test vectors are combined and the heuristic method is introduced to reduce the computation complexity of static test compaction. Experimental result of benchmark circuits show that the proposed approach reduces the test application time and test data storage effectively and keeps the fault coverage at the same time.
引文
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