嵌入式内核的可测试性设计研究
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摘要
随着深亚微米集成电路技术和基于IP复用的SoC设计技术的发展，国际集成电路产业开始了新一轮分工。新的SoC设计方法把系统集成与功能模块分开，分散了设计难度和规模，能充分发挥设计人员的智力资源优点，这为我国微电子工业赶上世界技术提供了一个适合我国国情的切入点。
集成电路规模的不断扩大，基于嵌入式核进行可重用设计已成为主流技术。但嵌入式核的来源不同、设计标准的不兼容性和电路日趋复杂等因素，使系统芯片最终测试的复杂度远远超出了人们的想象，测试费用上升到产品开发总规划的70％～80％，大大影响了产品的上市时间。随着设计复杂度的提升，测试芯片困难度的增加，如何在设计初期就开始考虑并解决设计完成后的测试问题，已经是一重要课题。
“半导体集成化芯片系统基础研究”是国家自然科学基金委员会组织实施的重大科学研究计划。其宗旨在于：以超过当前国际微电子生产水平2至3代的SoC设计需要解决的重要科学问题为研究对象，开展广泛、深入的基础研究，为我国2005年至2010年及其后的微电子科技与IC产业发展提供解决关键问题的科学方法，从而促进我国电子信息工业高速、持续地发展。SoC的可测试性设计是其中的重点项目。
基于这些原因，本文作者查阅了大量的国内外文献资料，对SoC设计中的可测试性设计从理论作了深入细致的研究，并进行了可行性的实践。可复用IP核以及系统芯片SoC的测试结构设计是一个非常复杂的问题，也是一个新兴研究领域。作者结合当今FPGA技术在IP复用上的平台优势，在这个新型的研究领域尝试进行较系统的研究，期望可以在理论和实践上能为我国发展独立自主产权的SoC设计技术作出贡献，为我国IC设计基础应用研究在21世纪迎头赶上世界一流技术尽一份力。
With the development of VDSM technology and IP-Reuse based SoC Design, the traditional IC industries begin to reform. IP-based SoC design separates system integration from function modular design, thus reducing the difficulty and scale of former design, and the designer can really bring themselves into play. And such situation is also a good chance for Chinese microelectronics industries which are always trying hard to catch up with the world-class technology.
The scale of the IC continuously enlarges, and reusing embedded IP cores in SoC design become the trend. But the source of the cores differs, the design has little compatiblility and the chip circuits become much more complex, the final test of SoC becomes a real big problem. The cost of test dramatically increases to be 78%~80% of the whole cost of product, and increase the time to market. So, considering and implementing a test early in the stage of the whole design process becomes an important task.
"Basic Research of Semiconductor Integrated System on a Chip" is a major program that is funded by National Nature Science Foundation of China. It's goal is to catch up with the world trend and do some basic and profound research of most-needed-to-solve problems in SoC design to provide scientific method for micro-technology and IC industries. Design-for-Test for SoC is the main project.
Considering the above reasons, the author consults a wide range of documents about DFT design in SoC, does a good research theoretically and practically. Nowadays, FPGA has the great potential in IP reuse based SoC design. The author considers the hot technology and also does a great research of it. Hopefully, with the author's great effort in research of DFT for SoCs, more IC designers will occur and willing to devote themselves to our country's basic research of IC design field.
集成电路规模的不断扩大，基于嵌入式核进行可重用设计已成为主流技术。但嵌入式核的来源不同、设计标准的不兼容性和电路日趋复杂等因素，使系统芯片最终测试的复杂度远远超出了人们的想象，测试费用上升到产品开发总规划的70％～80％，大大影响了产品的上市时间。随着设计复杂度的提升，测试芯片困难度的增加，如何在设计初期就开始考虑并解决设计完成后的测试问题，已经是一重要课题。
“半导体集成化芯片系统基础研究”是国家自然科学基金委员会组织实施的重大科学研究计划。其宗旨在于：以超过当前国际微电子生产水平2至3代的SoC设计需要解决的重要科学问题为研究对象，开展广泛、深入的基础研究，为我国2005年至2010年及其后的微电子科技与IC产业发展提供解决关键问题的科学方法，从而促进我国电子信息工业高速、持续地发展。SoC的可测试性设计是其中的重点项目。
基于这些原因，本文作者查阅了大量的国内外文献资料，对SoC设计中的可测试性设计从理论作了深入细致的研究，并进行了可行性的实践。可复用IP核以及系统芯片SoC的测试结构设计是一个非常复杂的问题，也是一个新兴研究领域。作者结合当今FPGA技术在IP复用上的平台优势，在这个新型的研究领域尝试进行较系统的研究，期望可以在理论和实践上能为我国发展独立自主产权的SoC设计技术作出贡献，为我国IC设计基础应用研究在21世纪迎头赶上世界一流技术尽一份力。
With the development of VDSM technology and IP-Reuse based SoC Design, the traditional IC industries begin to reform. IP-based SoC design separates system integration from function modular design, thus reducing the difficulty and scale of former design, and the designer can really bring themselves into play. And such situation is also a good chance for Chinese microelectronics industries which are always trying hard to catch up with the world-class technology.
The scale of the IC continuously enlarges, and reusing embedded IP cores in SoC design become the trend. But the source of the cores differs, the design has little compatiblility and the chip circuits become much more complex, the final test of SoC becomes a real big problem. The cost of test dramatically increases to be 78%~80% of the whole cost of product, and increase the time to market. So, considering and implementing a test early in the stage of the whole design process becomes an important task.
"Basic Research of Semiconductor Integrated System on a Chip" is a major program that is funded by National Nature Science Foundation of China. It's goal is to catch up with the world trend and do some basic and profound research of most-needed-to-solve problems in SoC design to provide scientific method for micro-technology and IC industries. Design-for-Test for SoC is the main project.
Considering the above reasons, the author consults a wide range of documents about DFT design in SoC, does a good research theoretically and practically. Nowadays, FPGA has the great potential in IP reuse based SoC design. The author considers the hot technology and also does a great research of it. Hopefully, with the author's great effort in research of DFT for SoCs, more IC designers will occur and willing to devote themselves to our country's basic research of IC design field.
引文
[1] Zeitzoff, P.M.Circuit, MOSFET, and front end Process integration trends and challenges for the 180 nm and below technology generations: an International Teclmology Roadmap for Semiconductors perspective. Solid-State and Integrated-Circuit Technology,2001.Proceedings.6th International Conference. pp.: 23—28 vol.1
[2] Henry Chang, Larry Cooke, Merrill Hunt etc. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Acedemic Publishers. 1999.
[3] Rochit Rajsuman.SoC设计与测试，北京航空航天大学出版社，2003年8月
[4] Gupta R.K.Zorian,Y. Introducing core-based system design. IEEE Design & Test of Computers. pp.: 15-5. Oct-Dec.1997
[5] Frantz, GA. System on a chip: a system perspective. VLSI Technology, Systems, and Aplications,2001.Proceedings of Technical Papers. 2001 International Symposium. pp.:1-5. APril 2001
[6] Zorian,Y. Test requirements for embedded core-based systems and IEEE P1500. Test Conference, 1997. Proceedings., International. pp.: 191-199
[7] Zorian,Y.; Marinissen, E.J.; Dey, S. Testing embedded-core-based system chips. Computer.June 1999.on Page(s):52-60
[8] Bassam Tabbar, Abdallah Tabbara, Alberto Sangiovanni-Vincentelli. Function/Arehitecture Optimization and Co-design of Embedded Systems. USA: Kiuwer Academic Publishers.2000.
[9] Hunt, M. Rowson, J. A Blocking in a system on a chip. IEEE Spectrum. pp.: 35-41, Nov.1996(IP)
[10] Bricaud, P.J. IP reuse creation for system-on-a-chip design. Custom Integrated Cireuits,1999.Proceedings of the IEEE 1999 pp.:395-401. May1999
[11] 魏少军．新世纪电信网络的发展与SOC设计方法学．中国集成电路．2001年12月．P22-36
[12] Michael Keating, Pierre Bricaud. REUSE METHODOLOGY MANUAL: for System-On-a-Chip Design.USA: Kluwer Academic Publishers.1999, Second Printing.
[13] Alfred L．Crouch．数字集成电路与嵌入式内核系统可测试性设计(影印版)．中国电力出版社．2004年1月．
[14] Kwang-Ting Cheng, Dey, S.; Rodgers, M.; Roy, K. Test challenges for deep sub-micron techoologies. Design Automation Conference, 2000. Proceedings 2000.on Page(s): 142-149
[15] Zorian, Y.; Marinissen, E.J.; Dey, S. Testing Embedded-Core-Based System Chips. Test Conference, 1998. Proceedings., International. pp. 130-143
[16] Corno, E Sonza Reorda, M.Squillero, G. Violante, M. On the test of microprocessor IP cores.Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001.Proceedings. pp: 209-213
[17] 徐欣、孙广富、卢启中，“基于FPGA的嵌入式系统设计”，2002年嵌入式系统年会主
题报告论文
[18] IEEE P1500 Standard for Embedded Core Test. http://grouper.ieee.org/groups/1500
[19] Kenneth Wallquist, Alan Righter and Charles Hawkins. A General Purpose IddQ Measurement Circuit. In Proceedings IEEE Iternational Test Conference. pp: 642-651. October 1993.(ON CHIP SINK)
[20] Rajski, J. Tyszer, J. Modular logic built-in self-test for IP cores. Test Conference,1998.Proceedings., International. pp.313-321.oct. 1998(LBIST)
[21] Benso, A.; Chinsano, S.; Di Natale,G; Prinetto,P.; Bodoni,M.L. Online and offline BIST in IP-core design. IEEE Design & Test of Computers. Pp.92-99. SePt-Oct.2001
[22] Courjon, H. Scan design in the Philips ASIC test environment. Euro ASIC'90. Pp.370-375.29 May-1 Jun 1990
[23] Chih-Chang Lin. Marek-Sadowska, M.Kwang-Ting Cheng. Lee, M.T.C. Scan Paths through functional logic. Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996. Pp.487-490.5-8 May 1996
[24] Levitt, M.E. The economics of scan design. Test Conference,1989. Proceedings. 'Meeting the Tests of Time', International. Pp.869-874.29-31 Aug 1989
[25] IEEE Std 1149.1-2001: IEEE Standard Test Access Port and Boundary-Scan Architecture
[26] Jan M. Rabaey, Anantha Chandrakasan、Borivoje Nikolic, 《数字集成电路：设计透视(影印版 第二版)》，清华大学出版社，2004．3
[27] Synopsys Inc. DFT Compiler Scan Synthesis User Guide
[28] Synopsys Inc. TetraMAX ATPG User Guide
[29] 杨士元编著．数字系统的故障诊断与可靠性设计，清华大学出版社．2000年4月 第2版
[30] ASSET InterTech, Inc. Boundary-Scan Tutorial. 2000
[31] Lijoshmohan N K, Understanding Test Concepts
[32] V.D.Agrawal, C.J.Lin, P.W. Rutkowski, S.Wu, and Y. Zorian. Built-in Self-Test for Digital Integrated Circuits. AT&T Technical Joumal, Vol.73(N0.2):30,Mareh 1994
[33] Mallarapu, S.R.Hoffillan, A.J. IDDQ testing on a custom automotive IC. Solid-State Circuits, IEEE Joumal of Pp.: 295-299.Volume:30, Mar 1995
[34] Chakravarty, S. Thadikaran, P.J. Simulation and generation of IDDQ tests for bridging faults in combinational circuits. Computers, IEEE Trallsactions on Pp. 1131-1140. Volume:45, oct 1996
[35] Rajsuman, R. Iddq testing for CMOS VLSI. Proceedings of the IEEE. pp.: 544-568.Volume: 88, APr 2000
[36] Dervisolu, B. Design for testability: it is time to deliver it for Time-to-Market. Test Conference, 1999. Proceedings.International. pp.: 1102-1111
[37] Wuudiann Ke,; Khoan Truong. Design with testability for a Platform-based SoC design methodology. ASICs,1999.AP-ASIC'99. The First IEEE Asia Pacific Conference Pp.307-310.Aug. 1999
[38] Wbhl, P. Waicukauski, J. Using ATPG for clock rules checking in complex scan designs.VLSI Test Symposium, 1997., 15th IEEE. pp.:130-136.27 Apr-1 May1997
[39] Rajsuman, R. Design-for-Iddq-testing for embedded cores based system-on-a-chip. IDDQ Testing, 1998. Proceedings.1998 IEEE International Workshop. pp.:69-73. November 12-13, 1998
[40] Zorian, Y. Embedded memory test & repair: infrastructure IP for SOC yield. Test Conference,2002. Proceedings. International, pp.:340-349 oct.7-10,2002
[41] Lobetti-Bodoni, M; Pricco, A.,; Benso,A.,; Chiusano, S.; Prinetto, P.An on-line BISTed SRAM IP core. Test Conference, 1999. Proceedings. International. pp.: 993-1000. Setp. 1999
[42] Chih-Wea Wang Chi-Feng Wu Jin-Fu Li Cheng-Wen Wu Teng, T. Chiu, K.Hsiao-Ping Lin.A built-in self-test and self-diagnosis scheme for embedded SRAM. Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian pp.:45-50. Dec.2000
[43] Rajsuman, R. Testing a system-on-a-chip with embedded microprocessor. Test Conference,1999.Proceedings.International.pp.:499-508.SePt. 1999
[44] Kwang-Ting Cheng, Wei-Cheng Lai. Instruction-Level DFT for Testing Processor and IP Cores in System-on-A-Chip, 2001, 38th Conference on Design Automation (DAC'01). pp. 59-64
[45] Marinissen, E.J. Arendsen, R. Bos, G Dingemanse, H. Lousberg, M. Wouters, C. A structured and scalable mechanism for test access to embedded reusable cores. Test Conference, 1998.Proceedings., International. Pp.284-293
[46] Varma, P.; Bhatia, B. A structured test re-use methodology for core-based system chips. Test Conference, 1998.proceedings., International.pp.:294-302
[47] Marinissen, E.J.; Goel,S,K.; Lousberg, M. Wrapper design for embedded core test. Test Conference, 2000.Proceedings.International. Pp.911-920
[48] Douglas J. Smith, 《HDL Chip Design: A practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog》
[49] Immaneni, V. Raman, S. Direct access test scheme-design of block and core cells for embedded ASICs. Test Conference, 1990.Proceedings., International. Pp.488-92
[50] Chandramouli, R.; Pateras, S. Testing systems on a chip. IEEE Spectrum. Nov. 1996. pp.42-7
[51] Touba, N.A. Pouya, B. Using partial isolation rings to test core-based designs. IEEE Design&Test of Computers. Pp.52-59.Oct-Dec. 1997
[52] F.Bouwman, S.Oostdijk, R.Stans, B.Pouya. Macro Testability: The Results of Production Device Applications. Test Conference, 1992. Proceedings., International.pp.: 232-241
[53] Bhattacharya, S. Dey, S.H-SCAN: A high level alternative to full-scan testing with reduced area and test application overheads. VLSI Test SymPosium, 1996, Proceedings of 14th. pp.: 74-80
[54] Ono, T.; Wakui, K.; Hikima, H.; Nakamura, Y.; Yoshida, M. Integrated and automated design-for-testability implementation for cell-based ICs. Test SymPosium,1997.(ATS'97) Proceedings., Sixth Asian. pp.: 122-125
[55] Varma, P; Bhatia, B. A structured test re-use methodology for core-based system chips. Test
Conference, 1998. Proceedings., International. On page(s):294-302
[56] 夏宇闻，《从算法设计到硬线逻辑的实现-复杂数字逻辑系统的Verilog HDL设计技术和方法》，高等教育出版社，2001，2
[57] 夏宇闻，《从算法设计到硬线逻辑的实现-实验练习与Verilog语法手册》，高等教育出版社，2001．2
[58] 任晓文、文博，《CPLD/FPGA高级应用开发指南》，电子工业出版社，2003．6
[59] 王诚、薛小刚、钟信潮，《FPGA/CPLD设计工具Xilinx ISE 5.x实用详解》，人民邮电出版社，2003．12
[60] 任艳颖、王彬，《IC设计基础》，西安电子科技大学，2003．5
[2] Henry Chang, Larry Cooke, Merrill Hunt etc. Surviving the SOC Revolution: a guide to platform-based design. USA: KLUWER Acedemic Publishers. 1999.
[3] Rochit Rajsuman.SoC设计与测试，北京航空航天大学出版社，2003年8月
[4] Gupta R.K.Zorian,Y. Introducing core-based system design. IEEE Design & Test of Computers. pp.: 15-5. Oct-Dec.1997
[5] Frantz, GA. System on a chip: a system perspective. VLSI Technology, Systems, and Aplications,2001.Proceedings of Technical Papers. 2001 International Symposium. pp.:1-5. APril 2001
[6] Zorian,Y. Test requirements for embedded core-based systems and IEEE P1500. Test Conference, 1997. Proceedings., International. pp.: 191-199
[7] Zorian,Y.; Marinissen, E.J.; Dey, S. Testing embedded-core-based system chips. Computer.June 1999.on Page(s):52-60
[8] Bassam Tabbar, Abdallah Tabbara, Alberto Sangiovanni-Vincentelli. Function/Arehitecture Optimization and Co-design of Embedded Systems. USA: Kiuwer Academic Publishers.2000.
[9] Hunt, M. Rowson, J. A Blocking in a system on a chip. IEEE Spectrum. pp.: 35-41, Nov.1996(IP)
[10] Bricaud, P.J. IP reuse creation for system-on-a-chip design. Custom Integrated Cireuits,1999.Proceedings of the IEEE 1999 pp.:395-401. May1999
[11] 魏少军．新世纪电信网络的发展与SOC设计方法学．中国集成电路．2001年12月．P22-36
[12] Michael Keating, Pierre Bricaud. REUSE METHODOLOGY MANUAL: for System-On-a-Chip Design.USA: Kluwer Academic Publishers.1999, Second Printing.
[13] Alfred L．Crouch．数字集成电路与嵌入式内核系统可测试性设计(影印版)．中国电力出版社．2004年1月．
[14] Kwang-Ting Cheng, Dey, S.; Rodgers, M.; Roy, K. Test challenges for deep sub-micron techoologies. Design Automation Conference, 2000. Proceedings 2000.on Page(s): 142-149
[15] Zorian, Y.; Marinissen, E.J.; Dey, S. Testing Embedded-Core-Based System Chips. Test Conference, 1998. Proceedings., International. pp. 130-143
[16] Corno, E Sonza Reorda, M.Squillero, G. Violante, M. On the test of microprocessor IP cores.Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001.Proceedings. pp: 209-213
[17] 徐欣、孙广富、卢启中，“基于FPGA的嵌入式系统设计”，2002年嵌入式系统年会主
题报告论文
[18] IEEE P1500 Standard for Embedded Core Test. http://grouper.ieee.org/groups/1500
[19] Kenneth Wallquist, Alan Righter and Charles Hawkins. A General Purpose IddQ Measurement Circuit. In Proceedings IEEE Iternational Test Conference. pp: 642-651. October 1993.(ON CHIP SINK)
[20] Rajski, J. Tyszer, J. Modular logic built-in self-test for IP cores. Test Conference,1998.Proceedings., International. pp.313-321.oct. 1998(LBIST)
[21] Benso, A.; Chinsano, S.; Di Natale,G; Prinetto,P.; Bodoni,M.L. Online and offline BIST in IP-core design. IEEE Design & Test of Computers. Pp.92-99. SePt-Oct.2001
[22] Courjon, H. Scan design in the Philips ASIC test environment. Euro ASIC'90. Pp.370-375.29 May-1 Jun 1990
[23] Chih-Chang Lin. Marek-Sadowska, M.Kwang-Ting Cheng. Lee, M.T.C. Scan Paths through functional logic. Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996. Pp.487-490.5-8 May 1996
[24] Levitt, M.E. The economics of scan design. Test Conference,1989. Proceedings. 'Meeting the Tests of Time', International. Pp.869-874.29-31 Aug 1989
[25] IEEE Std 1149.1-2001: IEEE Standard Test Access Port and Boundary-Scan Architecture
[26] Jan M. Rabaey, Anantha Chandrakasan、Borivoje Nikolic, 《数字集成电路：设计透视(影印版 第二版)》，清华大学出版社，2004．3
[27] Synopsys Inc. DFT Compiler Scan Synthesis User Guide
[28] Synopsys Inc. TetraMAX ATPG User Guide
[29] 杨士元编著．数字系统的故障诊断与可靠性设计，清华大学出版社．2000年4月 第2版
[30] ASSET InterTech, Inc. Boundary-Scan Tutorial. 2000
[31] Lijoshmohan N K, Understanding Test Concepts
[32] V.D.Agrawal, C.J.Lin, P.W. Rutkowski, S.Wu, and Y. Zorian. Built-in Self-Test for Digital Integrated Circuits. AT&T Technical Joumal, Vol.73(N0.2):30,Mareh 1994
[33] Mallarapu, S.R.Hoffillan, A.J. IDDQ testing on a custom automotive IC. Solid-State Circuits, IEEE Joumal of Pp.: 295-299.Volume:30, Mar 1995
[34] Chakravarty, S. Thadikaran, P.J. Simulation and generation of IDDQ tests for bridging faults in combinational circuits. Computers, IEEE Trallsactions on Pp. 1131-1140. Volume:45, oct 1996
[35] Rajsuman, R. Iddq testing for CMOS VLSI. Proceedings of the IEEE. pp.: 544-568.Volume: 88, APr 2000
[36] Dervisolu, B. Design for testability: it is time to deliver it for Time-to-Market. Test Conference, 1999. Proceedings.International. pp.: 1102-1111
[37] Wuudiann Ke,; Khoan Truong. Design with testability for a Platform-based SoC design methodology. ASICs,1999.AP-ASIC'99. The First IEEE Asia Pacific Conference Pp.307-310.Aug. 1999
[38] Wbhl, P. Waicukauski, J. Using ATPG for clock rules checking in complex scan designs.VLSI Test Symposium, 1997., 15th IEEE. pp.:130-136.27 Apr-1 May1997
[39] Rajsuman, R. Design-for-Iddq-testing for embedded cores based system-on-a-chip. IDDQ Testing, 1998. Proceedings.1998 IEEE International Workshop. pp.:69-73. November 12-13, 1998
[40] Zorian, Y. Embedded memory test & repair: infrastructure IP for SOC yield. Test Conference,2002. Proceedings. International, pp.:340-349 oct.7-10,2002
[41] Lobetti-Bodoni, M; Pricco, A.,; Benso,A.,; Chiusano, S.; Prinetto, P.An on-line BISTed SRAM IP core. Test Conference, 1999. Proceedings. International. pp.: 993-1000. Setp. 1999
[42] Chih-Wea Wang Chi-Feng Wu Jin-Fu Li Cheng-Wen Wu Teng, T. Chiu, K.Hsiao-Ping Lin.A built-in self-test and self-diagnosis scheme for embedded SRAM. Test Symposium, 2000. (ATS 2000). Proceedings of the Ninth Asian pp.:45-50. Dec.2000
[43] Rajsuman, R. Testing a system-on-a-chip with embedded microprocessor. Test Conference,1999.Proceedings.International.pp.:499-508.SePt. 1999
[44] Kwang-Ting Cheng, Wei-Cheng Lai. Instruction-Level DFT for Testing Processor and IP Cores in System-on-A-Chip, 2001, 38th Conference on Design Automation (DAC'01). pp. 59-64
[45] Marinissen, E.J. Arendsen, R. Bos, G Dingemanse, H. Lousberg, M. Wouters, C. A structured and scalable mechanism for test access to embedded reusable cores. Test Conference, 1998.Proceedings., International. Pp.284-293
[46] Varma, P.; Bhatia, B. A structured test re-use methodology for core-based system chips. Test Conference, 1998.proceedings., International.pp.:294-302
[47] Marinissen, E.J.; Goel,S,K.; Lousberg, M. Wrapper design for embedded core test. Test Conference, 2000.Proceedings.International. Pp.911-920
[48] Douglas J. Smith, 《HDL Chip Design: A practical guide for designing, synthesizing and simulating ASICs and FPGAs using VHDL or Verilog》
[49] Immaneni, V. Raman, S. Direct access test scheme-design of block and core cells for embedded ASICs. Test Conference, 1990.Proceedings., International. Pp.488-92
[50] Chandramouli, R.; Pateras, S. Testing systems on a chip. IEEE Spectrum. Nov. 1996. pp.42-7
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