视频压缩与图像旋转的硬件实现研究
|
摘要
随着集成电路工艺技术的发展，FPGA和DSP处理器越来越多地应用到通信、图像处理和模式识别等领域。FPGA逐渐向大容量高速度方向发展，DSP向高速和并行方向发展，DSP的系统时钟越来越高，结构上增加并行处理单元，使得能够在单个时钟周期执行多条指令，所有这些使得许多以前无法在硬件上实现的算法现在很容易实现。本文第一部分介绍如何用FPGA和DSP实现基于H.263标准的视频压缩编码器。首先介绍了视频压缩编码发展的概况；然后介绍基于变换编码的视频压缩方法，并介绍FPGA和DSP处理器在视频压缩编码器中的应用；最后介绍了基于H.263标准的视频压缩编码器硬件实现，并根据FPGA的特点，提出适合其实现的运动估值算法和DCT和IDCT算法。提出的运动估值算法和DCT／IDCT算法充分利用FPGA的并行性特点。第二部分介绍一种基于单片FPGA的实时图像旋转系统。首先介绍图像旋转算法，并在该算法基础上对其进行改进，使其更适合硬件实现，减少了系统资源和整个系统的成本；然后介绍系统的硬件实现。
With the development of integrated circuit, FPGA and DSP processors have been widely used in many fields such as telecommunication ,image processing, pattern recognization and so on. With many resources and high speed, FPGA now has enabled much arithmetic implemental in hardware, which was not practical hi the past. The DSP processor is becoming faster and faster and has more parallel process units which enable DSP processor can execute more than one instructions in one cycle. The first section of this paper is concerned about how to implement video compressor based on H.263 standard using FPGA and DSP processor. First the survey of video encoding development has been conducted, then the video compression technology has been introduced and the application of FPGA and DSP processor in video compression field is appended, finally the hardware implementation of video compressor based on H.263 standard is introduced. According to the characteristic of FPGA, we bring forward the motion estimate and DCT/IDCT arith
metic which can be easily implemented in hardware. The motion estimation and DCT/IDCT arithmetic have fully exploited the parallel characteristic of FPGA. The second section of the paper introduces how to implement the real time image rotation system based on FPGA. First the arithmetic of image rotation is introduced , then we improve the arithmetic which is more suitable for hardware implementation and can save much resources , finally we introduce the system implementation.
With the development of integrated circuit, FPGA and DSP processors have been widely used in many fields such as telecommunication ,image processing, pattern recognization and so on. With many resources and high speed, FPGA now has enabled much arithmetic implemental in hardware, which was not practical hi the past. The DSP processor is becoming faster and faster and has more parallel process units which enable DSP processor can execute more than one instructions in one cycle. The first section of this paper is concerned about how to implement video compressor based on H.263 standard using FPGA and DSP processor. First the survey of video encoding development has been conducted, then the video compression technology has been introduced and the application of FPGA and DSP processor in video compression field is appended, finally the hardware implementation of video compressor based on H.263 standard is introduced. According to the characteristic of FPGA, we bring forward the motion estimate and DCT/IDCT arith
metic which can be easily implemented in hardware. The motion estimation and DCT/IDCT arithmetic have fully exploited the parallel characteristic of FPGA. The second section of the paper introduces how to implement the real time image rotation system based on FPGA. First the arithmetic of image rotation is introduced , then we improve the arithmetic which is more suitable for hardware implementation and can save much resources , finally we introduce the system implementation.
引文
[1] S. A. White, "Application of Distributed Arithmetic to Digital Signal Processing: A Tutorial Review," IEEE Acoustics , Speech and Signal processing magazine,vol.6,pp.4-19,july 1989．
[2] W.P.Burleson and L.L.Scharf," A VLSI Design Methodology for Distributed Arithmetic", J. VLSI Signal Processing. vol.2,pp.235-252, 1991．
[3] S.Wolter,A Schubert,H.Matz,and R.Laur,"On the Comparison between Architectures for the implementation of Distributed Arithmetic",Proc IEEE Int'l symp.circuit and system,vol.3,pp.1829-1832,1993．
[4] M.Sheu,J.Lee,J.Wang,A Susen, and L.liu,"A high throughout-Rate Architecture for 8 8 2-D DCT,"Proc. IEEE Int'l Conf. Acoustic, Speech and Signal Processing, vol.3,pp.1587-1590,1993．
[5] K.Nourji and N.Demassieux,"Optimal VLSI Architeuture For Distributed Arithmetic-Based Alogrithms," Proc.Int'l Conf.Acoustic,Speech and Signal Processing,vol.2, pp.509-512, 1994．
[6] K.Kim,S.Jang,S.Kwon,and K.Son,"A improvement of VLSI Architecture for 2-D Discrete Cosine Transform and its Inverse,"Proc.SPIE,vol.2727,pp.1017-1026． 1996．
[7] Trac D.Trans,"The BinDCT:Fast Mulplierless Approximation of the DCT,"IEEE Signal Processing Letter, vol. 7,no. 6,june 2000．
[8] Ulrich.Benzler,"Spatial Scalable Video Coding Using a Conbined Subband-DCT Approach" IEEE Transactions on Circuit and System for Video Technology, vol. 10,no.7,Octorber 2000．
[9] Vishnu Srinivasan and K.J.Ray Liu, "VLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Application".
[10] E.Y.Lam and J.Y.Goodman," A Mathematics Analysis of the DCT coefficient Distributions for Images,'TEEE Trans.on Image Processing .vol.9, pp.1661-1666, Oct.2000．
[11] Cin-Teng Lin, Gin-Der Wu, Shih-Chiech Hsiao, "New Techniques on Deformed Image Motion Estimation and Compensation," IEEE Trans. On Systems, Man, and Cybernetics-Part B, vol.29, No.6, December 1 999．
[12] 胡琳容，朱秀昌， “一个适用于H．263的运动估计搜索算法”， 通信学报， 第二十一期，第六期，2000年六月。
[13] Yui-Lam Chan, Wan-Chi Siu, "Reliable Search Strategy for Block Motion Estimation by Measuring the Error Surface," IEEE 3381 0-7803-5041-3/99,1999．
[14] Guido M. Schuster and Aggelos K . Katsaggelos, " An Optimal Quadtree-Based
Motion Estimation and Motion-Compensated Interpolation Scheme for Video Compression,"IEEE Trans.On Image Processing, vol.7,no.11,November 1998.
[15]Andrzej Ryszko, Kazimierz Witar,"An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation," IEEE 0-7695-1239-9/01,2001.
[16]余松煜，张文军，孙军《现代图像信息压缩技术》，科学出版社，1998
[17]A.Murat Tekalp University of Rochester,《Digiatal Video Processing》，清华大学出版社，1998。
[18]周炯磬，丁晓明编着，《信源编码原理》，人民邮电出版社，1996
[19]张正阳，“高效图象数据压缩研究”，西安电子科技大学博士论文，1999
[20]段勇，“高效图象编码技术研究及其硬件实现”，西安电子科技大学硕士论文，1999年．
[21]屈玉贵，梁晓雯编着《并行处理系统结构》，中国科学技术大学出版社，1999
[22]ITU-T Recommendation H.263.
[23]Dzung T.Hoang,Philips M.long,and Jeffery Scott,"Efficient Cost Measures for Motion Estimation at Low Bit Ratios",IEEE Transactions on Circuit and System for Video Technology,vol.8,no.4,August 1998.
[24]Tien-Ying Kuo and C. C. Jay Kuo,"Fast overlapped Block Motion Compensation with Checkerboard Block Partition", IEEE Transactions on Circuit and System for Video technology.vol.8,no.6,Octer.1998.
[25]V.K.Heer and H-E.Reinfelder,"A comparison of reversible methods for data commpression,"Pro. SPIE,vol.1233 Med,Image.IV,pp.354-365,1990
[26]Ut-Va Koc,K.J Ray liu,"Interpolation-Free Subpixel Motion Estimation Techniques in DCT domain",IEEE Transactions on Circuit and System for Video technology,vol.8,no.4,August 1998.
[27]宋万杰，罗丰，吴顺君编着《CPLD技术及其应用》，西安电子科技大学出版社，1999
[28]侯伯亨，顾新编着《VHDL硬件描述语言与数字逻辑电路设计》，西安电子科技大学出版社，1999，
[29]《The Programmable Data Book》, XILINX公司1999
[30]《Foundation仿真软件使用指南》, XILINX公司1999
[31]《TMS320C54x Assembly language tools》user guide,Ti company
[32]《TMS320C54 cpu and periferals》user guide,Ti company
[2] W.P.Burleson and L.L.Scharf," A VLSI Design Methodology for Distributed Arithmetic", J. VLSI Signal Processing. vol.2,pp.235-252, 1991．
[3] S.Wolter,A Schubert,H.Matz,and R.Laur,"On the Comparison between Architectures for the implementation of Distributed Arithmetic",Proc IEEE Int'l symp.circuit and system,vol.3,pp.1829-1832,1993．
[4] M.Sheu,J.Lee,J.Wang,A Susen, and L.liu,"A high throughout-Rate Architecture for 8 8 2-D DCT,"Proc. IEEE Int'l Conf. Acoustic, Speech and Signal Processing, vol.3,pp.1587-1590,1993．
[5] K.Nourji and N.Demassieux,"Optimal VLSI Architeuture For Distributed Arithmetic-Based Alogrithms," Proc.Int'l Conf.Acoustic,Speech and Signal Processing,vol.2, pp.509-512, 1994．
[6] K.Kim,S.Jang,S.Kwon,and K.Son,"A improvement of VLSI Architecture for 2-D Discrete Cosine Transform and its Inverse,"Proc.SPIE,vol.2727,pp.1017-1026． 1996．
[7] Trac D.Trans,"The BinDCT:Fast Mulplierless Approximation of the DCT,"IEEE Signal Processing Letter, vol. 7,no. 6,june 2000．
[8] Ulrich.Benzler,"Spatial Scalable Video Coding Using a Conbined Subband-DCT Approach" IEEE Transactions on Circuit and System for Video Technology, vol. 10,no.7,Octorber 2000．
[9] Vishnu Srinivasan and K.J.Ray Liu, "VLSI Design of High-Speed Time-Recursive 2-D DCT/IDCT Processor for Video Application".
[10] E.Y.Lam and J.Y.Goodman," A Mathematics Analysis of the DCT coefficient Distributions for Images,'TEEE Trans.on Image Processing .vol.9, pp.1661-1666, Oct.2000．
[11] Cin-Teng Lin, Gin-Der Wu, Shih-Chiech Hsiao, "New Techniques on Deformed Image Motion Estimation and Compensation," IEEE Trans. On Systems, Man, and Cybernetics-Part B, vol.29, No.6, December 1 999．
[12] 胡琳容，朱秀昌， “一个适用于H．263的运动估计搜索算法”， 通信学报， 第二十一期，第六期，2000年六月。
[13] Yui-Lam Chan, Wan-Chi Siu, "Reliable Search Strategy for Block Motion Estimation by Measuring the Error Surface," IEEE 3381 0-7803-5041-3/99,1999．
[14] Guido M. Schuster and Aggelos K . Katsaggelos, " An Optimal Quadtree-Based
Motion Estimation and Motion-Compensated Interpolation Scheme for Video Compression,"IEEE Trans.On Image Processing, vol.7,no.11,November 1998.
[15]Andrzej Ryszko, Kazimierz Witar,"An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation," IEEE 0-7695-1239-9/01,2001.
[16]余松煜，张文军，孙军《现代图像信息压缩技术》，科学出版社，1998
[17]A.Murat Tekalp University of Rochester,《Digiatal Video Processing》，清华大学出版社，1998。
[18]周炯磬，丁晓明编着，《信源编码原理》，人民邮电出版社，1996
[19]张正阳，“高效图象数据压缩研究”，西安电子科技大学博士论文，1999
[20]段勇，“高效图象编码技术研究及其硬件实现”，西安电子科技大学硕士论文，1999年．
[21]屈玉贵，梁晓雯编着《并行处理系统结构》，中国科学技术大学出版社，1999
[22]ITU-T Recommendation H.263.
[23]Dzung T.Hoang,Philips M.long,and Jeffery Scott,"Efficient Cost Measures for Motion Estimation at Low Bit Ratios",IEEE Transactions on Circuit and System for Video Technology,vol.8,no.4,August 1998.
[24]Tien-Ying Kuo and C. C. Jay Kuo,"Fast overlapped Block Motion Compensation with Checkerboard Block Partition", IEEE Transactions on Circuit and System for Video technology.vol.8,no.6,Octer.1998.
[25]V.K.Heer and H-E.Reinfelder,"A comparison of reversible methods for data commpression,"Pro. SPIE,vol.1233 Med,Image.IV,pp.354-365,1990
[26]Ut-Va Koc,K.J Ray liu,"Interpolation-Free Subpixel Motion Estimation Techniques in DCT domain",IEEE Transactions on Circuit and System for Video technology,vol.8,no.4,August 1998.
[27]宋万杰，罗丰，吴顺君编着《CPLD技术及其应用》，西安电子科技大学出版社，1999
[28]侯伯亨，顾新编着《VHDL硬件描述语言与数字逻辑电路设计》，西安电子科技大学出版社，1999，
[29]《The Programmable Data Book》, XILINX公司1999
[30]《Foundation仿真软件使用指南》, XILINX公司1999
[31]《TMS320C54x Assembly language tools》user guide,Ti company
[32]《TMS320C54 cpu and periferals》user guide,Ti company
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |