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基于Cradle CT3400的视频压缩协议的设计和实现
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摘要
为了节约传输带宽、存储空间,视频压缩编码早已成为国内外研究和工业应用的热点之一。同时,随着现代DSP技术的发展,特别是多核DSP的广泛应用,在DSP上用软件实现视频压缩编码已成为必然趋势。因此对视频压缩标准中的关键技术及其在多核的硬件环境下的设计实现进行研究,并根据不同环境特点进行性能优化,具有十分重要的理论与现实意义。
     本文研究H.263编解码在多核嵌入式处理器上的优化实现,采用的嵌入式处理器是Cradle公司推出的面向多媒体应用的CT3400多核DSP。H.263协议是ITU-T专为中高质量运动图像压缩所设计的低码率图像压缩标准,适用于视频电话、数据存储、视频观看、视频监控等多种的视频应用领域,且主要是作用于带宽相对较窄的视频通信应用方面。Cradle公司生产的CT3400,是一款专门为视频压缩处理的3SOC(Software Scalable System on a Chip)数字信号处理芯片,可以支持灵活的软件系统,只用一套芯片即可实现MPEG的编码、解码、图像处理以及网络传输这样一系列功能。
     本文首先简要介绍了H.263协议和CT3400的硬件结构和特点,阐述了本文的研究背景。然后总结了CT3400的使用要点和技巧,有助于进一步理解多核DSP,理解CT3400的特点和功能。H.263基于CT3400的设计和实现是本文研究的重点,为合理高效的使用CT3400的各种异构多核,先划分出编码器、解码器、输入输出三个并行部分,并分别分配以固定的处理核,这三个部分只存在数据单向传递,没有同步要求。然后对编码器、解码器两部分划分出若干功能模块,并合理设计模块间的接口和通信等问题,接着分别设计和实现各个功能模块。最后,给出了系统最终实现的性能指标和演示效果。
     在具体功能模块的实现过程中,对一些压缩算法作了调研和研究。特别是运动估计算法,运动估计的运算量是总运算量的60%~80%,该算法对编码性能影响巨大。对于不同的视频内容、不同的硬件条件,有不同的最优算法,本文最后提出了三种适用不同环境的算法,并进行仿真、比较,最后给出了仿真结果。
As the original video data is so voluminous for real applications, video coding has been a focus of research and applications for saving transport bandwidth and storage space. Meanwhile, modern DSP technology is developed and multi-core DSP is in the extensive application. On DSP software video compression coding has become an inevitable trend. So it's very important for us to have an in-depth study on the key techniques used in video coding, its realization under different hardware environment and performance optimization according to different environmental characteristics.
     In this paper, the optimization and realization of H.263 video codec on embedded multi-core processor is researched. The embedded processor used is a multi-core DSP for multimedia applications produced by Cradle Corporation. H.263 protocol is an ITU-T recommendation that for high-quality image compression at low bit-rate. It's applicable to video telephony, data storage, video viewing, video surveillance and other video applications. And H.263 is mainly applied in narrow-bandwidth video communication applications. CT3400, produced by Cradle Corp., is a 3SOC (Software Scalable System on a Chip) digital signal processor. It can support flexible software system, and can achieve a whole MPEG system including encoding, decoding, image processing and network transmission function in one chip.
     This paper firstly briefly introduces H.263 protocol and CT3400 hardware structure and characteristics, as the study background. Then it summarizes the main points and skills of using CT3400. This part helps for the further understanding of multi-core DSP and understanding of the characteristics and functions of CT3400. The focus of the study in this paper is the design and realization of H.263 on CT3400. For the purpose of reasonable and efficient use of the heterogeneous processors in CT3400, H.263 is basely divided into three parallel parts: encoder, decoder and input/output. These parts are allocated fix processors, and between these parts, there are no synchronization requirement and only one-direction data transmission. Then the encoder and decoder parts are divided into several functions modules. Before designing and implementing each module, the interfaces and communication problems between modules have been rational and well designed. Finally, the performance indicators and actually performance of the realized system on CT3400 is reported.
     Also, this paper studies and researches some compression algorithm which contained in functional modules. Particularly, the motion estimation algorithm is researched. Because the computing quantum of motion estimation is 60% to 80% of that of the total encoder, this algorithm enormous impacts the system performance. Meanwhile, for different type of video and different hardware, there have different optimal algorithms. In the last chapter, three new algorithms are proposed which fit particular environments. All the three algorithms are simulated and compared with other well-known algorithms, and the results are reported and analyzed.
引文
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