24位∑-△A/D转换器中抽取滤波器的设计和实现
摘要
近十几年来,随着微电子技术的快速发展和计算机技术在集成电路中的应用,集成电路已发展到超大规模甚至是单片系统集成阶段,大大促进了数字技术的发展。数字技术具有速度快、精度高、抗干扰能力强等优点而得到广泛的应用,越来越多的电子设备已经从采用模拟电路实现而大范围地向数字化转变。随着数字化进程的深入,作为连接模拟和数字世界桥梁的模数转换器也同样成为研究热点,其中高位的∑-△型A/D转换器作为高精度信号处理中的重要接口部件,由于其转换精度高而使它们在当今高精度信号处理领域中倍受青睐。因此本论文以实现性能良好的高位∑-△型A/D转换器芯片为目标,设计和实现一款24位∑-△型A/D转换器的关键部分——数字抽取滤波器。
本文先简要介绍∑-△A/D转换器在高精度信号处理中的应用和数字抽取滤波器在∑-△A/D转换器中的作用,接着对∑-△A/D转换器的基本工作原理进行了介绍,其中着重分析了过采样技术和噪声整形技术的基本原理,然后对数字抽取滤波器的原理和实现结构进行了研究,特别介绍了抽取的原理、抽取滤波器的多级结构以及多级结构中的前级梳状滤波器和后级半带滤波器的等方面的原理。
本论文设计的数字抽取滤波器采样频率为256KHz,输出数据率为20Hz,要求整个滤波器实现12800倍降采样,其中级联积分梳状滤波器实现3200倍降采样,半带滤波器实现最后的四倍频降采样。积分梳状滤波器采用无乘法器、结构规则、易于版图实现的递归结构来实现,而半带滤波器则采用运算量低、节省硬件资源的转置型结构来实现。设计首先使用MATLAB对滤波器整体进行仿真,由设计指标定出了各部分结构的参数,然后采用CSMC 0.5um工艺规则完成滤波器的整体版图设计,最终完成了流片和测试。测试结果表明,所设计的数字抽取滤波器实现了抽取滤波的功能,且整体性能良好,达到预期目标。
With the rapid development of microelectronic technology and the aid of computer technology in IC design and development, the scale and complexity of integrated circuits have been increasing exponentially over the past few decades. Due to its flexibility, high resolution, strong anti-interference and fast increasing processing power, more and more applications are using digital circuits and digital technology. Powerful digital circuits and digital processing technology demand higher performance analog-to-digital converters (ADC), which is the interface between analog and digital worlds. This encouraged research activities on high performance ADCs. Among these high performance ADCs, sigma-delta ADC technology has been proven to be an excellent technology choice for implementing high resolution ADC in large-scale digital CMOS process. Its popularity has made it a critical component in many applications.
In this thesis, a brief introduction is given to the application of sigma-delta A/D converters in high-resolution signal processing applications, and the role of decimation filters in sigma-delta A/D converters. The second part explains the basic theory of sigma-delta A/D converters; include the analysis of oversampling and noise shaping technology, followed by a summary of research results in the theory and implementation of digital decimation filters, including comb filters and half-band filter as decimation filters.
The sampling frequency of the designed digital decimation filter is 256kHz. The output data rate is 20Hz. The filter's decimation ratio is 12800, with decimation ratio of 3200 realized by the CIC filter and decimation ratio of 4 realized by the half band filter. The CIC filter is implemented using a recursive structure. The half band filter is realized with a transpose structure. Matlab computer software is used in the design and simulations of the filter. The filter is fabricated in CSMC 0.5um CMOS process. The test results verified the filter's functionality. The design goals and targets have been successfully achieved.
本文先简要介绍∑-△A/D转换器在高精度信号处理中的应用和数字抽取滤波器在∑-△A/D转换器中的作用,接着对∑-△A/D转换器的基本工作原理进行了介绍,其中着重分析了过采样技术和噪声整形技术的基本原理,然后对数字抽取滤波器的原理和实现结构进行了研究,特别介绍了抽取的原理、抽取滤波器的多级结构以及多级结构中的前级梳状滤波器和后级半带滤波器的等方面的原理。
本论文设计的数字抽取滤波器采样频率为256KHz,输出数据率为20Hz,要求整个滤波器实现12800倍降采样,其中级联积分梳状滤波器实现3200倍降采样,半带滤波器实现最后的四倍频降采样。积分梳状滤波器采用无乘法器、结构规则、易于版图实现的递归结构来实现,而半带滤波器则采用运算量低、节省硬件资源的转置型结构来实现。设计首先使用MATLAB对滤波器整体进行仿真,由设计指标定出了各部分结构的参数,然后采用CSMC 0.5um工艺规则完成滤波器的整体版图设计,最终完成了流片和测试。测试结果表明,所设计的数字抽取滤波器实现了抽取滤波的功能,且整体性能良好,达到预期目标。
With the rapid development of microelectronic technology and the aid of computer technology in IC design and development, the scale and complexity of integrated circuits have been increasing exponentially over the past few decades. Due to its flexibility, high resolution, strong anti-interference and fast increasing processing power, more and more applications are using digital circuits and digital technology. Powerful digital circuits and digital processing technology demand higher performance analog-to-digital converters (ADC), which is the interface between analog and digital worlds. This encouraged research activities on high performance ADCs. Among these high performance ADCs, sigma-delta ADC technology has been proven to be an excellent technology choice for implementing high resolution ADC in large-scale digital CMOS process. Its popularity has made it a critical component in many applications.
In this thesis, a brief introduction is given to the application of sigma-delta A/D converters in high-resolution signal processing applications, and the role of decimation filters in sigma-delta A/D converters. The second part explains the basic theory of sigma-delta A/D converters; include the analysis of oversampling and noise shaping technology, followed by a summary of research results in the theory and implementation of digital decimation filters, including comb filters and half-band filter as decimation filters.
The sampling frequency of the designed digital decimation filter is 256kHz. The output data rate is 20Hz. The filter's decimation ratio is 12800, with decimation ratio of 3200 realized by the CIC filter and decimation ratio of 4 realized by the half band filter. The CIC filter is implemented using a recursive structure. The half band filter is realized with a transpose structure. Matlab computer software is used in the design and simulations of the filter. The filter is fabricated in CSMC 0.5um CMOS process. The test results verified the filter's functionality. The design goals and targets have been successfully achieved.
引文
[1]Stewart,R.W.An overview of sigma delta ADCs and DAC devices[J].Oversampling and Sigma-Delta Strategies for DSP,Nov 1995,1/1-1/9
[2]张媛媛,姜岩峰.∑-△模拟/数字转换器综述[J].微电子学,2006,36(4),456-460.
[3]王晶.模拟/数字转换技术及其发展趋势[J].微电子学,2005,35(3),221-225.
[4]Ritoniemi.T,Pajarre.E,lngalsuo.S,Husu.T,Eerola.V,Saramiki.T.A stereo audio sigma-delta A/D-converter[J],JOURNAL OF SOLID-STATE CIRCUITS,29(12),1994,1514-1523.
[5]Jiri Nedved,Jozef Vanneuville,Donne Gevaert,Jan Sevenhans.A Transistor-Only Switched Current Sigma-Delta A/D Converter for a CMOS Speech CODEC[J].JOURNAL OF SOLID-STATE CIRCUITS,30(7),1995,819-822.
[6]James C.Morizio,Michael Hoke,Taskin Kocak.14-bit 2.2-MS/s Sigma-Delta ADC's[J],IEEE JOURNAL OF SOLID-STATE CIRCUITS,35(7),2000,968-977.
[7]Hotger Benidt,Raik Richter,Hans-Joachim Jeiitschel.A 100 MS/sec,8th-order Quadrature Sigma-Delta ADC for Complex-IF Signal Digitization in a Wideband-IF Sampling Receiver[C].ASIC 2003 Proceedings 5th International Conference,2003,669-672.
[8]L.J.Breems,E.J.van der Zwan,E.C.Dijkmans,J.H.Huijsing.A 1.8mW CMOS Σ Δ Modulator with Integrated Mixer for A/D Conversion of IF Signal[J],JOURNAL OF SOLID-STATE CIRCUITS,35(1),2000,468-475.
[9]Zhongrning Shi.Sigma-delta ADC and DAC for digital wireless communication[C],Radio Frequency Integrated Circuits(RFIC) Symposium,IEEE 13-15,1999,57-62.
[10]Philips,K.A 4.4mW 76dB Complex Σ Δ ADC for Bluetooth Receivers[C],ISSCC,2003,64-65.
[11]YuanChenandK-T.Tiew.A Sixth-order Sub sampling Continuous time Bandpass Delta-Sigma Modulator[J],CireuitSandSystems,Vol.6,2005,5589-5592.
[12]Q.Sandifort,L.J.Breems,C.Dijkmans,H.Schuurmans.IF-to-Digital Converter for FM/AM/IBOC Radio[C].Proceedings of the 29th European Solid-State Circuit Conference,2003,707-710.
[13]Sun-Hong Kim,Ho-Yeon Lee,Seok-Woo Choi,Dong-Yong Kim.Wideband multi-bit third-order sigma-delta ADC for wireless transceivers[C].ASIC 5th International Conference,Vol.1,2003,689-692.
[14]Richard Gaggl,Maurizio Inversi,Andreas Wiesbauer.A Power Optimized 14-Bit SC ΔΣ Modulator for ADSL CO Applications[C].ISSCC 2004,SESSION 4.
[15]Takeshi Ueno,Tetsuro ltakura.A 0.9V 1.5mW Continuous-Time △∑ Modulator for WCDMA[C].ISSCC 2004,SESSION 4.
[16]Chiheb REEAI,Adel GHAZEL,Fethi FARHAT.High order l-bit Sigma Delta ADC For Multistandard GSM/RJMTS Radio Receiver[C].ISCAS,2004,128-131.
[17]Oguz altum,jinseok Koh,Philip.E.Allen.A 1.5V multirate multibit sigma delta modulator for GSM WCDMA in a 90 nm digital CMOS process[C].Circuits and Systems ISCAS,Vol.6,2005,5577-5580.
[18]Yong Ping Xu,Rui Yu.Electromechanical Resonator Based Bandpass Sigma-Delta Modulator for Wireless Transceivers[C].RFIT,2005,101-104.
[19]Bahar Jalali,Farahani,Mohammed lsmail.Adaptive Sigma Delta ADC for WiMAX Fixed Point Wireless Applications[C].2005 IEEE.
[20]Raf Schoofs,Michiel Steyaert,Willy Sansen.A1 GHz Continuous-Time Sigma-Delta A/D Converter in 90nm Standard CMOS,2005 IEEE
[21]Ana Rusu,Delia Rodriguez,de Llera Gondlez.The Design of a Low-Distortion Sigma-Delta ADC for WLAN Standards[C].ISSCS,Vol.1,2005,151-154.
[22]A.Rusu,M.Ismail.Low-distortion bandpass ∑△ modulator for wireless radio receivers[J].ELECTRONICS LETTERS,41(19),2005,1044-1046.
[23]Jen-Shiun Chiang,Yi-Tsung Li,Hsin-Liang Chen.A 20-MS/S SIGMA DELTA MODULATOR FOR 802.11/a APPLICATIONS[C].ISCAS,2006,1888-1992.
[24]Ana Rusu,Mohammed Ismaill.Sigma-Delta Solutions for Future Wireless Handields[C].ICECS,2006,58-61.
[25]Lucien J.Breems,Robert H.M,van Veldhoven.Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers[C].ICECS,2006,41-45.
[26]Silva,P.G.R,Breems,L.J,Makinwa K.A.A,Roovers,R,Huijsing,J.H.An 118dB DR CT IF-to-Baseband ∑△ Modulator for AM/FM/IBOC Radio Receivers[C].ISSCC,2006.66-67.
[27]Bharath Kumar Thandri,Jose Silva-Martinez.A 63 dB SNR,75-mW Bandpass RF ∑△ADC at 950 MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology[J].JOURNAL OF SOLID-STATE CIRCUITS,42(2),2007,269-279.
[28]Teng-Hung Chang,Lan-Rong Dung,Jwin-Yen Guo,Kai-Jiun Yang.A 2.5-V 14-bit,180-mW Cascaded ∑△ ADC for ADSL2+ Application[J].JOURNAL OF SOLID-STATE CIRCUITS,42(11),2007,2357-2368.
[29]Paulo G.R.Silva,Lucien J.Breems.An IF-to-Baseband ∑△ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range[J].JOURNAL OF SOLID-STATE CIRCUITS,42(5),2007,1076-1089.
[30]Thomas Christen,Thomas Burger,Qiuting Huang.A 0.13um CMOS EDGE/UMTS/WLAN Tri-Mode ∑△ADC with -92dB THD[C].ISSCC,SESSION 13,2007.
[31]Sotir Ouzounovl,Robert van Veidhoven.A 1.2V 121-Mode CT ∑△ Modulator for Wireless Receivers in 90nm CMOS[C].ISSCC,SESSION 13,2007,242-600.
[32]董在望,李冬梅,王志华,李水明.高等模拟集成电路[M].北京:清华大学出版社,2006.
[33]StevenR.Norsworthy,RIChardSehreier,GaborC.TemeS.Delta-sigma DataConverters Theory Design,and Simulation[M].PIScataway USA:IEEE Cireuits&Systems Soeiety,1996.
[34]Schreier R,Temes G.C.Delta-sigma数据转换器[M].北京:科学出版社,2007.
[35]S.R.Norsworthy,R.Schreier,G.C.Temes.Delta-Sigma Data Converters,Theory,Design,and Simulation[M].Piscataway,NJ:IEEE Press,1997.
[36]洪志良.模拟集成电路分析与设计[M].北京:科学出版社,2005.
[37]R.J.贝克著,沈树群、李国华、汤静译.CMOS混合信号电路设计[M].北京:科学出版社,2005.
[38]RichardSehreier,GaborC.Temes.Understanding Delta-Sigma Data Converters[M].Piseataway USA:IEEEPress,2005.
[39]Ovidiu Bajdechi,Johan H.Huijsing.Systematic design of Sigma-Delta analog-to-digital converters[M].Boston:Kluwer Academic Publishers,2004.
[40]R.del Rio,F.Medeiro.CMOS cascade sigma-delta modulators for sensors and telecom[M].Dordrecht:Springer,2006.
[41]Phillip E.Allen,Douglas R.Holberg著,冯军、李智群译.CMOS模拟集成电路设计[M].北京:电子工业出版社,2006.
[42]陈贵灿,张瑞智,程军.大规模集成电路设计[M].北京:高等教育出版社,2005.
[43]秦世才,高清运.现代模拟集成电子学[M].北京:科学出版社,2003.
[44]易婷.高性能∑-△模数转换器设计[D].复旦大学博士论文,2002.
[45]David A.Johns,Ken Martin著,曾朝阳、赵阳、方顺等译.模拟集成电路设计[M].北京:机械工业出版社,2005.
[46]孙振国.高精度∑-△调制器的设计[D].浙江大学硕士学位论文 2005
[47]R.Jacob Baker,Harry W.Li,David E.Boyce著陈中建译.CMOS电路设计·布局与仿真[M].北京:机械工业出版社,2006.
[48]张欣.VLSI数字信号处理——设计与实现[M].北京:科学出版社,2003
[49]姜宇柏,黄志强.通信收发信机的Verilog实现与仿真[M].北京:机械工业出版社,2007.
[50]P.P.VAIDYANATHAN,TRUONG Q.NGUYEN.A"TRICK" for the Design of FIR Half-Band Filters[J].IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS.VOL.CAS-34,NO.3,1987,297-300.
[51]王宏.MATLAB 65及其在信号处理中的应用[M].北京:清华大学出版社,2004.
[52]飞思科技产品研发中心.MATLAB 7辅助信号处理技术与应用[M]北京:电子工业出版社,2005.
[53]Robert J.Schilling,Sandra L.Harris.Fundamentals of digital signal processing using MATLAB[M].西安:西安交通大学出版社,2005.
[54]Vinay K.Ingle,John G.Proakis.Digital signal processing using MATLAB[M].北京:科学出版社,2003.
[55]Soei-Shin Hang,Rajeev Jain.Decimation filter compiler for oversampling A/D applications[C].ICASSP,Vol.5,1992,537-540.
[56]Brian P.Brandt,Bruce A.Wooley.A Low-Power,Area- Efficient Digital Filter for Decimation and Interpolation[J].JOURNAL OF SOLID-STATE CIRCUITS,29(6),1994,679-687.
[57]H.Aboushady,Y.Dumonteix,M.M.Lo(u|¨)erat,H.Mehrez.EFFICIENT POLYPHASE DECOMPOSITION OF COMB DECIMATION FILTERS IN ∑△ ANALOG-TO-DIGITAL CONVERTERS[J].Circuits and Systems Ⅱ,48(10),898-903.
[58]SHUNl CHU,C.SIDNEY BURRUS.Multirate Filter Designs Using Comb Filters[J].TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL.CAS-31,NO.11,1984,913-924.
[59]Gorun Rujii'i,Hrvoje Bubii.EFFICIENT MODIFIED-SINC DECIMATION FILTERS[J].Circuits and Systems Ⅱ,48(10),2001,898-903.
[60]Stephanie Sculley,Terri Fie.DIGITAL COMB FILTER IMPLEMENTATION FOR THE Ⅱ∑△ A/D CONVERTER[C].ISCAS,Vol.2,1996,281-284.
[61]Louis Luh,John Choma,Jr.Jeffrey Draper,Herming Chiueh.A High-speed Digital Comb Filter for ∑△Analog-to-Digital Conversion[J].Circuits and Systems,1999,356-359.
[62]Nianxiong Tan,Sven Eriksson,Lars Wanhammar.A Novel Bit-Serial Design of Comb Filters for Oversampling A/D Converters[C].IEEE International Symposium on Circuits and Systems,1994,259-262.
[63]Emad N.Farag,Ran-Hong Yan,Mohamed I.Elnasry.DECIMATION FILTERS:LOW-POWER DESIGN AND OPTIMIZATION[J].Communications,Computers and Signal Processing,2(2),1997,850-853.
[64]PENG Chungan,YU Dunshan,SHANG Tianxiu,SHENG Shimin.Efficient VLSI Design and Implementation of DecimationFilter for 2~(nd) ∑△ A/D Converter[J].北京大学学报(自然科学版),43(3),2007,394-399.
[65]Pavel Zahradn'ik,Miroslav Vlcek.Analytical Design of Optimal FIR Comb Filters[C].10th International Telecommunications Conference,Vol.1,2003,3590-3593.
[66]Hengfang Zhu,Xiaobo Wu,Xiaolang Yan.Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters[C].Electron Devices and Solid-State Circuits,2005,665-668.
[67]Andrea Gerosa,Andrea Neviani.A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter[C].ISCAS,Vol.2,2004,248-248.
[68]Letizia Lo Presti.Efficient Modified-Sinc Filters for Sigma-Delta A/D Converters[J].IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ,47(11),2000,1204-1213.
[69]Massimiliano,Laddomada.Comb-Based Decimation Filters for ∑△ A/D Converters:Novel Schemes and Comparisons[J].TRANSACTIONS ON SIGNAL PROCESSING,55(5),2007,1769-1779.
[70]J.C.Candy.Decimation for sigma-delta modulation[J].TRANSACTIONS ON COMMUNICATION,vol.COM-34,NO.1,1986,72-76.
[71]Hogenauer E B.An Economical Crass of Digital Filters for Decimation and Interpolation[J].TRANSACTIONS ON ACOUSTICS,SPEECH,AND SIGNAL PROCESSING,VOL.ASSP-29,NO.2,1981,155-162.
[72]Sung-Mo Kang,Yusul Leblebici著,王志功、窦建华等译.CMOS数字集成电路——分析与设计[M].北京:电子工业出版社,2005.
[73]Alan B.Marcovitz著,殷洪玺、刘新元、禹莹等译.逻辑设计基础(第二版)[M].北京:清华大学出版社,2006.
[74]Uwe Meyer-Baese著,刘凌译.数字信号处理的FPGA实现(第二版)[M].北京:清华大学出版社,2006.
[75]易婷,方杰,洪志良.14位1.5625 MHz的∑△A/D中的降采样低通滤波器的设计[J].固体电子学研究与进展,24(4),2004,455-460.
[76]许波,林争辉.一种用于∑△A/D或D/A过采样转换器的数字滤波器[J].微电子学,30(2),2000,69-71.
[77]Keshab K.Parhi著,陈弘毅、白国强、吴行军等译.VLSI数字信号处理系统[M].北京:机械工业出版社,2004.
[78]杨刚,林争辉.多级抽取滤波器的VLSI实现[J].上海交通大学学报,34(7),2000,900-902.
[79]李梁,李儒章,张俊安,杨毓军.一种适合∑△A/D转换器的FIR数字滤波器[J].微电子学,36(3),2006,340-343.
[80]李东生.电子设计自动化与IC设计[M].北京:高等教育出版社,2004.
[2]张媛媛,姜岩峰.∑-△模拟/数字转换器综述[J].微电子学,2006,36(4),456-460.
[3]王晶.模拟/数字转换技术及其发展趋势[J].微电子学,2005,35(3),221-225.
[4]Ritoniemi.T,Pajarre.E,lngalsuo.S,Husu.T,Eerola.V,Saramiki.T.A stereo audio sigma-delta A/D-converter[J],JOURNAL OF SOLID-STATE CIRCUITS,29(12),1994,1514-1523.
[5]Jiri Nedved,Jozef Vanneuville,Donne Gevaert,Jan Sevenhans.A Transistor-Only Switched Current Sigma-Delta A/D Converter for a CMOS Speech CODEC[J].JOURNAL OF SOLID-STATE CIRCUITS,30(7),1995,819-822.
[6]James C.Morizio,Michael Hoke,Taskin Kocak.14-bit 2.2-MS/s Sigma-Delta ADC's[J],IEEE JOURNAL OF SOLID-STATE CIRCUITS,35(7),2000,968-977.
[7]Hotger Benidt,Raik Richter,Hans-Joachim Jeiitschel.A 100 MS/sec,8th-order Quadrature Sigma-Delta ADC for Complex-IF Signal Digitization in a Wideband-IF Sampling Receiver[C].ASIC 2003 Proceedings 5th International Conference,2003,669-672.
[8]L.J.Breems,E.J.van der Zwan,E.C.Dijkmans,J.H.Huijsing.A 1.8mW CMOS Σ Δ Modulator with Integrated Mixer for A/D Conversion of IF Signal[J],JOURNAL OF SOLID-STATE CIRCUITS,35(1),2000,468-475.
[9]Zhongrning Shi.Sigma-delta ADC and DAC for digital wireless communication[C],Radio Frequency Integrated Circuits(RFIC) Symposium,IEEE 13-15,1999,57-62.
[10]Philips,K.A 4.4mW 76dB Complex Σ Δ ADC for Bluetooth Receivers[C],ISSCC,2003,64-65.
[11]YuanChenandK-T.Tiew.A Sixth-order Sub sampling Continuous time Bandpass Delta-Sigma Modulator[J],CireuitSandSystems,Vol.6,2005,5589-5592.
[12]Q.Sandifort,L.J.Breems,C.Dijkmans,H.Schuurmans.IF-to-Digital Converter for FM/AM/IBOC Radio[C].Proceedings of the 29th European Solid-State Circuit Conference,2003,707-710.
[13]Sun-Hong Kim,Ho-Yeon Lee,Seok-Woo Choi,Dong-Yong Kim.Wideband multi-bit third-order sigma-delta ADC for wireless transceivers[C].ASIC 5th International Conference,Vol.1,2003,689-692.
[14]Richard Gaggl,Maurizio Inversi,Andreas Wiesbauer.A Power Optimized 14-Bit SC ΔΣ Modulator for ADSL CO Applications[C].ISSCC 2004,SESSION 4.
[15]Takeshi Ueno,Tetsuro ltakura.A 0.9V 1.5mW Continuous-Time △∑ Modulator for WCDMA[C].ISSCC 2004,SESSION 4.
[16]Chiheb REEAI,Adel GHAZEL,Fethi FARHAT.High order l-bit Sigma Delta ADC For Multistandard GSM/RJMTS Radio Receiver[C].ISCAS,2004,128-131.
[17]Oguz altum,jinseok Koh,Philip.E.Allen.A 1.5V multirate multibit sigma delta modulator for GSM WCDMA in a 90 nm digital CMOS process[C].Circuits and Systems ISCAS,Vol.6,2005,5577-5580.
[18]Yong Ping Xu,Rui Yu.Electromechanical Resonator Based Bandpass Sigma-Delta Modulator for Wireless Transceivers[C].RFIT,2005,101-104.
[19]Bahar Jalali,Farahani,Mohammed lsmail.Adaptive Sigma Delta ADC for WiMAX Fixed Point Wireless Applications[C].2005 IEEE.
[20]Raf Schoofs,Michiel Steyaert,Willy Sansen.A1 GHz Continuous-Time Sigma-Delta A/D Converter in 90nm Standard CMOS,2005 IEEE
[21]Ana Rusu,Delia Rodriguez,de Llera Gondlez.The Design of a Low-Distortion Sigma-Delta ADC for WLAN Standards[C].ISSCS,Vol.1,2005,151-154.
[22]A.Rusu,M.Ismail.Low-distortion bandpass ∑△ modulator for wireless radio receivers[J].ELECTRONICS LETTERS,41(19),2005,1044-1046.
[23]Jen-Shiun Chiang,Yi-Tsung Li,Hsin-Liang Chen.A 20-MS/S SIGMA DELTA MODULATOR FOR 802.11/a APPLICATIONS[C].ISCAS,2006,1888-1992.
[24]Ana Rusu,Mohammed Ismaill.Sigma-Delta Solutions for Future Wireless Handields[C].ICECS,2006,58-61.
[25]Lucien J.Breems,Robert H.M,van Veldhoven.Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers[C].ICECS,2006,41-45.
[26]Silva,P.G.R,Breems,L.J,Makinwa K.A.A,Roovers,R,Huijsing,J.H.An 118dB DR CT IF-to-Baseband ∑△ Modulator for AM/FM/IBOC Radio Receivers[C].ISSCC,2006.66-67.
[27]Bharath Kumar Thandri,Jose Silva-Martinez.A 63 dB SNR,75-mW Bandpass RF ∑△ADC at 950 MHz Using 3.8-GHz Clock in 0.25-um SiGe BiCMOS Technology[J].JOURNAL OF SOLID-STATE CIRCUITS,42(2),2007,269-279.
[28]Teng-Hung Chang,Lan-Rong Dung,Jwin-Yen Guo,Kai-Jiun Yang.A 2.5-V 14-bit,180-mW Cascaded ∑△ ADC for ADSL2+ Application[J].JOURNAL OF SOLID-STATE CIRCUITS,42(11),2007,2357-2368.
[29]Paulo G.R.Silva,Lucien J.Breems.An IF-to-Baseband ∑△ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range[J].JOURNAL OF SOLID-STATE CIRCUITS,42(5),2007,1076-1089.
[30]Thomas Christen,Thomas Burger,Qiuting Huang.A 0.13um CMOS EDGE/UMTS/WLAN Tri-Mode ∑△ADC with -92dB THD[C].ISSCC,SESSION 13,2007.
[31]Sotir Ouzounovl,Robert van Veidhoven.A 1.2V 121-Mode CT ∑△ Modulator for Wireless Receivers in 90nm CMOS[C].ISSCC,SESSION 13,2007,242-600.
[32]董在望,李冬梅,王志华,李水明.高等模拟集成电路[M].北京:清华大学出版社,2006.
[33]StevenR.Norsworthy,RIChardSehreier,GaborC.TemeS.Delta-sigma DataConverters Theory Design,and Simulation[M].PIScataway USA:IEEE Cireuits&Systems Soeiety,1996.
[34]Schreier R,Temes G.C.Delta-sigma数据转换器[M].北京:科学出版社,2007.
[35]S.R.Norsworthy,R.Schreier,G.C.Temes.Delta-Sigma Data Converters,Theory,Design,and Simulation[M].Piscataway,NJ:IEEE Press,1997.
[36]洪志良.模拟集成电路分析与设计[M].北京:科学出版社,2005.
[37]R.J.贝克著,沈树群、李国华、汤静译.CMOS混合信号电路设计[M].北京:科学出版社,2005.
[38]RichardSehreier,GaborC.Temes.Understanding Delta-Sigma Data Converters[M].Piseataway USA:IEEEPress,2005.
[39]Ovidiu Bajdechi,Johan H.Huijsing.Systematic design of Sigma-Delta analog-to-digital converters[M].Boston:Kluwer Academic Publishers,2004.
[40]R.del Rio,F.Medeiro.CMOS cascade sigma-delta modulators for sensors and telecom[M].Dordrecht:Springer,2006.
[41]Phillip E.Allen,Douglas R.Holberg著,冯军、李智群译.CMOS模拟集成电路设计[M].北京:电子工业出版社,2006.
[42]陈贵灿,张瑞智,程军.大规模集成电路设计[M].北京:高等教育出版社,2005.
[43]秦世才,高清运.现代模拟集成电子学[M].北京:科学出版社,2003.
[44]易婷.高性能∑-△模数转换器设计[D].复旦大学博士论文,2002.
[45]David A.Johns,Ken Martin著,曾朝阳、赵阳、方顺等译.模拟集成电路设计[M].北京:机械工业出版社,2005.
[46]孙振国.高精度∑-△调制器的设计[D].浙江大学硕士学位论文 2005
[47]R.Jacob Baker,Harry W.Li,David E.Boyce著陈中建译.CMOS电路设计·布局与仿真[M].北京:机械工业出版社,2006.
[48]张欣.VLSI数字信号处理——设计与实现[M].北京:科学出版社,2003
[49]姜宇柏,黄志强.通信收发信机的Verilog实现与仿真[M].北京:机械工业出版社,2007.
[50]P.P.VAIDYANATHAN,TRUONG Q.NGUYEN.A"TRICK" for the Design of FIR Half-Band Filters[J].IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS.VOL.CAS-34,NO.3,1987,297-300.
[51]王宏.MATLAB 65及其在信号处理中的应用[M].北京:清华大学出版社,2004.
[52]飞思科技产品研发中心.MATLAB 7辅助信号处理技术与应用[M]北京:电子工业出版社,2005.
[53]Robert J.Schilling,Sandra L.Harris.Fundamentals of digital signal processing using MATLAB[M].西安:西安交通大学出版社,2005.
[54]Vinay K.Ingle,John G.Proakis.Digital signal processing using MATLAB[M].北京:科学出版社,2003.
[55]Soei-Shin Hang,Rajeev Jain.Decimation filter compiler for oversampling A/D applications[C].ICASSP,Vol.5,1992,537-540.
[56]Brian P.Brandt,Bruce A.Wooley.A Low-Power,Area- Efficient Digital Filter for Decimation and Interpolation[J].JOURNAL OF SOLID-STATE CIRCUITS,29(6),1994,679-687.
[57]H.Aboushady,Y.Dumonteix,M.M.Lo(u|¨)erat,H.Mehrez.EFFICIENT POLYPHASE DECOMPOSITION OF COMB DECIMATION FILTERS IN ∑△ ANALOG-TO-DIGITAL CONVERTERS[J].Circuits and Systems Ⅱ,48(10),898-903.
[58]SHUNl CHU,C.SIDNEY BURRUS.Multirate Filter Designs Using Comb Filters[J].TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL.CAS-31,NO.11,1984,913-924.
[59]Gorun Rujii'i,Hrvoje Bubii.EFFICIENT MODIFIED-SINC DECIMATION FILTERS[J].Circuits and Systems Ⅱ,48(10),2001,898-903.
[60]Stephanie Sculley,Terri Fie.DIGITAL COMB FILTER IMPLEMENTATION FOR THE Ⅱ∑△ A/D CONVERTER[C].ISCAS,Vol.2,1996,281-284.
[61]Louis Luh,John Choma,Jr.Jeffrey Draper,Herming Chiueh.A High-speed Digital Comb Filter for ∑△Analog-to-Digital Conversion[J].Circuits and Systems,1999,356-359.
[62]Nianxiong Tan,Sven Eriksson,Lars Wanhammar.A Novel Bit-Serial Design of Comb Filters for Oversampling A/D Converters[C].IEEE International Symposium on Circuits and Systems,1994,259-262.
[63]Emad N.Farag,Ran-Hong Yan,Mohamed I.Elnasry.DECIMATION FILTERS:LOW-POWER DESIGN AND OPTIMIZATION[J].Communications,Computers and Signal Processing,2(2),1997,850-853.
[64]PENG Chungan,YU Dunshan,SHANG Tianxiu,SHENG Shimin.Efficient VLSI Design and Implementation of DecimationFilter for 2~(nd) ∑△ A/D Converter[J].北京大学学报(自然科学版),43(3),2007,394-399.
[65]Pavel Zahradn'ik,Miroslav Vlcek.Analytical Design of Optimal FIR Comb Filters[C].10th International Telecommunications Conference,Vol.1,2003,3590-3593.
[66]Hengfang Zhu,Xiaobo Wu,Xiaolang Yan.Low-Power and Hardware Efficient Decimation Filters in Sigma-Delta A/D Converters[C].Electron Devices and Solid-State Circuits,2005,665-668.
[67]Andrea Gerosa,Andrea Neviani.A low-power decimation filter for a sigma-delta converter based on a power-optimized sinc filter[C].ISCAS,Vol.2,2004,248-248.
[68]Letizia Lo Presti.Efficient Modified-Sinc Filters for Sigma-Delta A/D Converters[J].IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ,47(11),2000,1204-1213.
[69]Massimiliano,Laddomada.Comb-Based Decimation Filters for ∑△ A/D Converters:Novel Schemes and Comparisons[J].TRANSACTIONS ON SIGNAL PROCESSING,55(5),2007,1769-1779.
[70]J.C.Candy.Decimation for sigma-delta modulation[J].TRANSACTIONS ON COMMUNICATION,vol.COM-34,NO.1,1986,72-76.
[71]Hogenauer E B.An Economical Crass of Digital Filters for Decimation and Interpolation[J].TRANSACTIONS ON ACOUSTICS,SPEECH,AND SIGNAL PROCESSING,VOL.ASSP-29,NO.2,1981,155-162.
[72]Sung-Mo Kang,Yusul Leblebici著,王志功、窦建华等译.CMOS数字集成电路——分析与设计[M].北京:电子工业出版社,2005.
[73]Alan B.Marcovitz著,殷洪玺、刘新元、禹莹等译.逻辑设计基础(第二版)[M].北京:清华大学出版社,2006.
[74]Uwe Meyer-Baese著,刘凌译.数字信号处理的FPGA实现(第二版)[M].北京:清华大学出版社,2006.
[75]易婷,方杰,洪志良.14位1.5625 MHz的∑△A/D中的降采样低通滤波器的设计[J].固体电子学研究与进展,24(4),2004,455-460.
[76]许波,林争辉.一种用于∑△A/D或D/A过采样转换器的数字滤波器[J].微电子学,30(2),2000,69-71.
[77]Keshab K.Parhi著,陈弘毅、白国强、吴行军等译.VLSI数字信号处理系统[M].北京:机械工业出版社,2004.
[78]杨刚,林争辉.多级抽取滤波器的VLSI实现[J].上海交通大学学报,34(7),2000,900-902.
[79]李梁,李儒章,张俊安,杨毓军.一种适合∑△A/D转换器的FIR数字滤波器[J].微电子学,36(3),2006,340-343.
[80]李东生.电子设计自动化与IC设计[M].北京:高等教育出版社,2004.
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