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一种用于模数转换器的高速高精度比较器的ASIC设计
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摘要
模数转换器在核电子学领域有广泛的应用。作为模数转换器的核心模块——比较器,其高速高精度设计是设计者不断追求的目标,也是设计的难点。本文介绍了一种采用cmos工艺设计的高速高精度动态比较器,对其结构、设计、仿真结果和版图实现进行了详细的阐述。
Analog to digital converter is widely used in nuclear electronics. As the core module of ADC——comparator, the high-speed and high-resolution design is the pursuit of the goals of the designer, and also a difficult point of design. This paper introduces a high speed and high resolution dynamic comparator designed with CMOS process, the structure, design, simulation results and layout implementation are described in detail.
引文
[1]魏微,陆卫国,郭海东,王铮,赵京伟.一种高速高精度全差分采样保持电路的ASIC设计[J].核电子学与探测技术,2012,32(8):893-898.
    [2]Phillip E.Allen,Douglas R.Holberg,著.冯军,李智群,译.CMOS模拟集成电路设计(第二版)[M].北京:电子工业出版社,2005.3:359-397.
    [3]乔高帅.一种高精度逐次逼近模数转换器的研究和设计[D].上海:上海交通大学,2009.
    [4]Haidong Guo,et al.A low-power 16-bit500kS/s ADC[J].Microelectronics and Electron Devices,2005.WMED'05.2005IEEE Workshop on:84-87.
    [5]Richard K.Hester,et al.Fully Differential ADC with Rail-to-Rail common-mode range and nonlinear capacitor compensation[J].IEEE Journal of Solid-State circuits,2009,Vol.25,No.1:173-182.
    [6]魏微,陆卫国,王铮.电容阵列式逐次逼近模数变换器的误差分析及刻度[C].第十六届核电子学与核探测技术学术年会.四川绵阳,2012.
    [7]G.M.Yin,F.Op't Eynde,W.Sansen.A High-Speed Comparator with 8-b Resolution[J].IEEE Journal of Solid-State Circuits,1992.Vol.27,No.2:208-211.

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