基于表面势的碳化硅基VDMOS器件模型
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摘要
为了满足功率电路及系统设计对碳化硅基垂直双注入金属氧化物半导体晶体管(VDM OS)模型的需求,建立了一套基于表面势计算方法的可描述碳化硅基VDM OS器件电学特性的模型.模型包括静态部分与动态部分.静态部分不仅分别针对沟道区、积累区、寄生结型场效应晶体管(JFET)区及N-外延层建立电流模型,还考虑了界面态对于阈值电压偏移与沟道迁移率的影响.动态部分中引入了界面陷阱对于电容的影响,完善了基于端电荷划分理论的动态模型.结果表明,所提器件模型的输出特性和转移特性的仿真结果与实测结果之间的均方根误差均小于5%,开关特性的仿真结果与实测结果之间的均方根误差小于10%.
To meet the requirements of the power circuit and system design for the silicon carbide( Si C) vertical double-implantation metal oxide semiconductor transistor( VDMOS) device models,a model for descripting the electrical characteristics of Si C VDM OS based on the surface potential calculation method is proposed. This model includes the static part and the dynamic part. In the static model,the current models are built for the channel region,the accumulation region,the junction field effect transistor( JFET) region,and the N-epitaxy layer,respectively. The effects of the interface states on the threshold voltage offset and the channel mobility are considered. In the dynamic model,the influence of the interface trap on the capacitance is introduced and the dynamic model based on the terminal charge division theory is perfected. The results show that the root mean square errors of the simulation results and the measurement results for the output characteristic and the transfer characteristics simulated by the surface-potential-based model of Si C VDM OS are less than 5%,and those for the switching characteristic are less than 10%.
To meet the requirements of the power circuit and system design for the silicon carbide( Si C) vertical double-implantation metal oxide semiconductor transistor( VDMOS) device models,a model for descripting the electrical characteristics of Si C VDM OS based on the surface potential calculation method is proposed. This model includes the static part and the dynamic part. In the static model,the current models are built for the channel region,the accumulation region,the junction field effect transistor( JFET) region,and the N-epitaxy layer,respectively. The effects of the interface states on the threshold voltage offset and the channel mobility are considered. In the dynamic model,the influence of the interface trap on the capacitance is introduced and the dynamic model based on the terminal charge division theory is perfected. The results show that the root mean square errors of the simulation results and the measurement results for the output characteristic and the transfer characteristics simulated by the surface-potential-based model of Si C VDM OS are less than 5%,and those for the switching characteristic are less than 10%.
引文
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[8]Hiroshima University&STARC.Hi SIM HV 2.0.0User's M anual[EB/OL].[2017-07-11].https://w enku.baidu.com/view/64ce6aedaeaad1f346933f25.html.
[9]Shi L,Jia K,Sun W.A novel compact high-voltage LDM OS transistor model for circuit simulation[J].IEEE Transactions on Electron Devices,2013,60(1):346-353.DOI:10.1109/ted.2012.2227116.
[10]Liu S,Zhu R,Jia K,et al.A novel model of the high-voltage VDM OS for the circuit simulation[J].Solid-State Electronics,2014,93(3):21-26.DOI:10.1016/j.sse.2013.12.006.
[11]Hisamoto D,Yoshimoto H,Tega N.Modified interface state charge model for 4H-Si C pow er M OSFETs[J].IEEE Electron Device Letters,2015,36(5):490-492.DOI:10.1109/led.2015.2411751.
[2]Shenai K.Future prospects of widebandgap(WBG)semiconductor pow er sw itching devices[J].IEEE Transactions on Electron Devices,2015,62(2):248-257.DOI:10.1109/ted.2014.2360641.
[3]Chandra Mouli G R,Schijffelen J H,Bauer P,et al.Design and comparison of a 10-k W interleaved boost converter for PV application using Si and Si C devices[J].IEEE Journal of Emerging and Selected Topics in Power Electronics,2017,5(2):610-623.DOI:10.1109/jestpe.2016.2601165.
[4]Mantooth H A,Peng K,Santi E,et al.Modeling of w ide bandgap pow er semiconductor devices-partⅠ[J].IEEE Transactions on Electron Devices,2015,62(2):423-433.DOI:10.1109/ted.2014.2368274.
[5]d'Alessandro V,Magnani A,Riccio M,et al.SPICE modeling and dynamic electrothermal simulation of Si C pow er M OSFETs[C]//2014 IEEE 26th International Symposium on Power Semiconductor Devices and IC's(ISPSD).Waikoloa,HI,USA,2014:285-288.DOI:10.1109/ispsd.2014.6856032.
[6]Sun K,Wu H,Lu J,et al.Improved modeling of medium Voltage Si C M OSFET w ithin w ide temperature range[J].IEEE Transactions on Power Electronics,2014,29(5):2229-2237.DOI:10.1109/tpel.2013.2273459.
[7]贾侃.功率SOI-LDMOS器件的SPICE模型研究与应用[D].南京:东南大学电子科学与工程学院,2013.
[8]Hiroshima University&STARC.Hi SIM HV 2.0.0User's M anual[EB/OL].[2017-07-11].https://w enku.baidu.com/view/64ce6aedaeaad1f346933f25.html.
[9]Shi L,Jia K,Sun W.A novel compact high-voltage LDM OS transistor model for circuit simulation[J].IEEE Transactions on Electron Devices,2013,60(1):346-353.DOI:10.1109/ted.2012.2227116.
[10]Liu S,Zhu R,Jia K,et al.A novel model of the high-voltage VDM OS for the circuit simulation[J].Solid-State Electronics,2014,93(3):21-26.DOI:10.1016/j.sse.2013.12.006.
[11]Hisamoto D,Yoshimoto H,Tega N.Modified interface state charge model for 4H-Si C pow er M OSFETs[J].IEEE Electron Device Letters,2015,36(5):490-492.DOI:10.1109/led.2015.2411751.
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