A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time

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• 作者：LiFang Liu (1)
  Dong Wu (1) (2)
  XueMei Liu (1)
  ZongLiang Huo (3)
  Ming Liu (3)
  LiYang Pan (1) (2)
  
  1. Institute of Microelectronics ; University of Tsinghua ; Beijing ; 100084 ; China
  2. Tsinghua National Laboratory for Information Science and Technology ; Beijing ; 100084 ; China
  3. Laboratory of Nano-Fabrication and Novel Devices Integrated Technology ; Institute of Microelectronics ; Chinese Academy of Sciences ; Beijing ; 100029 ; China
  
• 关键词：NOR flash memory ; giga ; level ; 65 nm technology ; array efficiency ; high speed ; NOR闂瓨 ; giga绾?/li> 65nm宸ヨ壓 ; 闃靛垪鏁堢巼 ; 楂橀€?/li> 042405
• 刊名：SCIENCE CHINA Information Sciences
• 出版年：2015
• 出版时间：April 2015
• 年：2015
• 卷：58
• 期：4
• 页码：1-8
• 全文大小：1,316 KB
• 参考文献：1. Jayanti, S, Yang, X Y, Suri, R (2010) Ultimate scalability of TaN metal floating gate with incorporation of high-K blocking dielectrics for flash memory applications. Proceedings of IEEE International Electron Devices Meeting (IEDM), San Francisco. pp. 106-109
  2. Cai, Y M, Song, Y H, Kwon, W H (2008) A novel nody-tied fin field effect transistor flash memory structure with 位-shaped floating gate for sub 45 nm NOR flash memory. Jpn J Appl Phys 47: pp. 6304-6306 CrossRef
  3. Xiao, N, Chen, Z G, Liu, F (2011) P3Stor: a parallel, durable flash-based SSD for enterprise-scale storage system. Sci China Inf Sci 54: pp. 1129-1141 CrossRef
  4. Qiao, F Y, Pan, L Y, Yu, X (2014) Total ionizing radiation effects of 2-T SONOS for 130 nm/4 Mb NOR flash memory technology. Sci China Inf Sci 57: pp. 062402 CrossRef
  5. An, H, Kim, K, Jung, S (2010) The threshold voltage fluctuation of one memory cell for the scaling-down NOR flash. Proceedings of IEEE International Conference on Network Infrastructure and Digital Content, Beijing. pp. 433-436
  6. Ankolekar, P P, Isaac, R, Bredow, J W (2010) Multibit error-correction methods for latency-constrained flash memory systems. IEEE Trans Dev Mat Rel 10: pp. 33-39 CrossRef
  7. Fastow, R, Banerjee, R, Bjeletich, P (2008) A 45 nm NOR flash technology with self-aligned contacts and 0.024 渭m2 cell size for multi-level applications. Proceedings of International Symposium on VLSI Technology, Systems and Applications, Hsinchu. pp. 81-82
  8. Sevalli, G, Brazzelli, D, Camerlenghi, E (2005) A 65 nm NOR flash technology with 0.042 渭m2 cell size for high performance multilevel application. Proceedings of IEEE International Electron Devices Meeting, Washington D C. pp. 849-852
  9. Takeuchi, K (2009) Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD). IEEE J Solid-State Circuits 44: pp. 1227-1234 CrossRef
  10. Govoreanu, B, Brunco, D P, Houdt, J V (2005) Scaling down the interpoly dielectric for next generation flash memory: challenges and opportunities. Solid-State Electron 49: pp. 1841-1848 CrossRef
  11. Kim, J K, Sakui, K, Lee, S S (1997) A 120-mm 64-Mb NAND flash memory achieving 180 ns/byte effective program speed. IEEE J Solid-State Circuits 32: pp. 670-680 CrossRef
  12. Razavi, B (2001) Design of Analog CMOS Integrated Circuits. McGraw-Hill Higher Education Press, New York
  
• 刊物类别：Computer Science
• 刊物主题：Chinese Library of Science
  Information Systems and Communication Service
  
• 出版者：Science China Press, co-published with Springer
• ISSN：1869-1919

文摘

A 1G-cell NOR flash memory chip has been designed and fabricated successfully with 65 nm technology. To compromise the array efficiency and chip speed, the paper establishes an array model including parasitics of the whole array, and optimizes the sector structure as 512 wordlines (WLs) and 4096 bitlines (BLs). Furthermore, by adding other models of long and thin metal lines, we have analyzed the speed of critical circuit nodes. As a result, the agreement of WL delay between simulation and measurement verifies the accuracy of the array model and lines models. The test results indicate that the chip achieves random access time of 100 ns and page read time of 25 ns under 3.3 V voltage supply.