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High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth
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<title> High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth - Nano Letters (ACS Publications) title> the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics." /> achs/favicon.ico" /> achs/css/atypon-print.css" /> class="journal article pod"> action/clickThrough?id=2896080&url=http%3A%2F%2Facsmediakit.org&loc=%2Fdoi%2Fabs%2F10.1021%2Fnl503596j&pubId=419762264" style="text-decoration: none; border: none;">
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class="articleTitle">High-Speed Planar GaAs Nanowire Arrays with fmax > 75 GHz by Wafer-Scale Bottom-up Growth

Xin Miaoclass="NLM_x"> class="NLM_xref-aff">鈥?/sup>class="ref" href="#notes-1">class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Kelson Chabakclass="NLM_x"> class="NLM_xref-aff">鈥?/sup>class="NLM_xref-aff">鈥?/sup>class="ref" href="#notes-1">class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Chen Zhangclass="NLM_x"> class="NLM_xref-aff">鈥?/sup>class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Parsian K. Mohseniclass="NLM_x"> class="NLM_xref-aff">鈥?/sup>class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Dennis Walkerclass="NLM_x"> class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, Jr.class="NLM_xref-aff">鈥?/sup>class="NLM_x">ace.acs.org/2008/acs" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xml:space="preserve">, and Xiuling Liclass="NLM_x"> class="ref" href="#cor1">*class="NLM_xref-aff">鈥?/sup>class="NLM_x"> 鈥?/sup> Microand Nanotechnology Laboratory, class="institution">Universityof Illinois Urbana鈭扖hampaign, 208 N. Wright Street, Urbana, Illinois 61801, class="country">UnitedStates鈥?/sup> class="institution">AirForce Research Laboratory, Sensors Directorate, 2241 Avionics Circle, Wright-PattersonAir Force Base, Ohio 45433, class="country">United StatesNano Lett., class="citation_year">2015, class="citation_volume">15 (5), pp 2780–2786DOI: 10.1021/nl503596jPublication Date (Web): December 10, 2014Copyright 漏 2014 American Chemical Society*E-mail: mailto:xiuling@illinois.edu">xiuling@illinois.edu.

act">Abstract

Wafer-scale defect-free planar III鈥揤 nanowire (NW) arrays with 鈭?00% yield and precisely defined positions are realized via a patterned vapor鈥搇iquid鈥搒olid (VLS) growth method. Long and uniform planar GaAs NWs were assembled in perfectly parallel arrays to form double-channel T-gated NW array-based high electron mobility transistors (HEMTs) with DC and RF performance surpassing those for all field-effect transistors (FETs) with VLS NWs, carbon nanotubes (CNTs), or graphene channels in-plane with the substrate. For a planar GaAs NW array-based HEMT with 150 nm gate length and 2 V drain bias, the on/off ratio (ION/IOFF), cutoff frequency (fT), and maximum oscillation frequency (fmax) are 104, 33, and 75 GHz, respectively. By characterizing more than 100 devices on a 1.5 脳 1.5 cm2 chip, we prove chip-level electrical uniformity of the planar NW array-based HEMTs and verify the feasibility of using this bottom-up planar NW technology for post-Si large-scale nanoelectronics.

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