2.5GHz全速率时钟数据恢复电路的设计
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摘要
过去二十年来,电话、传真、电视和数据等信号传递的爆炸性需求推动了光纤通信的迅速发展,光纤通信以及与之相关的技术和工艺取得了革命性的进步,美国同步光网络(SONET)和国际同步数字体系(SDH)标准的建立为光纤通信系统的大规模研制和应用开辟的前进的道路。现在,2.5Gbps高速光纤通信系统已经在世界范围内进入大规模建设阶段,更高速率的系统的研制和应用也在开展之中。
时钟数据恢复电路(CDR)正是光纤通信以及很多其他高速串行数据通信系统中不可缺少的关键电路,也是系统向更高速率提升的主要瓶颈。同时,CDR电路还要满足一系列苛刻的国际复用标准。
本文介绍了一种使用0.18μm CMOS工艺实现的,用于SDH系统STM-16(2.5Gbps)标准的时钟数据恢复电路。首先介绍了光纤通信系统的基本概念以及常见的时钟数据恢复电路的结构和基本原理,然后介绍了一个带鉴频器(FD)辅助频率捕获的双环路锁相环时钟数据恢复电路的设计与仿真。
从仿真结果来看,本设计电路可以稳定工作在2.5Gbps的速率下,并符合ITU-T国际标准中对STM-16级别的相关要求。
In the past twenty years, the great demand of transmission of telephone, fax, television and data led to a rapid development of optical communication, optical communication and its technology achieved great progress. The recommendation from SONET and SDH standardized and accelerated the researches and applications of optical communication system. Nowadays, STM-16(2.5Gb/s) has began to construct extensively, and higher-speed system is being studied.
The clock and data recovery(CDR) circuit is a key component in the optical communication system as well as many other high-speed serial data communication systems, and is the main bottleneck of systems’upgrading to higher speed. The CDR circuit is asked to meet a series of hard and fast standard given by the Synchronous Digital Hierarchy(SDH), which they called recommendation.
This paper introduces a clock and data recovery circuit, which is realized in the standard 0.18μm CMOS technology, is used to work under the series STM-16(2.5Gbps) of SDH system. Above all, this paper introduces the basic conceptions of optical communication system, the fundamentals and topological structure of the CDR which is widely and soundly used recently. Then introduces a PLL based frequency acquisition aided dual-loop CDR circuit, the design and simulation results are presented.
According to the simulation results, this CDR circuit can work on 2.5Gbps stably and meet the corresponding ITU-T recommendations.
时钟数据恢复电路(CDR)正是光纤通信以及很多其他高速串行数据通信系统中不可缺少的关键电路,也是系统向更高速率提升的主要瓶颈。同时,CDR电路还要满足一系列苛刻的国际复用标准。
本文介绍了一种使用0.18μm CMOS工艺实现的,用于SDH系统STM-16(2.5Gbps)标准的时钟数据恢复电路。首先介绍了光纤通信系统的基本概念以及常见的时钟数据恢复电路的结构和基本原理,然后介绍了一个带鉴频器(FD)辅助频率捕获的双环路锁相环时钟数据恢复电路的设计与仿真。
从仿真结果来看,本设计电路可以稳定工作在2.5Gbps的速率下,并符合ITU-T国际标准中对STM-16级别的相关要求。
In the past twenty years, the great demand of transmission of telephone, fax, television and data led to a rapid development of optical communication, optical communication and its technology achieved great progress. The recommendation from SONET and SDH standardized and accelerated the researches and applications of optical communication system. Nowadays, STM-16(2.5Gb/s) has began to construct extensively, and higher-speed system is being studied.
The clock and data recovery(CDR) circuit is a key component in the optical communication system as well as many other high-speed serial data communication systems, and is the main bottleneck of systems’upgrading to higher speed. The CDR circuit is asked to meet a series of hard and fast standard given by the Synchronous Digital Hierarchy(SDH), which they called recommendation.
This paper introduces a clock and data recovery circuit, which is realized in the standard 0.18μm CMOS technology, is used to work under the series STM-16(2.5Gbps) of SDH system. Above all, this paper introduces the basic conceptions of optical communication system, the fundamentals and topological structure of the CDR which is widely and soundly used recently. Then introduces a PLL based frequency acquisition aided dual-loop CDR circuit, the design and simulation results are presented.
According to the simulation results, this CDR circuit can work on 2.5Gbps stably and meet the corresponding ITU-T recommendations.
引文
1陈红林. 1.244GHz、0.25μm CMOS工艺可变分频比锁相环倍频器设计.东南大学硕士论文. 2004: 1~2
2盛志伟.超高速时钟恢复电路电路设计.东南大学硕士论文. 2004: 1 2
3 B. Razavi. Design of Integrated Circuits for Optical Communications.清华大学出版社. 2005: 288~329
4王骏峰. 10Gb/s CMOS时钟恢复电路.东南大学硕士论文. 2004: 4
5 ITU-T Recommendation G.783. G.823. G.825
6 J. Lee, B. Razavi. A 40Gb/s Clock and Data Recovery Circuit 0.18μm CMOS Technology. 2003 IEEE International Solid-State Circuit Conference. 2. 2003. Session 13. 40Gb/s Communication ICs. Paper 13.7
7孟凡生. 10-40Gbps光通信和万/千兆以太网时钟处理芯片设计.东南大学硕士论文. 2004: 64~72
8 J. Savoj, B. Razavi. A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector. IEEE Journal of Solid-State Circuits, Vol. 36, No. 5, May, 2001: 761~767
9 Jin Kyu Kwon, Tae Kwan Heo, Sang-Bock Cho, and Sung Min Park. A 5-Gbp/s 1/8-Rate Cmos Clock and Data Recovery Circuit. Iscas2004: IV-294~296
10 A. Seedher, G. E. Sobelman. Fractional Rate Phase Detectors for Clock and Data Recovery. IEEE 2003: 313~316
11 Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo. A 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique. IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, July 2003: 1213~1219
12 J. D. v. d. Tang, D. Kasperkovitz, A. v. Roermund. A 9.8-11.5GHz Quadrature Ring Oscillator for Optical Receiver. Ieee Journal of Solid-State Circuit, Vol. 37, No.3, 3. 2002: 438~442
13 L. W. Couch II.数字与模拟通信系统(第六版).罗新民等译.电子工业出版社. 2003: 131~144
14 M. Beshara. Design Considerations for High Speed Clock and Data Recovery Circuits. A Thesis for the Degree of Master of Applied Science, Ottawa-Carleton Institute for Electrical Engineering, Carleton University 2002: 23~24
15 S. B. Anand. High Speed Clock and Data Recovery Circuits for Random Non-Return-to-Zero Data. A Dissertation for the Degree of Doctor of Philosophy in Electrical Engineering, UCLA. 2001: 45~49
16唐世民. PCI Express中的2.5Gbps时钟数据恢复电路的设计与实现.国防科技大学硕士论文. 2006: 16~18
17 B. Razavi.射频微电子.余志平译等.清华大学出版社. 2006: 5~25
18 S. H. Lee, M. S. Hwang, Y. Choi, S. Kim, Y. Moon, B. J. Lee, D. K. Jeong, W. Kim, Y. J. Park and G. Ahn. A 5 Gb/s 0.25μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit, IEEE J. Solid-State Circuits, Vol. 37: 1822~1830, Dec. 2002
19 J. E. Rogers and J. R. Long. A 10 Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18-μm CMOS, IEEE J. Solid-State Circuits, Vol.37, pp.1781–1789, May 2002. C. F. Schaeffer, The Zero-Beat Method of Frequency Discriminat ion: Proceedings IRE. Vol. 30: 365~367, August 1942
20 F. M. GARDNER. Properties of Frequency Difference Detectors. IEEE Transactions on Communications, Vol. Com-33, No.2, February 1985
21 B. Razavi. Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits - A Tutorial: 6~10
22 C. R. Hogge. A Self-Correcting Clock Recovery Circuit. IEEE J. Lightwave Tech. Vol. 3: 1312~1314.Dec.1985
23 J. D. H. Alexander. Clock Recovery from Random Binary Data. Electrics Letters. Vol. 11: 541~542 Oct.1975
24 F. Yuan. CMOS Current-Mode Circuits for Data Communications. Springer. 2007: 181
25 B. Razavi.模拟CMOS集成电路设计.西安交通大学出版社. 2003: 391~429
26 W. F. Egan. Phase Lock Basics. A Wiley-Interscience Publication. 1998: 105~136
27 F. Yuan. CMOS Current-Mode Circuits for Data Communications. Springer. 2007: 173~176
28姜梅,刘三清,李乃平,陈钊.用于电荷泵锁相环的无源滤波器的设计.微电子学. 33(4). 2008: 1~2
29陈文焕.电荷泵锁相环的基础研究.电子科技大学硕士学位论文. 2005: 22~25
30严杰锋.电荷泵锁相环的模型研究和电路设计.复旦大学博士学位论文. 2006: 17~20
31 M. H. Perrott, Yunteng Huang, R. T. Baird, B. W. Garlepp, Ligang Zhang, J. P. Hein. A2.5Gb/s Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC 2006, Session 18 Clock and Data Recovery,18.2: 328~329
32 D. H. Wolaver. Phase-Locked Loop Circuit Design. Prentice Hall. 1991: 9~22
33 K. Vichienchom. A Multi-gigabit CMOS Transceiver with 2x Oversampling Linear Phase Detector. A Dissertation Submitted to the Graduate Faculty of North Carolina State University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy. 2003: 3~12
34 M. Balsi. F. Centurelli, G. Scotti, P. Tommasino, A. trifiletti. An Accurate Behavioral Model of Phase Detectors for Clock Recovery Circuits. ISCAS. 2003: IV636~639
35 M. Usama, T. Kwasniewski. Design and Comparison of CMOS Current Mode Logic Latches. IEEE. ISCAS. 2004: IV353~356
36 V. Stojanovic and V. G. Oklobdzija. Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems. IEEE Journal Of Solid-State Circuits, Vol.34, No.4, April 1999: 536~548
37 J. Cao, Clock Multiplier Unit and Clock Data Recovery Circuit for 10Gb/s Broadband Communication in 0.18μm CMOS. Dissertation for the Degree of Doctor from University of California. 2003: 20~23
38 J. Savoj, B. Razavi. A l0-Gb/s CMOS Clock and Data Recovery Circuit. 2000 Symposium on VLSI Circuits Digest of Technical Papers: 136~139
39 K. S. Yeo, A. Cabuk, R. Wu, M. A. Ma, X. P. Yu And G.Q. Yan. Non-Sequential Linear CMOS Phase Detector for CDR Applications. IEE Proc.-Circuit Devies Syst, Vol. 152, No.6, Dec. 2005: 667~672
40 H. Arora, N. Klemmer, J. C. Morizio, P. D. Wolf. Enhanced Phase Noise Modeling of Fractional-N Frequency Synthesizers. IEEE Trans. Circuits Syst. I, Reg. Papers. 2005, 52(2): 379~395
41韩良.白涛.一种锁相环中高性能电荷泵电路.微电子学与计算机. 2008, 25(3): 190~192
42温显光.解宁.何乐年.徐新民.孙振国.高速PLL电路中的电荷泵电路设计.微电子学与计算机. 2004, 21(12): 207~209
43曾健平.谢海情.晏敏.曾云.新型全差分电荷泵设计.微电子学与计算机. 2006, 23(7): 135~140
44王裕忠.锁相回路系统之射频电压控制振荡器之研究.国立台湾科技大学硕士学位论文. 2005: 35~39
2盛志伟.超高速时钟恢复电路电路设计.东南大学硕士论文. 2004: 1 2
3 B. Razavi. Design of Integrated Circuits for Optical Communications.清华大学出版社. 2005: 288~329
4王骏峰. 10Gb/s CMOS时钟恢复电路.东南大学硕士论文. 2004: 4
5 ITU-T Recommendation G.783. G.823. G.825
6 J. Lee, B. Razavi. A 40Gb/s Clock and Data Recovery Circuit 0.18μm CMOS Technology. 2003 IEEE International Solid-State Circuit Conference. 2. 2003. Session 13. 40Gb/s Communication ICs. Paper 13.7
7孟凡生. 10-40Gbps光通信和万/千兆以太网时钟处理芯片设计.东南大学硕士论文. 2004: 64~72
8 J. Savoj, B. Razavi. A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector. IEEE Journal of Solid-State Circuits, Vol. 36, No. 5, May, 2001: 761~767
9 Jin Kyu Kwon, Tae Kwan Heo, Sang-Bock Cho, and Sung Min Park. A 5-Gbp/s 1/8-Rate Cmos Clock and Data Recovery Circuit. Iscas2004: IV-294~296
10 A. Seedher, G. E. Sobelman. Fractional Rate Phase Detectors for Clock and Data Recovery. IEEE 2003: 313~316
11 Seong-Jun Song, Sung Min Park, Hoi-Jun Yoo. A 4-Gb/s CMOS Clock and Data Recovery Circuit Using 1/8-Rate Clock Technique. IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, July 2003: 1213~1219
12 J. D. v. d. Tang, D. Kasperkovitz, A. v. Roermund. A 9.8-11.5GHz Quadrature Ring Oscillator for Optical Receiver. Ieee Journal of Solid-State Circuit, Vol. 37, No.3, 3. 2002: 438~442
13 L. W. Couch II.数字与模拟通信系统(第六版).罗新民等译.电子工业出版社. 2003: 131~144
14 M. Beshara. Design Considerations for High Speed Clock and Data Recovery Circuits. A Thesis for the Degree of Master of Applied Science, Ottawa-Carleton Institute for Electrical Engineering, Carleton University 2002: 23~24
15 S. B. Anand. High Speed Clock and Data Recovery Circuits for Random Non-Return-to-Zero Data. A Dissertation for the Degree of Doctor of Philosophy in Electrical Engineering, UCLA. 2001: 45~49
16唐世民. PCI Express中的2.5Gbps时钟数据恢复电路的设计与实现.国防科技大学硕士论文. 2006: 16~18
17 B. Razavi.射频微电子.余志平译等.清华大学出版社. 2006: 5~25
18 S. H. Lee, M. S. Hwang, Y. Choi, S. Kim, Y. Moon, B. J. Lee, D. K. Jeong, W. Kim, Y. J. Park and G. Ahn. A 5 Gb/s 0.25μm CMOS Jitter-Tolerant Variable-Interval Oversampling Clock/Data Recovery Circuit, IEEE J. Solid-State Circuits, Vol. 37: 1822~1830, Dec. 2002
19 J. E. Rogers and J. R. Long. A 10 Gb/s CDR/DEMUX with LC Delay Line VCO in 0.18-μm CMOS, IEEE J. Solid-State Circuits, Vol.37, pp.1781–1789, May 2002. C. F. Schaeffer, The Zero-Beat Method of Frequency Discriminat ion: Proceedings IRE. Vol. 30: 365~367, August 1942
20 F. M. GARDNER. Properties of Frequency Difference Detectors. IEEE Transactions on Communications, Vol. Com-33, No.2, February 1985
21 B. Razavi. Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits - A Tutorial: 6~10
22 C. R. Hogge. A Self-Correcting Clock Recovery Circuit. IEEE J. Lightwave Tech. Vol. 3: 1312~1314.Dec.1985
23 J. D. H. Alexander. Clock Recovery from Random Binary Data. Electrics Letters. Vol. 11: 541~542 Oct.1975
24 F. Yuan. CMOS Current-Mode Circuits for Data Communications. Springer. 2007: 181
25 B. Razavi.模拟CMOS集成电路设计.西安交通大学出版社. 2003: 391~429
26 W. F. Egan. Phase Lock Basics. A Wiley-Interscience Publication. 1998: 105~136
27 F. Yuan. CMOS Current-Mode Circuits for Data Communications. Springer. 2007: 173~176
28姜梅,刘三清,李乃平,陈钊.用于电荷泵锁相环的无源滤波器的设计.微电子学. 33(4). 2008: 1~2
29陈文焕.电荷泵锁相环的基础研究.电子科技大学硕士学位论文. 2005: 22~25
30严杰锋.电荷泵锁相环的模型研究和电路设计.复旦大学博士学位论文. 2006: 17~20
31 M. H. Perrott, Yunteng Huang, R. T. Baird, B. W. Garlepp, Ligang Zhang, J. P. Hein. A2.5Gb/s Multi-Rate 0.25μm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. ISSCC 2006, Session 18 Clock and Data Recovery,18.2: 328~329
32 D. H. Wolaver. Phase-Locked Loop Circuit Design. Prentice Hall. 1991: 9~22
33 K. Vichienchom. A Multi-gigabit CMOS Transceiver with 2x Oversampling Linear Phase Detector. A Dissertation Submitted to the Graduate Faculty of North Carolina State University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy. 2003: 3~12
34 M. Balsi. F. Centurelli, G. Scotti, P. Tommasino, A. trifiletti. An Accurate Behavioral Model of Phase Detectors for Clock Recovery Circuits. ISCAS. 2003: IV636~639
35 M. Usama, T. Kwasniewski. Design and Comparison of CMOS Current Mode Logic Latches. IEEE. ISCAS. 2004: IV353~356
36 V. Stojanovic and V. G. Oklobdzija. Comparative Analysis of Master–Slave Latches and Flip-Flops for High-Performance and Low-Power Systems. IEEE Journal Of Solid-State Circuits, Vol.34, No.4, April 1999: 536~548
37 J. Cao, Clock Multiplier Unit and Clock Data Recovery Circuit for 10Gb/s Broadband Communication in 0.18μm CMOS. Dissertation for the Degree of Doctor from University of California. 2003: 20~23
38 J. Savoj, B. Razavi. A l0-Gb/s CMOS Clock and Data Recovery Circuit. 2000 Symposium on VLSI Circuits Digest of Technical Papers: 136~139
39 K. S. Yeo, A. Cabuk, R. Wu, M. A. Ma, X. P. Yu And G.Q. Yan. Non-Sequential Linear CMOS Phase Detector for CDR Applications. IEE Proc.-Circuit Devies Syst, Vol. 152, No.6, Dec. 2005: 667~672
40 H. Arora, N. Klemmer, J. C. Morizio, P. D. Wolf. Enhanced Phase Noise Modeling of Fractional-N Frequency Synthesizers. IEEE Trans. Circuits Syst. I, Reg. Papers. 2005, 52(2): 379~395
41韩良.白涛.一种锁相环中高性能电荷泵电路.微电子学与计算机. 2008, 25(3): 190~192
42温显光.解宁.何乐年.徐新民.孙振国.高速PLL电路中的电荷泵电路设计.微电子学与计算机. 2004, 21(12): 207~209
43曾健平.谢海情.晏敏.曾云.新型全差分电荷泵设计.微电子学与计算机. 2006, 23(7): 135~140
44王裕忠.锁相回路系统之射频电压控制振荡器之研究.国立台湾科技大学硕士学位论文. 2005: 35~39