用于频率合成器的电荷泵锁相环设计
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摘要
近年来,随着计算机、雷达、导航技术,尤其是无线通信技术的发展,CMOS单片射频收发机由于其低成本、低功耗、高集成度的特点而被广泛应用。而频率合成器是射频收发机中的关键部分,它能满足对频率稳定度、频谱纯度、频率范围和输出频率个数等的较高要求。频率合成器是从一个或多个频率中产生多频率的系统,它以锁相环技术为基础。本文以频率合成器为目标,围绕其主要部分-电荷泵锁相环的理论、模型和设计,进行了深入的研究。
在分析锁相环基本线性模型的基础上,建立起电荷泵锁相环的高阶线性模型,并分析了高阶环路的稳定性。同时建立了电荷泵锁相环的噪声模型,为后面的低层次设计和优化提供理论依据。然后详细介绍了锁相环各模块电路的工作原理。比较了鉴相器的各种实现方式,针对鉴相器的死区效应与工作频率之间的矛盾,对电路结构进行了优化设计。比较了各种电荷泵在非理想因素上的表现,并讨论这些因素,包括电流匹配、时钟馈通、电荷共享等的影响。
接下来本文采用0.18μm工艺设计了一个电荷泵锁相环。以自顶向底的设计方法,从制定设计指标开始,进行了各层次的设计。其中设计的鉴频鉴相器消除了死区效应,鉴相精度高,并且可以达到很高的工作频率;设计的高性能电荷泵采用误差放大器技术,实现了很好的电流匹配性能;根据建立的系统模型,设计并优化了三阶环路滤波器的参数,能够很好地抑制高次谐波。
最后对电荷泵锁相环的版图进行了研究和设计。论述了模拟电路和数模混合电路版图的设计要点,分析了混合电路版图中的噪声和干扰的来源,并介绍了相应的解决方法。根据版图设计理论,完成了电荷泵锁相环中各模块的版图设计,并采用所论述的减小干扰的途径对所设计的版图进行优化,实现了布局紧凑,干扰较小的版图设计。
These years, as the techniques such as computer, radar, navigation, especially the wireless communication technology develop rapidly, CMOS single-chip radio frequency transceiver is widely implemented for its advantages of low cost, low power consumption, and high integration. The frequency synthesizer is the critical part of the transceiver, because it could meet the high requirement for the frequency stability, spectrum purity, frequency range and the number of output frequencies. Frequency synthesizer, based on the Phase-Locked Loop techniques, could generate frequencies from single or multiple frequencies. This thesis carries out research on the theory, model and design methods of Charge-Pump Phase-Locked Loop (CPPLL), with the objective to design a frequency synthesizer later.
Based on the basic linear model of the Phase-Locked Loop, chapter 2 establishes the high-order model of the CPPLL and analysis the stability of the high-order loop. Apart from the linear model, this chapter establishes the noise model of the CPPLL, on the basis of which lower-level circuits are designed and optimized on the latter chapters. The detailed working principles of the PLL modules are introduced then. Comparison among different ways to design Phase Frequency Detector (PFD) is made, and the circuit is optimized to resolve the contradiction of delay span required by the "Dead Zone" effect and working frequency. Also, various kinds of Charge Pump (CP) are compared by their performance on the none-ideal effects, including current matching, clock feeding-through, charge sharing, etc.
The fourth chapter focuses on a specific design of CPPLL with the 0.18um process. Following the top-down design flow, design task is carried out from making design specification to doing transistor-level design. The PFD designed eliminates the "Dead Zone" effect and achieves a good detecting precision and a high working frequency. The high-level charge pump designed shows a perfect current matching performance, based on the error operational amplifier technique. According to the system model established before, a three-order loop filter optimized for its parameter, which is able to eliminate the high-order harmonic wave.
In the final part, the thesis studies and designs the layout of a CPPLL. First, some design principles are listed about the analog circuit layout and the mixed-signal circuit layout. Next, the source of the noise and disturbance in the mixed-signal layout is analyzed and the corresponding resolution is proposed. Finally, under the guidelines of the layout theory, the layout of the CPPLL modules is completed and optimized with the disturbance-reducing methods discussed before. It achieves a tightly-arranged layout with less-disturbance.
在分析锁相环基本线性模型的基础上,建立起电荷泵锁相环的高阶线性模型,并分析了高阶环路的稳定性。同时建立了电荷泵锁相环的噪声模型,为后面的低层次设计和优化提供理论依据。然后详细介绍了锁相环各模块电路的工作原理。比较了鉴相器的各种实现方式,针对鉴相器的死区效应与工作频率之间的矛盾,对电路结构进行了优化设计。比较了各种电荷泵在非理想因素上的表现,并讨论这些因素,包括电流匹配、时钟馈通、电荷共享等的影响。
接下来本文采用0.18μm工艺设计了一个电荷泵锁相环。以自顶向底的设计方法,从制定设计指标开始,进行了各层次的设计。其中设计的鉴频鉴相器消除了死区效应,鉴相精度高,并且可以达到很高的工作频率;设计的高性能电荷泵采用误差放大器技术,实现了很好的电流匹配性能;根据建立的系统模型,设计并优化了三阶环路滤波器的参数,能够很好地抑制高次谐波。
最后对电荷泵锁相环的版图进行了研究和设计。论述了模拟电路和数模混合电路版图的设计要点,分析了混合电路版图中的噪声和干扰的来源,并介绍了相应的解决方法。根据版图设计理论,完成了电荷泵锁相环中各模块的版图设计,并采用所论述的减小干扰的途径对所设计的版图进行优化,实现了布局紧凑,干扰较小的版图设计。
These years, as the techniques such as computer, radar, navigation, especially the wireless communication technology develop rapidly, CMOS single-chip radio frequency transceiver is widely implemented for its advantages of low cost, low power consumption, and high integration. The frequency synthesizer is the critical part of the transceiver, because it could meet the high requirement for the frequency stability, spectrum purity, frequency range and the number of output frequencies. Frequency synthesizer, based on the Phase-Locked Loop techniques, could generate frequencies from single or multiple frequencies. This thesis carries out research on the theory, model and design methods of Charge-Pump Phase-Locked Loop (CPPLL), with the objective to design a frequency synthesizer later.
Based on the basic linear model of the Phase-Locked Loop, chapter 2 establishes the high-order model of the CPPLL and analysis the stability of the high-order loop. Apart from the linear model, this chapter establishes the noise model of the CPPLL, on the basis of which lower-level circuits are designed and optimized on the latter chapters. The detailed working principles of the PLL modules are introduced then. Comparison among different ways to design Phase Frequency Detector (PFD) is made, and the circuit is optimized to resolve the contradiction of delay span required by the "Dead Zone" effect and working frequency. Also, various kinds of Charge Pump (CP) are compared by their performance on the none-ideal effects, including current matching, clock feeding-through, charge sharing, etc.
The fourth chapter focuses on a specific design of CPPLL with the 0.18um process. Following the top-down design flow, design task is carried out from making design specification to doing transistor-level design. The PFD designed eliminates the "Dead Zone" effect and achieves a good detecting precision and a high working frequency. The high-level charge pump designed shows a perfect current matching performance, based on the error operational amplifier technique. According to the system model established before, a three-order loop filter optimized for its parameter, which is able to eliminate the high-order harmonic wave.
In the final part, the thesis studies and designs the layout of a CPPLL. First, some design principles are listed about the analog circuit layout and the mixed-signal circuit layout. Next, the source of the noise and disturbance in the mixed-signal layout is analyzed and the corresponding resolution is proposed. Finally, under the guidelines of the layout theory, the layout of the CPPLL modules is completed and optimized with the disturbance-reducing methods discussed before. It achieves a tightly-arranged layout with less-disturbance.
引文
[1] I.A.Young,et.al.,A PLL Clock Generater with 5 to 110 MHz of Lock Rangefor Microprocessors,IEEE Journal of Solid-State Circuits, 1992,27:1599-1607
[2] L.Kyoohyun,et.al.,A Low-Noise Phase-Lock Loop Design by Loop Bandwidth Optimization,IEEE Journal of Solid-State Circuits,2000,35:807-815
[3] Rohde U L.Microwave and wireless synthesizers.New York: John Wiley&Sons Inc,1997
[4] A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO.pdf
[5] Roland E. Best. Phase-Locked Loops Design, Simulation and Application(Fifth Edition).
[6] F.M.Gardner. Phaselock Techniques.
[7] F.M.Gardner.Charge-Pump Phase-Lock Loops.IEEE Journal of Communications, 1980, COM-28:1849-1858
[8] F.M.Gardner.Phase Accuracy of Charge Pump PLL's.IEEE Journal of Communications, 1982,COM-30:2362-2363
[9] Dan H.Wolaver,Phase-Lock Loop Circuit Design.New York:Prentice Hall,1999.
[10] David Rosemarin,Accurately Compute PLL Charge-Pump Filter Parameters. Microwaves & RF,February, 1999:89-94
[11] Ken Holladay,Design a PLL for a specific loop bandwidth.www.ednmag.com, October 2000
[12] S.Mirabbasi,K.Martin,Design of loop filter in phase-locked loops.Electronics Letters Vol.35,October 1999:1801-1802
[13] An Analysis and Performance Evalution of a Passive Filter Design Technique for Charge Pump Phase-Lock Loops.www.national.com,Application Note 1001,May 1996
[14] Kyoohyum Lim,Chan-Hong Park,Dal-Soo Kim and Beomsup Kim.A Low-Noise Phase-Locked Loop Bandwidth Optimization.IEEE Journal of Solid-State Circuits,2000,35:808-815
[15] Joonsuk Lee and Beomsup Kim,A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control.IEEE Journal of Solid-State Circuits,2000,35:l137-1145
[16] Mozhgan Mansuri and Chih-Kong Ken Yang,Jitter Optimization Based on Phase-Locked Loop Design Parameters.IEEE Journal of Solid-State Circuits,2002,37:1375-1382
[17] Behzad Razavi,Monlithic Phase-Locked Loops and Clock Recovery Circuits:Theory and Design,New York:IEEE Press, 1996
[18] F.M.Gardner.Phase Accuracy of Charge Pump PLL's.IEEE Journal of Communications, 1982,COM-30:2362-2363
[19] J.Kang and D.Kim,A CMOS clock and data recovery with tow-XOR phase-frequency detector circuit, ISSCC Dig.Tech.,2001,4:226-269
[20] S.Anand and B.Razavi,A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,IEEE Journal of Solid-State Circuits,2001,36:432-439
[21] J.Sovoj and B.Razavi,A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,IEEE Journal of Solid-State Circuits,2001,36:761-767
[22] Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactor and charge-pump.IEEE,Vol l,PP.269-272,Jan 1999.
[23]H.O.Johansson.A Simple Precharged CMOS phase Frequency Detector.IEEE Journal of Solid State Circuits,Vol 33,No 2,PP.295-299,Feb 1998.
[24]Woogen Rhee.Design of High-Performance CMOS Charge Pumps in Phase locked loops.IEEE International Symposium on Circuits and Systems,Vol 2,PP.545-548,1999.
[25]William S.T.Yah,Howard C.Luong.A 2-V 900-MHz Monolithic CMOS Dual-Loop frequency synthesizer for GSM Receivers.IEEE Journal of Solid-State Circuits,Vol 36,PP.204-216,2001
[26]LI Jin-cheng and QIU Yu-lin.Current Mismatches in Charge Pufnps of DLL-Based RF CMOS Oscillators[T].半导体学报,Vol.22,No.ll,PP.1369-1373,Nov2001.
[27]William S.T.Yah,Howard C.Luong.A 2-V 900-MHz Monolithic CMOS Dual-Loop frequency synthesizer for GSM Receivers.IEEE Journal ofSolid-State Circuits,Vol 36,PP.204-216,2001
[28]TANG JDVD,KASPERKOVITZ D,ROERMUND A V A 9.8-11.5GHz quadrature ring oscillator for optical receivers[J].IEEE[J]of Solid-State Circuits,2002,37(3):438-442.
[29]ANAND S B,RAZAVI B.A CMOS clock recovery circuit for 2.5Gbit/s NRZ data[J].IEEE J of Solid-State Circuits,2001,36(3):432-439.
[30]YAN WST,LUONG H C.A 900MHz CMOS low-phase-noise voltage-controlled ring oscillator [J].IEEE Trans Circuits Syst II,2001,48(2):216-221.
[31]Best R.E.,Phase-Locked Loops Design,Simulation,and Application.5th edition,New York:The McGraw-Hill Inc.,2003
[32]Tai-Cheng Lee,Behzad Razavi,A Stabilization Technique for Phase-Locked Frequency Synthesizers,IEEE Journal of Solid-State Circuits,2003,38:888-894
[33]Mansuri M.and Yang C,Jitter Optimization Based on Phase-Lock Loop Design Parameters.IEEE Journal of Solid-State Circuits,2002,37:1375-1382
[34]Benyong Zhang,Phillip E.Allen,Jeff M.Huard,A Fast Switching PLL Frequency Synthesizer With an On-Chip Passive Discrete-Time Loop Filter in 0.25-μm CMOS,IEEE Journal of Solid-State Circuits,2003,38:855-865
[35]乔文浩然正气,邹务金.基于Verilog-A的电荷泵锁相环行为级建模和模拟
[36]Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactor and charge-pump.IEEE,Vol 1,PP.269-272,Jan 1999.
[37]H.O.Johansson.A Simple Precharged CMOS phase Frequency Detector.IEEE Journal of Solid State Circuits,Vol 33,No 2,PP.295-299,Feb 1998.
[38]Saug-O Jeort,Tae-Sik Cheung,Woo-Young Choi.Phase/frequency detector for high-speed PLL applications.Electronics Letters,Vol,34,no 22,PP.2120-2121,October 1998.
[39]Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactorand charge-pump.IEEE,Vol 1,PP.269-272,Jan 1999.
[40]Woogen Rhee.Design of High-Performance CMOS Charge Pumps in Phase locked loops.IEEE International Symposium on Circuits and Systems,Vol 2,PP.545-548,1999.
[41]Magnusson H,Olsson H.Design of a high-speed low-voltage(IV) charge-pump for wideband phase-looked loops.ICECS,pp.148-151,2003.
[42]Phillip E.Allen 著,CMOS 模拟集成电路设计,冯军,李智群译.电子工业出版社.2002,
[43]Jae Shin Lee,Min Sun Keel,Shin II Lim and Suki Kim.Charge Pump with perfect current matching characteristics in Phase-Locked loops.Electronics Letters,Vol 36,PP.1908,Nov 2000.
[44]Yan,W.S.T.Luong,H.C.A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:ANALOG AND DlGlTAL SIGNAL PROCESSING 2001.48(2).216-221.
[45]Behzad Razavi著,模拟CMOS集成电路设计,陈贵灿等译,西安交通大学出版社,2002.
[46]J Rabaey,A Chandrakasan,B Nikolic.Digital Integrated Circuits-A Design Perspective[M],2nd edition.Prentice-Hall,2005.
[2] L.Kyoohyun,et.al.,A Low-Noise Phase-Lock Loop Design by Loop Bandwidth Optimization,IEEE Journal of Solid-State Circuits,2000,35:807-815
[3] Rohde U L.Microwave and wireless synthesizers.New York: John Wiley&Sons Inc,1997
[4] A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO.pdf
[5] Roland E. Best. Phase-Locked Loops Design, Simulation and Application(Fifth Edition).
[6] F.M.Gardner. Phaselock Techniques.
[7] F.M.Gardner.Charge-Pump Phase-Lock Loops.IEEE Journal of Communications, 1980, COM-28:1849-1858
[8] F.M.Gardner.Phase Accuracy of Charge Pump PLL's.IEEE Journal of Communications, 1982,COM-30:2362-2363
[9] Dan H.Wolaver,Phase-Lock Loop Circuit Design.New York:Prentice Hall,1999.
[10] David Rosemarin,Accurately Compute PLL Charge-Pump Filter Parameters. Microwaves & RF,February, 1999:89-94
[11] Ken Holladay,Design a PLL for a specific loop bandwidth.www.ednmag.com, October 2000
[12] S.Mirabbasi,K.Martin,Design of loop filter in phase-locked loops.Electronics Letters Vol.35,October 1999:1801-1802
[13] An Analysis and Performance Evalution of a Passive Filter Design Technique for Charge Pump Phase-Lock Loops.www.national.com,Application Note 1001,May 1996
[14] Kyoohyum Lim,Chan-Hong Park,Dal-Soo Kim and Beomsup Kim.A Low-Noise Phase-Locked Loop Bandwidth Optimization.IEEE Journal of Solid-State Circuits,2000,35:808-815
[15] Joonsuk Lee and Beomsup Kim,A Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control.IEEE Journal of Solid-State Circuits,2000,35:l137-1145
[16] Mozhgan Mansuri and Chih-Kong Ken Yang,Jitter Optimization Based on Phase-Locked Loop Design Parameters.IEEE Journal of Solid-State Circuits,2002,37:1375-1382
[17] Behzad Razavi,Monlithic Phase-Locked Loops and Clock Recovery Circuits:Theory and Design,New York:IEEE Press, 1996
[18] F.M.Gardner.Phase Accuracy of Charge Pump PLL's.IEEE Journal of Communications, 1982,COM-30:2362-2363
[19] J.Kang and D.Kim,A CMOS clock and data recovery with tow-XOR phase-frequency detector circuit, ISSCC Dig.Tech.,2001,4:226-269
[20] S.Anand and B.Razavi,A CMOS clock recovery circuit for 2.5-Gb/s NRZ data,IEEE Journal of Solid-State Circuits,2001,36:432-439
[21] J.Sovoj and B.Razavi,A 10-Gb/s CMOS clock and data recovery circuit with a half-rate linear phase detector,IEEE Journal of Solid-State Circuits,2001,36:761-767
[22] Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactor and charge-pump.IEEE,Vol l,PP.269-272,Jan 1999.
[23]H.O.Johansson.A Simple Precharged CMOS phase Frequency Detector.IEEE Journal of Solid State Circuits,Vol 33,No 2,PP.295-299,Feb 1998.
[24]Woogen Rhee.Design of High-Performance CMOS Charge Pumps in Phase locked loops.IEEE International Symposium on Circuits and Systems,Vol 2,PP.545-548,1999.
[25]William S.T.Yah,Howard C.Luong.A 2-V 900-MHz Monolithic CMOS Dual-Loop frequency synthesizer for GSM Receivers.IEEE Journal of Solid-State Circuits,Vol 36,PP.204-216,2001
[26]LI Jin-cheng and QIU Yu-lin.Current Mismatches in Charge Pufnps of DLL-Based RF CMOS Oscillators[T].半导体学报,Vol.22,No.ll,PP.1369-1373,Nov2001.
[27]William S.T.Yah,Howard C.Luong.A 2-V 900-MHz Monolithic CMOS Dual-Loop frequency synthesizer for GSM Receivers.IEEE Journal ofSolid-State Circuits,Vol 36,PP.204-216,2001
[28]TANG JDVD,KASPERKOVITZ D,ROERMUND A V A 9.8-11.5GHz quadrature ring oscillator for optical receivers[J].IEEE[J]of Solid-State Circuits,2002,37(3):438-442.
[29]ANAND S B,RAZAVI B.A CMOS clock recovery circuit for 2.5Gbit/s NRZ data[J].IEEE J of Solid-State Circuits,2001,36(3):432-439.
[30]YAN WST,LUONG H C.A 900MHz CMOS low-phase-noise voltage-controlled ring oscillator [J].IEEE Trans Circuits Syst II,2001,48(2):216-221.
[31]Best R.E.,Phase-Locked Loops Design,Simulation,and Application.5th edition,New York:The McGraw-Hill Inc.,2003
[32]Tai-Cheng Lee,Behzad Razavi,A Stabilization Technique for Phase-Locked Frequency Synthesizers,IEEE Journal of Solid-State Circuits,2003,38:888-894
[33]Mansuri M.and Yang C,Jitter Optimization Based on Phase-Lock Loop Design Parameters.IEEE Journal of Solid-State Circuits,2002,37:1375-1382
[34]Benyong Zhang,Phillip E.Allen,Jeff M.Huard,A Fast Switching PLL Frequency Synthesizer With an On-Chip Passive Discrete-Time Loop Filter in 0.25-μm CMOS,IEEE Journal of Solid-State Circuits,2003,38:855-865
[35]乔文浩然正气,邹务金.基于Verilog-A的电荷泵锁相环行为级建模和模拟
[36]Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactor and charge-pump.IEEE,Vol 1,PP.269-272,Jan 1999.
[37]H.O.Johansson.A Simple Precharged CMOS phase Frequency Detector.IEEE Journal of Solid State Circuits,Vol 33,No 2,PP.295-299,Feb 1998.
[38]Saug-O Jeort,Tae-Sik Cheung,Woo-Young Choi.Phase/frequency detector for high-speed PLL applications.Electronics Letters,Vol,34,no 22,PP.2120-2121,October 1998.
[39]Won-Hyo Lee,Jun-Dong Cho,Sung-Dae Lee.A high speed and low power phase-frequency detactorand charge-pump.IEEE,Vol 1,PP.269-272,Jan 1999.
[40]Woogen Rhee.Design of High-Performance CMOS Charge Pumps in Phase locked loops.IEEE International Symposium on Circuits and Systems,Vol 2,PP.545-548,1999.
[41]Magnusson H,Olsson H.Design of a high-speed low-voltage(IV) charge-pump for wideband phase-looked loops.ICECS,pp.148-151,2003.
[42]Phillip E.Allen 著,CMOS 模拟集成电路设计,冯军,李智群译.电子工业出版社.2002,
[43]Jae Shin Lee,Min Sun Keel,Shin II Lim and Suki Kim.Charge Pump with perfect current matching characteristics in Phase-Locked loops.Electronics Letters,Vol 36,PP.1908,Nov 2000.
[44]Yan,W.S.T.Luong,H.C.A 900-MHz CMOS low-phase-noise voltage-controlled ring oscillator. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II:ANALOG AND DlGlTAL SIGNAL PROCESSING 2001.48(2).216-221.
[45]Behzad Razavi著,模拟CMOS集成电路设计,陈贵灿等译,西安交通大学出版社,2002.
[46]J Rabaey,A Chandrakasan,B Nikolic.Digital Integrated Circuits-A Design Perspective[M],2nd edition.Prentice-Hall,2005.