基于锁相环结构的频率综合器芯片电路设计
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摘要
无线通信技术采用电磁波替代了传统的电缆,并不断追求着更高的便携性。由于尺寸的优势,集成电路成为实现该技术最合适的载体。本论文围绕集成射频收发机的关键模块频率综合器展开研究,主要针对锁相环型频率综合器,从相关理论入手,系统的阐述了环路参数计算,模块电路设计,版图规划以及流片测试的全过程,并在压控振荡器尾电流源的选择、低电源电压振荡器的实现和高频电流模式逻辑(CML, Current-Mode Logic)分频器的设计上提出了相应的解决思路。论文完成以下研究内容：
全面的分析了锁相环的工作原理,频率特性和噪声特性,讨论了环路中主要非线性效应的来源和作用机理,并给出相应的解决方法。
总结了几种改善相噪性能的技术。比较了有无尾电流源对于压控振荡器的影响,据此提出一种用于正交压控振荡器(QVCO, Quadrature Voltage-controlled Oscillator)的改进型开关偏置电流源结构。该结构可以在工作中形成“伪高阻”状态,避免线性区交叉耦合管对于谐振腔的损耗,同时保留传统开关偏置技术的优点,抑制闪烁噪声的产生。该QVCO通过0.18μmCMOS工艺实现,在1V电源电压下振荡在4.56GHz,实现了186.5dBc/Hz的FOM(Figure of Merit),调谐范围为17.3%。
讨论了低电源电压压控振荡器(VCO, Voltage-controlled Oscillator)设计的必要性和面临的问题,提出了一种基于电感偏置网络的电路结构。该结构中交叉耦合管栅端的信号幅度可以达到谐振腔输出幅度的3倍以上,详细的理论推导证明这会减小交叉耦合管的沟道噪声贡献,从而改善VCO的相位噪声性能。同时,电感偏置网络还会在振荡频率和谐振腔品质因子(Q值)上带来一定的提升。结合自适应体端偏置技术的应用,该VCO在0.3V电源电压下可以稳定工作在4.9GHz, FOM达到192.5dBc/Hz。0.13μm CMOS工艺下的测试结果验证了这种电感偏置网络技术的有效性。
介绍了环路分频器、双模预分频器和除2分频器的的分类与工作原理,针对除2分频器在工作频率和分频范围设计上的难点,分析了用于CML结构的感性峰化技术并在0.18μm CMOS工艺上进行了实现。测试结果显示该CML分频器消耗了3.6mW的功耗并实现了2-9GHz的工作范围。同时给出的还有两种结构预分频器的流片测试结果。
按照脉冲超宽带(IR_UWB, Impulse Radio Ultra-Wideband)系统指标,对锁相环的参数进行了详细计算。设计了反馈结构的电荷泵电路,相比于传统结构提升了66%的动态范围。介绍了PS计数器和Sigma Delta调制器(SDM,Sigma-Delta Modulator)的实现方法。在0.18μm和0.13μm CMOS工艺上实现了两款应用于IR_UWB6-9GHz频段的小数锁相环,测试结果显示其相位噪声分别为-68.6dBc/Hz@10KHz.-111.3dBc/Hz@1MHz和-80dBc/z@10KHz.-111.8dBc/Hz@1MHz,满足系统要求。
The medium of wireless communication chose electromagnetic waves instead of traditional cable, and had been pursuing more portability. Due to the advantage of dimension, the integrated circuits become the most suitable carrier. This thesis discusses around the PLL-based frequency synthesizer, which is the key component in integrated RF transceiver. Starting from the theory, this thesis comprehensively introduces the whole process including calculation of the loop parameter, design of module circuits, planning of layout, the tapepout and chip testing. Solutions in choice of the VCO's tail current sources, realization of the low supply voltage VCO and design of the CML divider have been proposed. This thesis has the following achievements:
The working principle, the frequency characteristics and the noise characteristics of PLL are presented. This thesis discusses the source and mechanism of the main nonlinear effects in the loop, followed by the corresponding solutions.
Several techniques to improve the phase noise performance are summarized. This thesis compares the effects of the presence or absence of the tail current source in VCOs. Based on the comparison, an improved switched biasing topology has been proposed in QVCO design. This topology forms a "pseudo-Z" state during the operation, decreasing the loss of tank caused by the cross-coupled Mosfets in linear region. Meanwhile, the advantages of the conventional switched biasing technique have been retained to suppress the flicker noise. The QVCO has been frabricated in0.18μm CMOS technology, working at4.56GHz under1V supply voltage. A FOM of186.5dBc/Hz and a tuning range of17.3%are achieved.
This thesis discusses the necessity and the problem in low supply voltage VCO design. An inductive biasing network is proposed. The amplitude at the gate node of cross coupled Mosfets could be3times larger than that at the output node in the VCO. A detailed theoretical analysis proves that the multiple relationship will reduce the channel noise contribution from the Mosfets, so as to improve the phase noise performance of the VCO. Additionally, this network will bring some other improvements in the oscillation frequency and Q factor of the tank. Cooperating with the adaptive body biasing technique, the proposed VCO oscillates at4.56GHz under 0.3V supply voltage and achieves a FOM of192.5dBc/Hz. Measurement results in0.13μm CMOS technology verify the validity of the inductive biasing technique.
This thesis introduces the classification and operating principle of the loop divider, prescaler and/2divider. In terms of the difficulty in the design of working frequency and range, the CML topology with inductive peaking technique has been analyzed and realized in0.18μm CMOS technology. Measurement results show that this CML divider consumes3.6mW power consumption and achieves a range of2-9GHz. The test results of two prescalers are also given.
According to the requirements of IR_UWB system, the PLL parameters are calculated in detail. A charge pump with feedback topology is proposed, enhancing66%of the dynamic range compared to that of the traditional structure. Implementations of PS counter and Sigma Delta Modulator are also introduced. This thesis realizes two faction-N PLLs for6-9GHz IR_UWB system in0.18μm and0.13μm CMOS process. Measurement results show that the phase noise of the two PLLs are-68.6dBc/Hz@10KHz、-111.3dBc/Hz@1MHz and-80dBc/Hz@10KHz.-111.8dBc/Hz@1MHz, respectively, meeting the system requirements.
全面的分析了锁相环的工作原理,频率特性和噪声特性,讨论了环路中主要非线性效应的来源和作用机理,并给出相应的解决方法。
总结了几种改善相噪性能的技术。比较了有无尾电流源对于压控振荡器的影响,据此提出一种用于正交压控振荡器(QVCO, Quadrature Voltage-controlled Oscillator)的改进型开关偏置电流源结构。该结构可以在工作中形成“伪高阻”状态,避免线性区交叉耦合管对于谐振腔的损耗,同时保留传统开关偏置技术的优点,抑制闪烁噪声的产生。该QVCO通过0.18μmCMOS工艺实现,在1V电源电压下振荡在4.56GHz,实现了186.5dBc/Hz的FOM(Figure of Merit),调谐范围为17.3%。
讨论了低电源电压压控振荡器(VCO, Voltage-controlled Oscillator)设计的必要性和面临的问题,提出了一种基于电感偏置网络的电路结构。该结构中交叉耦合管栅端的信号幅度可以达到谐振腔输出幅度的3倍以上,详细的理论推导证明这会减小交叉耦合管的沟道噪声贡献,从而改善VCO的相位噪声性能。同时,电感偏置网络还会在振荡频率和谐振腔品质因子(Q值)上带来一定的提升。结合自适应体端偏置技术的应用,该VCO在0.3V电源电压下可以稳定工作在4.9GHz, FOM达到192.5dBc/Hz。0.13μm CMOS工艺下的测试结果验证了这种电感偏置网络技术的有效性。
介绍了环路分频器、双模预分频器和除2分频器的的分类与工作原理,针对除2分频器在工作频率和分频范围设计上的难点,分析了用于CML结构的感性峰化技术并在0.18μm CMOS工艺上进行了实现。测试结果显示该CML分频器消耗了3.6mW的功耗并实现了2-9GHz的工作范围。同时给出的还有两种结构预分频器的流片测试结果。
按照脉冲超宽带(IR_UWB, Impulse Radio Ultra-Wideband)系统指标,对锁相环的参数进行了详细计算。设计了反馈结构的电荷泵电路,相比于传统结构提升了66%的动态范围。介绍了PS计数器和Sigma Delta调制器(SDM,Sigma-Delta Modulator)的实现方法。在0.18μm和0.13μm CMOS工艺上实现了两款应用于IR_UWB6-9GHz频段的小数锁相环,测试结果显示其相位噪声分别为-68.6dBc/Hz@10KHz.-111.3dBc/Hz@1MHz和-80dBc/z@10KHz.-111.8dBc/Hz@1MHz,满足系统要求。
The medium of wireless communication chose electromagnetic waves instead of traditional cable, and had been pursuing more portability. Due to the advantage of dimension, the integrated circuits become the most suitable carrier. This thesis discusses around the PLL-based frequency synthesizer, which is the key component in integrated RF transceiver. Starting from the theory, this thesis comprehensively introduces the whole process including calculation of the loop parameter, design of module circuits, planning of layout, the tapepout and chip testing. Solutions in choice of the VCO's tail current sources, realization of the low supply voltage VCO and design of the CML divider have been proposed. This thesis has the following achievements:
The working principle, the frequency characteristics and the noise characteristics of PLL are presented. This thesis discusses the source and mechanism of the main nonlinear effects in the loop, followed by the corresponding solutions.
Several techniques to improve the phase noise performance are summarized. This thesis compares the effects of the presence or absence of the tail current source in VCOs. Based on the comparison, an improved switched biasing topology has been proposed in QVCO design. This topology forms a "pseudo-Z" state during the operation, decreasing the loss of tank caused by the cross-coupled Mosfets in linear region. Meanwhile, the advantages of the conventional switched biasing technique have been retained to suppress the flicker noise. The QVCO has been frabricated in0.18μm CMOS technology, working at4.56GHz under1V supply voltage. A FOM of186.5dBc/Hz and a tuning range of17.3%are achieved.
This thesis discusses the necessity and the problem in low supply voltage VCO design. An inductive biasing network is proposed. The amplitude at the gate node of cross coupled Mosfets could be3times larger than that at the output node in the VCO. A detailed theoretical analysis proves that the multiple relationship will reduce the channel noise contribution from the Mosfets, so as to improve the phase noise performance of the VCO. Additionally, this network will bring some other improvements in the oscillation frequency and Q factor of the tank. Cooperating with the adaptive body biasing technique, the proposed VCO oscillates at4.56GHz under 0.3V supply voltage and achieves a FOM of192.5dBc/Hz. Measurement results in0.13μm CMOS technology verify the validity of the inductive biasing technique.
This thesis introduces the classification and operating principle of the loop divider, prescaler and/2divider. In terms of the difficulty in the design of working frequency and range, the CML topology with inductive peaking technique has been analyzed and realized in0.18μm CMOS technology. Measurement results show that this CML divider consumes3.6mW power consumption and achieves a range of2-9GHz. The test results of two prescalers are also given.
According to the requirements of IR_UWB system, the PLL parameters are calculated in detail. A charge pump with feedback topology is proposed, enhancing66%of the dynamic range compared to that of the traditional structure. Implementations of PS counter and Sigma Delta Modulator are also introduced. This thesis realizes two faction-N PLLs for6-9GHz IR_UWB system in0.18μm and0.13μm CMOS process. Measurement results show that the phase noise of the two PLLs are-68.6dBc/Hz@10KHz、-111.3dBc/Hz@1MHz and-80dBc/Hz@10KHz.-111.8dBc/Hz@1MHz, respectively, meeting the system requirements.
引文
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