应变硅器件低场迁移率模型和新结构SGOI器件的性能分析
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摘要
随着CMOS (Complementary Metal Oxide Semiconductor,互补式场效应晶体管)器件尺寸进入亚微米,深亚微米领域,传统器件所采用的材料和器件结构将会接近或达到它们的极限。要克服由于基本的物理问题对传统的MOSFET器件结构的发展所造成的障碍,需要从引入新的材料和采用新的器件结构两方面进行创新。基于SOI (silicon On Insulator,绝缘体上硅)技术和应变硅技术(Si)结合体的新型器件SGOI(SiGe On Insulator绝缘体上硅锗)被认为是纳米范围内最具有应用前景的器件结构。本文从器件结构、物理模型和可靠性等方面对SGOI MOSFET进行了分析研究。主要的研究工作和成果如下：
1.论文通过合理地引入数学表达式,考虑了纯硅和掺杂硅中由于声子边界散射引起热导率的减小。在温度范围从300到1000K,硅膜厚度从10nm到1μm之间应用该模型得到的结果和实验数据比较吻合。该代数式模型不仅和实验数据吻合,也和基于积分形式的热导率以及玻尔兹曼传输方程获得预测值一致。该数值热导率的建模和ISE-TCAD电热模拟结果显示,如果不考虑声子边界散射引起的热导率的减小,SOI晶体管的电学和热学性能的评估都会受到比较大的影响。
2.从能带角度定性地分析了应力对Si中载流子迁移率的影响,经过分析研究提出了弛豫Si1-xGex层上应变Si n型金属氧化物半导体场效应晶体管(nMOSFET)低场电子迁移率模型,该模型计算得到的结果与报道的实验数据以及ISE模拟得到的结果一致。此外研究了温度和应变Si膜厚度对Si/Si1-xGex nMOSFET中电子迁移率的影响。研究结果显示：由于温度的升高会增加声子与电子的散射概率,导致声学声子散射迁移率降低。阱内的量子效应使得载流子随着厚度的减小而减小,引起载流子通过低迁移率的弛豫Si1-xGex层进行传导,并且弛豫SiGe层和栅氧化层之间非常靠近,这样沟道中界面态密度大大增加,也会降低器件的迁移率。该模型可以模拟任意锗(Ge)组分下的迁移率,数学表达式简单,易于嵌入到器件模拟器中,为设计和优化应变硅电路提供很好的理论支持。
3.为了减小SGOI器件的自加热效应,从改进器件结构的角度提出了一种新型的SGOI器件结构,称之为双台阶式埋氧SGOI MOSFET。研究了该器件的工艺流程,使用器件模拟器ISE对该新型器件结构的电学以及热学特性进行了深入的研究,模拟中考虑了边界声子散射引起热导率的减小以及该热导率随温度的变化关系。研究结果表明：由于沟道与漏端交界处电场强度最大,因此该区域会产生大量热量,迁移率退化最严重。通过减小沟道下埋氧层厚度,沟道区域热量可以很快通过薄的埋氧层传送到衬底,有效地降低了器件的自加热效应,也不会对器件的电容特性造成影响,同时该器件的关态电流,输出特性退化,迁移率的退化以及DIBL效应都得到了明显地抑制。因此,采用沟道下薄埋氧的SGOI MOSFET能够提高器件的整体性能和长期可靠性。
4.随着沟道长度的减小,纳米级SGOI器件对沟道区域电荷的控制能力持续下降,会出现由于短沟道效应(SCE)引起的DIBL效应(Drain Induced Barrier Lowering effect,沟致势垒降低效应)。在纳米级双台阶式埋氧SGOI MOSFET中引入接地平面(Ground Plane)技术减小短沟道效应对器件性能的影响,分析了引入该技术前后,不同沟道应变下不同栅长下该器件电学性能的差异。研究结果表明：当引入Ground Plane技术后,由于吸引了更多来自于漏端电力线的条数,减小了进入沟道区域的边缘电力线的条数,削弱了平行于沟道的横向电场对沟道区域电荷的作用,降低了沟道与漏端之间空间电荷区的宽度,提高了栅对沟道电荷的控制能力,减小了器件的DIBL效应,抑制了泄漏电流,降低了阈值电压的起伏。这为实现纳米级SGOI器件提供了很好的解决方案。
5.为了减小SGOI器件的自加热效应,从引入新的高热导率埋氧层材料的角度提出了一种新的器件结构,称之为SGSOAN(SiGe-silicon-on-aluminum nitride)。在这部分研究中先介绍了这种新型器件的制备工艺流程,接着使用器件模拟器ISE,分析了SGSOAN nMOSFET的电学和热学方面的性能,并和传统的SGOI器件的性能进行了比较。研究结果显示：SGSOAN nMOSFET的输出特性的退化程度远小于SGOI nMOSFET输出特性的退化程度；SGSOAN nMOSFET的跨导高于SGOI nMOSFET的跨导；热阻小于SGOI nMOSFET的热阻一个数量级。此外,研究了Si缓冲层对SGSOAN器件的影响,在Si缓冲层对SGSOAN器件的影响研究中发现：薄Si缓冲层和高Ge组分能够减小器件的阈值电压,提高器件的输出电流。因此,SGSOAN器件结构可以很好地减小SGOI的自加热效应,同时不会影响到器件的电学性能,扩大了其应用的领域。
综上所述,本文在SGOI MOSFET结构的基础上,提出了几种新型器件结构,通过数值仿真和物理建模对其进行了深入的理论分析,研究了它们的器件性能,得到了一些有意义的结果,为纳米SGOI MOSFET的实用化提供了指导。
As the size of complementary metal-oxide-semiconductor transistor enters into the submicron, even deep submicron regime according to the scaling rule, material and device structure in conventional device is approaching, or reaching to their limitation. All these inherent physical limits place the restrictions on the development of the traditional MOSFET device. To overcome this barrier, one desirable solution to these problems is to introduce new material and change the structure of the devices. The new device named SiGe On Insulator (SGOI) originated from combination of SOI and strained silicon (Si) technology has been regarded as a promising device in the nanometer regime and it is investigated in the ways of device structure, physical modeling and reliability for the novel SGOI MOSFET in this thesis, respectively. The major research work and results are as follows:
1. This section develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to the temperature range of 300-1000K for silicon layer thicknesses fromlOnm to 1μm, which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration.
2. First of all, the effect of strain on the carrier mobility in Si material is analyzed qualitatively from the standpoint of the band. Then, a low field electron mobility model for strained Si grown on relaxed Si1-xGex layer is proposed. The results using this model are in well agreement with the reported experimental results and simulation results from ISE device simulator. Furthermore, the effects of temperature and strained Si film thickness on the electron mobility in Si/Si1-xGex nMOSFET are also investigated. The results indicate, the rise in temperature increases the scattering ratio between phonon and electron, leading to the degradation in acoustic phonon scattering mobility. It is shown that the quantum effect in well leads to the degradation in mobility resulting from decreasing thickness, therefore, many electrons are forced to conduct through the low mobility relaxed SiGe layer. And increased interface state density due to the close proximity of the oxide to the SiGe will also limit the performance of the device. This mobility in any germanium (Ge) content can be reflected using this model. Mathematical expression of the mobility is so easy that can be incorporated in general device simulator without difficulty.
3. For reducing the heating effect of SGOI devices, a novel SGOI device structure called SGOI MOSFET with double step buried oxide is proposed from the angle of improving device structure. Firstly, the process flow for this device is outlined. Then, the electrical and thermal characteristics for this device have been studied using device emulator ISE. During the simulation, the decrease in thermal conductivity due to the boundary phonon scattering and dependence of thermal conductivity on temperature have been taken into accounted. The research results indicate that, because the peak electric field occurs in the junction of channel and drain terminal, large amount of heat is generated in this region, therefore, the degradation in mobility at which is most serious. By reducing buried oxide thickness below the channel can eliminate heating effect of the device and has not degraded capacitive characteristics of this device greatly. In the meanwhile, standoff current, output characteristics degradation, the mobility degradation and DIBL effect have been suppressed efficiently. Therefore, employing SGOI MOSFET with a moderate thickness of buried oxide can improve overall device performance and long-term reliability.
4. With the decrease of the channel length, control ability nanoscale SGOI devices over electron charge in the channel begins to drop, leading to drain induced barrier lowering (DIBL) effect caused by short channel effect (SCE). We introduce ground plane (GP) technology to decrease this negative effect on performance of the device, analyze the difference in electrical properties of the device with different Ge content and different gate length.The results of the study indicate that, when introducing ground plane technology, more electric field lines coming from the drain region are inclined to extend toward substrate. The number of electric field lines entering the channel region decreases. The effect of the transverse electric field parallel to channel on the charge in the channel is eliminated. The width of space charge region is narrowed. The control ability of the gate electrode over channel charge has been improved due to the decreased electric field lines penetration through buried oxide layer, weakening DIBL effect of the device, suppressing the leakage current, lowering the threshold voltage fluctuations. This comes up with a good solution to realizing nanoscale SGOI device.
5. In order to reduce the heating effect of SGOI devices, a new kind of device structure called SGSOAN (SiGe-silicon-on-aluminum nitride) is put forward in terms of introducing a new buried oxide layer material with high conductivity. In this part of the study, the process flow of this new device is presented first, then electrical and thermal properties of this device is analyzed using device emulator and compared with the performance of the traditional SGOI devices. Research results show that the degradation in output characteristics of SGSOAN nMOSFET is far less than that of SGOI nMOSFET. The transconductance of SGSOAN nMOSFET is higher than that of SGOI nMOSFET. And thermal resistance of SGSOAN is less than one order of magnitude of that of SGOI nMOSFET. In addition, the effect of Si buffer layer on the performance of SGSOAN device is also studied. Results show that, both thin Si buffer layer and high Ge content decrease device threshold voltage, improve the output current. Therefore, SGSOAN device structure can not only reduce the heating effect of SGOI, but also will not affect the electrical properties.
In the conclusion, several novel SGOI MOSFETs are proposed and studied on the device characteristics in this dissertation. The quantitative theoretical analyses are taken through numerical simulation and modeling methods to a great deal of basic mechanism problems. A lot of meaningful results are obtained and the guideline for the Nanometer SGOI MOSFET is presented in this thesis.
1.论文通过合理地引入数学表达式,考虑了纯硅和掺杂硅中由于声子边界散射引起热导率的减小。在温度范围从300到1000K,硅膜厚度从10nm到1μm之间应用该模型得到的结果和实验数据比较吻合。该代数式模型不仅和实验数据吻合,也和基于积分形式的热导率以及玻尔兹曼传输方程获得预测值一致。该数值热导率的建模和ISE-TCAD电热模拟结果显示,如果不考虑声子边界散射引起的热导率的减小,SOI晶体管的电学和热学性能的评估都会受到比较大的影响。
2.从能带角度定性地分析了应力对Si中载流子迁移率的影响,经过分析研究提出了弛豫Si1-xGex层上应变Si n型金属氧化物半导体场效应晶体管(nMOSFET)低场电子迁移率模型,该模型计算得到的结果与报道的实验数据以及ISE模拟得到的结果一致。此外研究了温度和应变Si膜厚度对Si/Si1-xGex nMOSFET中电子迁移率的影响。研究结果显示：由于温度的升高会增加声子与电子的散射概率,导致声学声子散射迁移率降低。阱内的量子效应使得载流子随着厚度的减小而减小,引起载流子通过低迁移率的弛豫Si1-xGex层进行传导,并且弛豫SiGe层和栅氧化层之间非常靠近,这样沟道中界面态密度大大增加,也会降低器件的迁移率。该模型可以模拟任意锗(Ge)组分下的迁移率,数学表达式简单,易于嵌入到器件模拟器中,为设计和优化应变硅电路提供很好的理论支持。
3.为了减小SGOI器件的自加热效应,从改进器件结构的角度提出了一种新型的SGOI器件结构,称之为双台阶式埋氧SGOI MOSFET。研究了该器件的工艺流程,使用器件模拟器ISE对该新型器件结构的电学以及热学特性进行了深入的研究,模拟中考虑了边界声子散射引起热导率的减小以及该热导率随温度的变化关系。研究结果表明：由于沟道与漏端交界处电场强度最大,因此该区域会产生大量热量,迁移率退化最严重。通过减小沟道下埋氧层厚度,沟道区域热量可以很快通过薄的埋氧层传送到衬底,有效地降低了器件的自加热效应,也不会对器件的电容特性造成影响,同时该器件的关态电流,输出特性退化,迁移率的退化以及DIBL效应都得到了明显地抑制。因此,采用沟道下薄埋氧的SGOI MOSFET能够提高器件的整体性能和长期可靠性。
4.随着沟道长度的减小,纳米级SGOI器件对沟道区域电荷的控制能力持续下降,会出现由于短沟道效应(SCE)引起的DIBL效应(Drain Induced Barrier Lowering effect,沟致势垒降低效应)。在纳米级双台阶式埋氧SGOI MOSFET中引入接地平面(Ground Plane)技术减小短沟道效应对器件性能的影响,分析了引入该技术前后,不同沟道应变下不同栅长下该器件电学性能的差异。研究结果表明：当引入Ground Plane技术后,由于吸引了更多来自于漏端电力线的条数,减小了进入沟道区域的边缘电力线的条数,削弱了平行于沟道的横向电场对沟道区域电荷的作用,降低了沟道与漏端之间空间电荷区的宽度,提高了栅对沟道电荷的控制能力,减小了器件的DIBL效应,抑制了泄漏电流,降低了阈值电压的起伏。这为实现纳米级SGOI器件提供了很好的解决方案。
5.为了减小SGOI器件的自加热效应,从引入新的高热导率埋氧层材料的角度提出了一种新的器件结构,称之为SGSOAN(SiGe-silicon-on-aluminum nitride)。在这部分研究中先介绍了这种新型器件的制备工艺流程,接着使用器件模拟器ISE,分析了SGSOAN nMOSFET的电学和热学方面的性能,并和传统的SGOI器件的性能进行了比较。研究结果显示：SGSOAN nMOSFET的输出特性的退化程度远小于SGOI nMOSFET输出特性的退化程度；SGSOAN nMOSFET的跨导高于SGOI nMOSFET的跨导；热阻小于SGOI nMOSFET的热阻一个数量级。此外,研究了Si缓冲层对SGSOAN器件的影响,在Si缓冲层对SGSOAN器件的影响研究中发现：薄Si缓冲层和高Ge组分能够减小器件的阈值电压,提高器件的输出电流。因此,SGSOAN器件结构可以很好地减小SGOI的自加热效应,同时不会影响到器件的电学性能,扩大了其应用的领域。
综上所述,本文在SGOI MOSFET结构的基础上,提出了几种新型器件结构,通过数值仿真和物理建模对其进行了深入的理论分析,研究了它们的器件性能,得到了一些有意义的结果,为纳米SGOI MOSFET的实用化提供了指导。
As the size of complementary metal-oxide-semiconductor transistor enters into the submicron, even deep submicron regime according to the scaling rule, material and device structure in conventional device is approaching, or reaching to their limitation. All these inherent physical limits place the restrictions on the development of the traditional MOSFET device. To overcome this barrier, one desirable solution to these problems is to introduce new material and change the structure of the devices. The new device named SiGe On Insulator (SGOI) originated from combination of SOI and strained silicon (Si) technology has been regarded as a promising device in the nanometer regime and it is investigated in the ways of device structure, physical modeling and reliability for the novel SGOI MOSFET in this thesis, respectively. The major research work and results are as follows:
1. This section develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to the temperature range of 300-1000K for silicon layer thicknesses fromlOnm to 1μm, which agrees well with the experimental data. In addition, the algebraic model has an excellent agreement with both the experimental data and predictions of thin-film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation. The analytical thermal modeling and ISE-TCAD electrothermal simulations confirm that both the electrical and thermal performances of SOI transistor can be largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration.
2. First of all, the effect of strain on the carrier mobility in Si material is analyzed qualitatively from the standpoint of the band. Then, a low field electron mobility model for strained Si grown on relaxed Si1-xGex layer is proposed. The results using this model are in well agreement with the reported experimental results and simulation results from ISE device simulator. Furthermore, the effects of temperature and strained Si film thickness on the electron mobility in Si/Si1-xGex nMOSFET are also investigated. The results indicate, the rise in temperature increases the scattering ratio between phonon and electron, leading to the degradation in acoustic phonon scattering mobility. It is shown that the quantum effect in well leads to the degradation in mobility resulting from decreasing thickness, therefore, many electrons are forced to conduct through the low mobility relaxed SiGe layer. And increased interface state density due to the close proximity of the oxide to the SiGe will also limit the performance of the device. This mobility in any germanium (Ge) content can be reflected using this model. Mathematical expression of the mobility is so easy that can be incorporated in general device simulator without difficulty.
3. For reducing the heating effect of SGOI devices, a novel SGOI device structure called SGOI MOSFET with double step buried oxide is proposed from the angle of improving device structure. Firstly, the process flow for this device is outlined. Then, the electrical and thermal characteristics for this device have been studied using device emulator ISE. During the simulation, the decrease in thermal conductivity due to the boundary phonon scattering and dependence of thermal conductivity on temperature have been taken into accounted. The research results indicate that, because the peak electric field occurs in the junction of channel and drain terminal, large amount of heat is generated in this region, therefore, the degradation in mobility at which is most serious. By reducing buried oxide thickness below the channel can eliminate heating effect of the device and has not degraded capacitive characteristics of this device greatly. In the meanwhile, standoff current, output characteristics degradation, the mobility degradation and DIBL effect have been suppressed efficiently. Therefore, employing SGOI MOSFET with a moderate thickness of buried oxide can improve overall device performance and long-term reliability.
4. With the decrease of the channel length, control ability nanoscale SGOI devices over electron charge in the channel begins to drop, leading to drain induced barrier lowering (DIBL) effect caused by short channel effect (SCE). We introduce ground plane (GP) technology to decrease this negative effect on performance of the device, analyze the difference in electrical properties of the device with different Ge content and different gate length.The results of the study indicate that, when introducing ground plane technology, more electric field lines coming from the drain region are inclined to extend toward substrate. The number of electric field lines entering the channel region decreases. The effect of the transverse electric field parallel to channel on the charge in the channel is eliminated. The width of space charge region is narrowed. The control ability of the gate electrode over channel charge has been improved due to the decreased electric field lines penetration through buried oxide layer, weakening DIBL effect of the device, suppressing the leakage current, lowering the threshold voltage fluctuations. This comes up with a good solution to realizing nanoscale SGOI device.
5. In order to reduce the heating effect of SGOI devices, a new kind of device structure called SGSOAN (SiGe-silicon-on-aluminum nitride) is put forward in terms of introducing a new buried oxide layer material with high conductivity. In this part of the study, the process flow of this new device is presented first, then electrical and thermal properties of this device is analyzed using device emulator and compared with the performance of the traditional SGOI devices. Research results show that the degradation in output characteristics of SGSOAN nMOSFET is far less than that of SGOI nMOSFET. The transconductance of SGSOAN nMOSFET is higher than that of SGOI nMOSFET. And thermal resistance of SGSOAN is less than one order of magnitude of that of SGOI nMOSFET. In addition, the effect of Si buffer layer on the performance of SGSOAN device is also studied. Results show that, both thin Si buffer layer and high Ge content decrease device threshold voltage, improve the output current. Therefore, SGSOAN device structure can not only reduce the heating effect of SGOI, but also will not affect the electrical properties.
In the conclusion, several novel SGOI MOSFETs are proposed and studied on the device characteristics in this dissertation. The quantitative theoretical analyses are taken through numerical simulation and modeling methods to a great deal of basic mechanism problems. A lot of meaningful results are obtained and the guideline for the Nanometer SGOI MOSFET is presented in this thesis.
引文
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