SOI横向高压器件纵向耐压理论与新结构
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摘要
SOI(Silicon On Insulator)即“绝缘体上的硅”被称为二十一世纪的硅集成技术,其独特的结构带来隔离性能好、漏电流小、速度快、抗辐照和功耗低等优点,充分发挥了硅集成电路技术的潜力,特别是SOI高压集成电路(High Voltage Integrated Circuit,HVIC)在未来空天抗辐照领域具有特殊作用,因而得以广泛发展和应用。SOI横向高压器件作为HVIC的基石,由于介质层阻止了其耗尽区向衬底层扩展,使得习用的器件纵向耐压仅由顶层硅和介质层承担。而因隔离和散热的限制,顶层硅和介质层都不能太厚,同时由界面处无电荷高斯定理,使得器件击穿时的介质层电场仅为硅临界场的3倍即100V/μm左右,远未达到实际常用介质材料如SiO2的临界场600V/μm,所以SOI横向高压器件纵向耐压较低,限制了HVIC的应用和发展,目前投入应用的还没有突破600V的瓶颈。对此,国内外众多学者进行了深入研究,当前工作主要集中在新理论模型和新器件结构两个方面。
本文在对习用的SOI横向高压器件研究的基础上,围绕纵向耐压新理论、新模型和新器件结构进行研究。完善一个统一的纵向耐压新理论-介质场增强(ENhanced DIelectric layer Field,ENDIF)普适理论;首次建立一项新的电场模型-基于阈值能量经典雪崩击穿理论的硅临界击穿电场与其厚度定量关系模型;在ENIDF指导下提出两类电荷型SOI高压器件新结构-电荷岛型高压器件和复合介质埋层高压器件。
第一,完善介质场增强ENDIF理论,是优化设计SOI横向高压器件纵向耐压的普适理论。该理论基于介质场临界化的思想,通过增强介质层电场而提高SOI器件的纵向击穿电压。根据包含界面电荷的高斯定理,ENDIF给出增强介质层电场的三类技术:采用具有可变高临界电场的超薄顶层硅;引入低介电系数介质埋层;在介质层界面引入电荷。用ENDIF对现有典型纵向耐压结构进行理论上的概括与解释,并用以指导新的器件结构设计。ENDIF理论是新的高压SOI器件击穿电压终端理论,它突破了传统SOI横向高压器件的局限。
第二,首次建立硅临界电场与其厚度定量关系解析模型。基于阈值能量经典雪崩击穿理论,选择计及阈值能量的电离率公式,首次推导出适用于厚、薄硅层的硅临界电场与其厚度以及适用于高、低掺杂的硅临界电场与其掺杂浓度的新定量关系模型,获得了超薄硅层或者超高浓度情况下远高于常规30V/μm的硅临界电场,并由此获得SOI高压器件的介质场与纵向耐压的统一解析模型。讨论纳米级超薄硅层的临界场与电离率弛豫关系半经典模型。最后将该研究方法推广应用于其他半导体材料及器件。
第三,在ENDIF指导下,提出两类新的电荷型介质场增强高压器件-具有界面电荷岛的系列高压器件和具有复合埋层的SOI高压器件。
1)具有界面电荷岛的系列高压器件(Charge Islands,CI)。该类器件在介质层界面注入高浓度掺杂区,未耗尽高掺杂区内的电离杂质库仑力以及电场力的综合作用将在界面束缚电荷,利用界面电荷对介质场的增强作用和对顶层硅电场的削弱作用来提高器件耐压。主要包括:(1)界面电荷岛SOI高压器件(CI SOI),在5μm顶层硅、1μm介质层和60μm漂移区获得了606V的高压,介质场达582V/μm;(2)界面电荷岛部分SOI高压器件(CI PSOI),求解二维泊松方程推导此类结构纵向界面电场解析模型,获得631V高压,其最高表面温度分别比常规SOI和PSOI结构降低14.91K和7.66K;(3)改进型的界面电荷岛部分SOI高压器件(ICI PSOI),在80μm漂移区和20μm硅窗口上获得耐压663V的ICI PSOI,较相同尺寸CI PSOI提高85V,同时保持较低的自热效应;(4)基于ESIMOX技术的CI SOI高压器件,在2μm顶层硅、0.375μm介质层和15μm漂移区上获得了230V的耐压,远高于常规结构;(5)双面界面电荷岛SOI高压器件(DCI PSOI),获得了750V的耐压,高于相同尺寸下单面电荷岛结构的685V及常规SOI结构的206V。
2)复合埋层的SOI高压器件(SOI with Composite Buried Layer,CBL SOI)。该类结构的介质埋层包含两层氧化层,两层埋氧之间填充多晶,利用两层埋氧承受耐压,且多晶硅下界面的电荷增强了第二埋氧层的电场,从而提高器件耐压。主要包括:(1)单窗口双埋层SOI高压器件(SWCBL SOI),该结构第一埋层开有一个硅窗口,获得865V的高压,高于相同尺寸常规SOI结构232V;(2)双窗口双埋层SOI高压器件(DWCBL SOI),该结构第一层埋氧层开有两个窗口,并且上下两个埋氧层相连。在20μm顶层硅、2μm第一埋氧层、1μm第二埋氧层和80μm漂移区上获得了1040V的高压,在保持高耐压的同时具有较低的自热效应。在对SWCBL SOI耐压机理研究的基础上,对其进行实验研制。详细设计实验方案,在2.5μm第一埋氧层、0.5μm第二埋氧层和80μm漂移区上研制了耐压达761V的SOI LDMOS器件,突破了实用SOI器件耐压不超过600V的瓶颈。
SOI (Silicon On Insulator) fully exerts the potential of silicon-based integrated circuit due to the advantages such as superior isolation, reduced leakage current, high speed, perfect irradiation and low power dissipation because of its unique structure, and therefore, it is widely developed and applied. Dielectric buried layer prevents the depletion layer spreading into the substrate layer, and so, as the footstone of SOI HVIC (High Voltage Integrated Circuit), SOI lateral high voltage device limits the application of SOI HVIC because of its low vertical breakdown voltage (BV) as a result of the Gauss-theory without interface charges. Up to now, the breakdown voltage of the applied SOI device is less than 600V. To resolve the problem, semiconductor researchers have carried out plentiful work, and new theory models and new device structures are their two key disquisitive aspects.
In this thesis, the novel theory, the new model and the novel device structures are researched aiming at the vertical breakdown voltage of SOI lateral high voltage devices. A unified vertical breakdown voltage of ENDIF (ENhanced DIelectric layer Field) theory is consummated. Based ENDIF, a new silicon critical electric field model based on threshold energy avalanche breakdown classical theory and two kinds of novel charge-mode high voltage devices (SOI high voltage devices with interface charge island and composite buried layer) are reported. Operating mechanisms of the proposed devices are investigated, the analytical models of breakdown voltage and electric field are presented, and some experimental results are obtained.
1. ENDIF is consummated. Based on the concept of critical field approaching for dielectric buried layer, ENIDF is proposed whose standpoint is to increase vertical breakdown voltage by enhancing the electric field of dielectric buried layer (EI). From the continuity theorem of electric displacement including interface charge, three approaches to enhance dielectric layer electric field are presented by the ENDIF:①using a thin silicon layer with high critical electric field (ES,C);②introducing low permittivity dielectric buried layer;③implementing interface charges on the interface of dielectric layer. The ENDIF can well explain several existing SOI HV device structures and it is a new and effective rule for SOI HV devices, giving theoretical direction for increasing the vertical breakdown voltage.
2. Based on the ENDIF, the analytical mode of silicon critical electric field on silicon layer thickness (tS) is firstly presented. By threshold energy avalanche breakdown classical theory and the effective ionization rate considering the threshold energy of silicon, a new dependence of ES,C on tS which is applicable for both thin and thick silicon layer and a new formula of ES,C on impurity concentration in silicon (Nd) which is applicable for both low and high impurity concentration are obtained, from which, expressions of EI and BV are given. Moreover, the semi-classical model of the relaxation dependence between critical electric field and ionization rate for nano-level unltrathin silicon layer is discussed. Finally, the researchful method is used to other semiconductor materials and devices.
3. Based on the ENDIF, two kinds of novel charge-mode high voltage devices - interface charge island SOI and SOI with composite buried layer are reported.
(1) Interface Charge Islands SOI device The structures are characterized by a charge islands layer on the interface of dielectric buried layer in which the equidistant high concentration n+-regions are inserted. Interface charges are located on the interface by the compositive operations of electric field force and Coulomb’s force with high concentration ionized donors in the undepleted n+-regions. The induced inversion holes greatly enhance the electric field of the buried dielectric layer and therefore, effectively increase device breakdown voltage. Include:①CI SOI (Charge Islands SOI). BV=606V are obtained on 5μm silicon layer and 1μm dielectric buried layer, and EI reaches to 582V/μm;②Charge Islands partial-SOI (CI PSOI). An analytical model of the vertical interface electric field for the CI PSOI is derived. BV=631V is obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 15μm silicon window, and enhanced EI (△EI) by interface charges reaches to 498.2V/μm, at the same time, the maximal surface temperature of CI SOI reduces by 7.66K and 14.91K in comparison with the conventional PSOI and SOI, respectively;③Improved Charge Islands partial-SOI (ICI PSOI). BV of 663V for ICI PSOI are obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 20μm silicon window, which is larger by 85V than that of CI PSOI with the same structure parameters, with a low self-heating effect;④CI SOI based on ESIMOX. BV of 230V is obtained on 2μm silicon layer, 0.375μm dielectric buried layer and 15μm drift region, which is much larger than that of the conventional SOI;⑤DCI PSOI (Double-side Charge Islands SOI). BV=750V is obtained on 5μm silicon layer, 1μm dielectric buried layer and 70μm compared with 685V of CI SOI and 206V of the conventional SOI.
(2) SOI with Composite Buried Layer (CBL SOI)
The dielectric buried layer of the structures is made of two oxide layers and polysilicon between them. Its breakdown voltage is shared by the two oxide layers, furthermore, the charges on the bottom interface of polysilicon layer enhance the second buried layer electric field, thus breakdown voltage is increased. Include:①SOI with Single-Window Composite Buried Layer (SWCBL SOI). There is a single silicon window in the first buried layer. BV=865V is obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm compared with 633V of the conventional SOI.②SOI with Dingle-Window Composite Buried Layer (DWCBL SOI). There are two silicon windows in the first buried layer, and two buried layers are connected by an oxide layer. A high BV of 1040V is obtained on 20μm silicon layer, 2μm the first buried layer, 1μm the second buried layer and 80μm, and△EI reaches to 498.2V/μm, with a low self-heating effect. Moreover, 761V SWCBL SOI LDMOS is experimentally obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm, which breaks through the BV <600V limitation of the conventionally applied SOI device.
本文在对习用的SOI横向高压器件研究的基础上,围绕纵向耐压新理论、新模型和新器件结构进行研究。完善一个统一的纵向耐压新理论-介质场增强(ENhanced DIelectric layer Field,ENDIF)普适理论;首次建立一项新的电场模型-基于阈值能量经典雪崩击穿理论的硅临界击穿电场与其厚度定量关系模型;在ENIDF指导下提出两类电荷型SOI高压器件新结构-电荷岛型高压器件和复合介质埋层高压器件。
第一,完善介质场增强ENDIF理论,是优化设计SOI横向高压器件纵向耐压的普适理论。该理论基于介质场临界化的思想,通过增强介质层电场而提高SOI器件的纵向击穿电压。根据包含界面电荷的高斯定理,ENDIF给出增强介质层电场的三类技术:采用具有可变高临界电场的超薄顶层硅;引入低介电系数介质埋层;在介质层界面引入电荷。用ENDIF对现有典型纵向耐压结构进行理论上的概括与解释,并用以指导新的器件结构设计。ENDIF理论是新的高压SOI器件击穿电压终端理论,它突破了传统SOI横向高压器件的局限。
第二,首次建立硅临界电场与其厚度定量关系解析模型。基于阈值能量经典雪崩击穿理论,选择计及阈值能量的电离率公式,首次推导出适用于厚、薄硅层的硅临界电场与其厚度以及适用于高、低掺杂的硅临界电场与其掺杂浓度的新定量关系模型,获得了超薄硅层或者超高浓度情况下远高于常规30V/μm的硅临界电场,并由此获得SOI高压器件的介质场与纵向耐压的统一解析模型。讨论纳米级超薄硅层的临界场与电离率弛豫关系半经典模型。最后将该研究方法推广应用于其他半导体材料及器件。
第三,在ENDIF指导下,提出两类新的电荷型介质场增强高压器件-具有界面电荷岛的系列高压器件和具有复合埋层的SOI高压器件。
1)具有界面电荷岛的系列高压器件(Charge Islands,CI)。该类器件在介质层界面注入高浓度掺杂区,未耗尽高掺杂区内的电离杂质库仑力以及电场力的综合作用将在界面束缚电荷,利用界面电荷对介质场的增强作用和对顶层硅电场的削弱作用来提高器件耐压。主要包括:(1)界面电荷岛SOI高压器件(CI SOI),在5μm顶层硅、1μm介质层和60μm漂移区获得了606V的高压,介质场达582V/μm;(2)界面电荷岛部分SOI高压器件(CI PSOI),求解二维泊松方程推导此类结构纵向界面电场解析模型,获得631V高压,其最高表面温度分别比常规SOI和PSOI结构降低14.91K和7.66K;(3)改进型的界面电荷岛部分SOI高压器件(ICI PSOI),在80μm漂移区和20μm硅窗口上获得耐压663V的ICI PSOI,较相同尺寸CI PSOI提高85V,同时保持较低的自热效应;(4)基于ESIMOX技术的CI SOI高压器件,在2μm顶层硅、0.375μm介质层和15μm漂移区上获得了230V的耐压,远高于常规结构;(5)双面界面电荷岛SOI高压器件(DCI PSOI),获得了750V的耐压,高于相同尺寸下单面电荷岛结构的685V及常规SOI结构的206V。
2)复合埋层的SOI高压器件(SOI with Composite Buried Layer,CBL SOI)。该类结构的介质埋层包含两层氧化层,两层埋氧之间填充多晶,利用两层埋氧承受耐压,且多晶硅下界面的电荷增强了第二埋氧层的电场,从而提高器件耐压。主要包括:(1)单窗口双埋层SOI高压器件(SWCBL SOI),该结构第一埋层开有一个硅窗口,获得865V的高压,高于相同尺寸常规SOI结构232V;(2)双窗口双埋层SOI高压器件(DWCBL SOI),该结构第一层埋氧层开有两个窗口,并且上下两个埋氧层相连。在20μm顶层硅、2μm第一埋氧层、1μm第二埋氧层和80μm漂移区上获得了1040V的高压,在保持高耐压的同时具有较低的自热效应。在对SWCBL SOI耐压机理研究的基础上,对其进行实验研制。详细设计实验方案,在2.5μm第一埋氧层、0.5μm第二埋氧层和80μm漂移区上研制了耐压达761V的SOI LDMOS器件,突破了实用SOI器件耐压不超过600V的瓶颈。
SOI (Silicon On Insulator) fully exerts the potential of silicon-based integrated circuit due to the advantages such as superior isolation, reduced leakage current, high speed, perfect irradiation and low power dissipation because of its unique structure, and therefore, it is widely developed and applied. Dielectric buried layer prevents the depletion layer spreading into the substrate layer, and so, as the footstone of SOI HVIC (High Voltage Integrated Circuit), SOI lateral high voltage device limits the application of SOI HVIC because of its low vertical breakdown voltage (BV) as a result of the Gauss-theory without interface charges. Up to now, the breakdown voltage of the applied SOI device is less than 600V. To resolve the problem, semiconductor researchers have carried out plentiful work, and new theory models and new device structures are their two key disquisitive aspects.
In this thesis, the novel theory, the new model and the novel device structures are researched aiming at the vertical breakdown voltage of SOI lateral high voltage devices. A unified vertical breakdown voltage of ENDIF (ENhanced DIelectric layer Field) theory is consummated. Based ENDIF, a new silicon critical electric field model based on threshold energy avalanche breakdown classical theory and two kinds of novel charge-mode high voltage devices (SOI high voltage devices with interface charge island and composite buried layer) are reported. Operating mechanisms of the proposed devices are investigated, the analytical models of breakdown voltage and electric field are presented, and some experimental results are obtained.
1. ENDIF is consummated. Based on the concept of critical field approaching for dielectric buried layer, ENIDF is proposed whose standpoint is to increase vertical breakdown voltage by enhancing the electric field of dielectric buried layer (EI). From the continuity theorem of electric displacement including interface charge, three approaches to enhance dielectric layer electric field are presented by the ENDIF:①using a thin silicon layer with high critical electric field (ES,C);②introducing low permittivity dielectric buried layer;③implementing interface charges on the interface of dielectric layer. The ENDIF can well explain several existing SOI HV device structures and it is a new and effective rule for SOI HV devices, giving theoretical direction for increasing the vertical breakdown voltage.
2. Based on the ENDIF, the analytical mode of silicon critical electric field on silicon layer thickness (tS) is firstly presented. By threshold energy avalanche breakdown classical theory and the effective ionization rate considering the threshold energy of silicon, a new dependence of ES,C on tS which is applicable for both thin and thick silicon layer and a new formula of ES,C on impurity concentration in silicon (Nd) which is applicable for both low and high impurity concentration are obtained, from which, expressions of EI and BV are given. Moreover, the semi-classical model of the relaxation dependence between critical electric field and ionization rate for nano-level unltrathin silicon layer is discussed. Finally, the researchful method is used to other semiconductor materials and devices.
3. Based on the ENDIF, two kinds of novel charge-mode high voltage devices - interface charge island SOI and SOI with composite buried layer are reported.
(1) Interface Charge Islands SOI device The structures are characterized by a charge islands layer on the interface of dielectric buried layer in which the equidistant high concentration n+-regions are inserted. Interface charges are located on the interface by the compositive operations of electric field force and Coulomb’s force with high concentration ionized donors in the undepleted n+-regions. The induced inversion holes greatly enhance the electric field of the buried dielectric layer and therefore, effectively increase device breakdown voltage. Include:①CI SOI (Charge Islands SOI). BV=606V are obtained on 5μm silicon layer and 1μm dielectric buried layer, and EI reaches to 582V/μm;②Charge Islands partial-SOI (CI PSOI). An analytical model of the vertical interface electric field for the CI PSOI is derived. BV=631V is obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 15μm silicon window, and enhanced EI (△EI) by interface charges reaches to 498.2V/μm, at the same time, the maximal surface temperature of CI SOI reduces by 7.66K and 14.91K in comparison with the conventional PSOI and SOI, respectively;③Improved Charge Islands partial-SOI (ICI PSOI). BV of 663V for ICI PSOI are obtained on 5μm silicon layer, 1μm dielectric buried layer, 80μm drift region and 20μm silicon window, which is larger by 85V than that of CI PSOI with the same structure parameters, with a low self-heating effect;④CI SOI based on ESIMOX. BV of 230V is obtained on 2μm silicon layer, 0.375μm dielectric buried layer and 15μm drift region, which is much larger than that of the conventional SOI;⑤DCI PSOI (Double-side Charge Islands SOI). BV=750V is obtained on 5μm silicon layer, 1μm dielectric buried layer and 70μm compared with 685V of CI SOI and 206V of the conventional SOI.
(2) SOI with Composite Buried Layer (CBL SOI)
The dielectric buried layer of the structures is made of two oxide layers and polysilicon between them. Its breakdown voltage is shared by the two oxide layers, furthermore, the charges on the bottom interface of polysilicon layer enhance the second buried layer electric field, thus breakdown voltage is increased. Include:①SOI with Single-Window Composite Buried Layer (SWCBL SOI). There is a single silicon window in the first buried layer. BV=865V is obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm compared with 633V of the conventional SOI.②SOI with Dingle-Window Composite Buried Layer (DWCBL SOI). There are two silicon windows in the first buried layer, and two buried layers are connected by an oxide layer. A high BV of 1040V is obtained on 20μm silicon layer, 2μm the first buried layer, 1μm the second buried layer and 80μm, and△EI reaches to 498.2V/μm, with a low self-heating effect. Moreover, 761V SWCBL SOI LDMOS is experimentally obtained on 20μm silicon layer, 2.5μm the first buried layer, 0.5μm the second buried layer and 80μm, which breaks through the BV <600V limitation of the conventionally applied SOI device.
引文
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