基于高低压兼容工艺的高压驱动集成电路
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摘要
高压功率集成电路是功率电子学的重要领域,它将高压功率器件与控制和保护电路单片集成,减少了系统中的元件数、互连数和焊点数,不仅提高了系统的可靠性、稳定性,而且减少了系统的功耗、体积、重量和成本,对实现军事装备和民用装置的小型化、智能化和节能化有着重要的意义。在功率单片集成技术中,隔离技术是基础,高低压兼容工艺是关键,可集成的高压功率器件是核心。为此,国内外众多学者提出一系列的可集成高压功率器件和隔离技术,用于硅基和SOI(Silicon On Insulator)基高低压兼容工艺中,以满足不同应用领域的要求。迄今,由于SOI基横向高压器件的纵向耐压限制,尚无实用1000V SOI高压集成电路;而薄膜SOI的背栅效应导致高端器件穿通击穿,使得已有100V以上级薄膜SOI高低压兼容工艺的顶层硅膜厚度至少为1.5μm;对于硅基厚外延高压BCD(BipolarCMOS DMOS)工艺,存在热过程时间长、隔离横向扩散大等不足,且由于DMOS(Double-diffused MOSFET)器件漏极引出带来高压互连(High VoltageInterconnection,HVI)等新的问题。
本文围绕SOI高压器件耐压与背栅效应、高压互连技术和BCD工艺进行研究。提出SOI高压器件的场控REBULF(REduced BULk Field)模型,提出薄膜SOI高压器件的场氧离子注入IFO(Implantation after Field Oxide)技术,提出无浮空场板NFFP(No Floating Field Plate)高压互连结构。基于上述模型、技术和结构,开发PDP(Plasma Display Panel)寻址驱动电路、高压大电流控制电路和高压半桥驱动电路,其中控制电路和半桥驱动电路分别用于某军用装置和民用产品。本文主要有以下三方面工作:
1、提出一种利用背栅场控实现体内场降低的场控REBULF模型。基于背栅场控效应,降低SOI横向高压器件体内漏端电场,而提高体内源端电场,突破习用结构的纵向耐压限制,提高SOI横向高压器件的击穿电压。借助数值仿真,分析背栅场控对厚膜SOI横向高压器件击穿特性的影响,在背栅电压为330V时,实现击穿电压为1020V的场控REBULF LDMOS(Lateral Double-diffused MOSFET),较习用结构提高47.8%。该模型的提出,为SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路。
2、提出一种场氧离子注入IFO技术。该技术包含一个穿通击穿电压判据和一项注入工艺设计,可精确控制薄膜SOI背栅效应导致的高端厚栅氧器件的穿通击穿电压。基于IFO技术和隔离氧化共用技术,开发一种新的1μm超薄膜SOI高低压兼容工艺,将迄今100V以上级薄膜SOI高压工艺的顶层硅膜厚度从1.5μm降至1μm,实现高压NLDMOS(N-channel Lateral Double-diffused MOSFET)、厚栅氧PLDMOS(P-channel Lateral Double-diffused MOSFET)、5V CMOS的单片集成。利用基于IFO技术的薄膜SOI高低压兼容工艺,研制成功64位、80V、20mA PDP寻址驱动电路和用于某军用装置的120V、100mA高压大电流控制电路。
3、提出NFFP高压互连结构。通过求解二维泊松方程,建立具有HVI的单RESURF(Reduced SURface Field)器件表面电场和电势解析模型,利用p-top降场层的结终端扩展作用以及圆形器件结构的曲率效应,增强具有HVI的横向高压器件漂移区耗尽,降低高压互连线对器件击穿特性的有害影响。实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与p-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有HVI的高压器件击穿特性。基于NFFP高压互连结构和硅基薄外延BCD兼容工艺,研制成功880V高压半桥驱动电路,并已形成民用产品。
High voltage power IC is one of the key areas of power electronics. The high voltage power IC allows for the integration of high voltage power devices, control and protection circuits. Since the high voltage power IC reduces the number of system components, interconnection and solder points, it has not only improved system reliability and stability, but also reduced its size, weight and cost. It is of great significance for the miniaturization, intelligence, energy saving of military and civilian equipment. The isolation technology is the basis, the high and low voltage compatible process is very important, and the integrated high voltage power devices are the core to the monolithic power integration technology. For this reason, many scholars at home and abroad have proposed a series of integrated high voltage power devices and isolation technology on bulk silicon and SOI (Silicon On Insulator). The devices and isolation technology are used for high and low voltage compatible process to meet the requirements of different application areas. However, due to the limit of vertical breakdown voltage of lateral SOI high voltage device, there is no any practical 1000 V SOI high voltage IC. Since punch-through breakdown induced by thin layer SOI back-gate effect, the thickness of the top silicon is at least 1.5μm for the existing over 100 V thin layer SOI process. The thick epitaxial Si-based high voltage BCD (Bipolar CMOS DMOS) process has several drawbacks. The long diffusion times result in wider isolation diffusion. The greater lateral diffusion reduces the amount of useful area on a chip. Another important problem for the Si-based high voltage BCD process is HVI (High Voltage Interconnection) metal line extended form the drain contact of DMOS (Double-diffused MOSFET).
This dissertation focuses on breakdown voltage and back-gate effect of SOI high voltage device, HVI technology, and BCD process. A novel field-control REBULF (REduced BULk Field) model for SOI high voltage device, an IFO (Implantation after Field Oxide) technology for SOI high voltage device and a NFFP (No Floating Field Plate) HVI structure are proposed. Based on the proposed model, technology, and structure, we develop a PDP (Plasma Display Panel) data drive IC, a military high voltage high current control circuit, and a series of high voltage half bridge drive ICs. The high voltage high current control circuit has already been used in a military installation, and the high voltage half bridge drive IC products are available in the market. The three main results are as follows.
1. A novel field-control REBULF model is proposed for improving the vertical breakdown voltage of lateral SOI high voltage device. The mechanism of the improved breakdown characteristics is that the electric field distributions of the active region are modulated by back-gate field-control effect. The bulk electric field at the drain side is reduced, the bulk electric field at the source side is increased, and the breakdown voltage of the lateral SOI high voltage device is improved. The impact of the back-gate bias on over 600 V lateral thick layer SOI high voltage device is discussed via numerical simulations. When the back-gate bias is 330V, the breakdown voltage of the field-control REBULF LDMOS (Lateral Double-diffused MOSFET) is 1020V, which is 47.8% greater than that of a conventional LDMOS. The novel model presents a new method for realizing SOI high voltage power device and high voltage IC.
2. A novel IFO technology is proposed for high side thick gate oxide device to avoid punch-through breakdown induced by thin layer SOI back-gate effect. The technology includes a criterion of the punch-through breakdown and an implantation process for precise control of the punch-through breakdown voltage. Based on the proposed IFO technology and the conforming technology of isolation and oxidation, we develop a new thin layer SOI high and low voltage compatible process, which offers NLDMOS (N-channel Lateral Double-diffused MOSFET), PLDMOS (P-channel Lateral Double-diffused MOSFET) and 5 V CMOS devices. The thickness of the top silicon is decreased from 1.5μm to 1μm for the existing over 100 V thin layer SOI process. The thin layer SOI high voltage and low voltage compatible process based on IFO technology is successfully used for a 64-bit PDP data drive IC and a military high voltage high current control circuit. The operating voltage and output current of the PDP data drive IC are 80 V and 20 mA, respectively. The operating voltage and output current of the high voltage high current control circuit are 120 V and 100 mA, respectively. The high voltage high current control circuit has already been used in a military installation.
3. A NFFP HVI structure is proposed to improve the breakdown characteristics of the high voltage device with HVI. An analytical model for the surface potential and electric field distribution of the single RESURF (Reduced SURface Field) device with HVI is presented by solving two-dimensional Poisson equation. Using the effects of junction termination extension of the p-top layer and the curvature of a circular structure, the breakdown voltage of the lateral high voltage device with HVI is improved by spreading the depletion region. Two- and three-dimensional simulation results are presented. The breakdown voltage of the LDMOS with HVI is not exact in the two-dimensional simulation. In agreement with the three-dimensional simulation, the experimental results show that the breakdown voltage of the LDMOS, which depends strongly on the concentration of the p-top layer, will increase with the reduction of the width of the HVI. Based on the proposed NFFP HVI structure and the developed thin epitaxial high voltage BCD process, an 880 V half bridge drive IC is successfully realized. The high voltage half bridge drive IC products are available for civilian areas.
本文围绕SOI高压器件耐压与背栅效应、高压互连技术和BCD工艺进行研究。提出SOI高压器件的场控REBULF(REduced BULk Field)模型,提出薄膜SOI高压器件的场氧离子注入IFO(Implantation after Field Oxide)技术,提出无浮空场板NFFP(No Floating Field Plate)高压互连结构。基于上述模型、技术和结构,开发PDP(Plasma Display Panel)寻址驱动电路、高压大电流控制电路和高压半桥驱动电路,其中控制电路和半桥驱动电路分别用于某军用装置和民用产品。本文主要有以下三方面工作:
1、提出一种利用背栅场控实现体内场降低的场控REBULF模型。基于背栅场控效应,降低SOI横向高压器件体内漏端电场,而提高体内源端电场,突破习用结构的纵向耐压限制,提高SOI横向高压器件的击穿电压。借助数值仿真,分析背栅场控对厚膜SOI横向高压器件击穿特性的影响,在背栅电压为330V时,实现击穿电压为1020V的场控REBULF LDMOS(Lateral Double-diffused MOSFET),较习用结构提高47.8%。该模型的提出,为SOI基高压功率器件和高压集成电路的实现提供了一种新的设计思路。
2、提出一种场氧离子注入IFO技术。该技术包含一个穿通击穿电压判据和一项注入工艺设计,可精确控制薄膜SOI背栅效应导致的高端厚栅氧器件的穿通击穿电压。基于IFO技术和隔离氧化共用技术,开发一种新的1μm超薄膜SOI高低压兼容工艺,将迄今100V以上级薄膜SOI高压工艺的顶层硅膜厚度从1.5μm降至1μm,实现高压NLDMOS(N-channel Lateral Double-diffused MOSFET)、厚栅氧PLDMOS(P-channel Lateral Double-diffused MOSFET)、5V CMOS的单片集成。利用基于IFO技术的薄膜SOI高低压兼容工艺,研制成功64位、80V、20mA PDP寻址驱动电路和用于某军用装置的120V、100mA高压大电流控制电路。
3、提出NFFP高压互连结构。通过求解二维泊松方程,建立具有HVI的单RESURF(Reduced SURface Field)器件表面电场和电势解析模型,利用p-top降场层的结终端扩展作用以及圆形器件结构的曲率效应,增强具有HVI的横向高压器件漂移区耗尽,降低高压互连线对器件击穿特性的有害影响。实验与仿真结果表明,器件的击穿电压随着互连线宽度的减小而增加,并与p-top降场层浓度存在强的依赖关系,三维仿真结果与实验结果较吻合,而二维仿真并不能较好反映具有HVI的高压器件击穿特性。基于NFFP高压互连结构和硅基薄外延BCD兼容工艺,研制成功880V高压半桥驱动电路,并已形成民用产品。
High voltage power IC is one of the key areas of power electronics. The high voltage power IC allows for the integration of high voltage power devices, control and protection circuits. Since the high voltage power IC reduces the number of system components, interconnection and solder points, it has not only improved system reliability and stability, but also reduced its size, weight and cost. It is of great significance for the miniaturization, intelligence, energy saving of military and civilian equipment. The isolation technology is the basis, the high and low voltage compatible process is very important, and the integrated high voltage power devices are the core to the monolithic power integration technology. For this reason, many scholars at home and abroad have proposed a series of integrated high voltage power devices and isolation technology on bulk silicon and SOI (Silicon On Insulator). The devices and isolation technology are used for high and low voltage compatible process to meet the requirements of different application areas. However, due to the limit of vertical breakdown voltage of lateral SOI high voltage device, there is no any practical 1000 V SOI high voltage IC. Since punch-through breakdown induced by thin layer SOI back-gate effect, the thickness of the top silicon is at least 1.5μm for the existing over 100 V thin layer SOI process. The thick epitaxial Si-based high voltage BCD (Bipolar CMOS DMOS) process has several drawbacks. The long diffusion times result in wider isolation diffusion. The greater lateral diffusion reduces the amount of useful area on a chip. Another important problem for the Si-based high voltage BCD process is HVI (High Voltage Interconnection) metal line extended form the drain contact of DMOS (Double-diffused MOSFET).
This dissertation focuses on breakdown voltage and back-gate effect of SOI high voltage device, HVI technology, and BCD process. A novel field-control REBULF (REduced BULk Field) model for SOI high voltage device, an IFO (Implantation after Field Oxide) technology for SOI high voltage device and a NFFP (No Floating Field Plate) HVI structure are proposed. Based on the proposed model, technology, and structure, we develop a PDP (Plasma Display Panel) data drive IC, a military high voltage high current control circuit, and a series of high voltage half bridge drive ICs. The high voltage high current control circuit has already been used in a military installation, and the high voltage half bridge drive IC products are available in the market. The three main results are as follows.
1. A novel field-control REBULF model is proposed for improving the vertical breakdown voltage of lateral SOI high voltage device. The mechanism of the improved breakdown characteristics is that the electric field distributions of the active region are modulated by back-gate field-control effect. The bulk electric field at the drain side is reduced, the bulk electric field at the source side is increased, and the breakdown voltage of the lateral SOI high voltage device is improved. The impact of the back-gate bias on over 600 V lateral thick layer SOI high voltage device is discussed via numerical simulations. When the back-gate bias is 330V, the breakdown voltage of the field-control REBULF LDMOS (Lateral Double-diffused MOSFET) is 1020V, which is 47.8% greater than that of a conventional LDMOS. The novel model presents a new method for realizing SOI high voltage power device and high voltage IC.
2. A novel IFO technology is proposed for high side thick gate oxide device to avoid punch-through breakdown induced by thin layer SOI back-gate effect. The technology includes a criterion of the punch-through breakdown and an implantation process for precise control of the punch-through breakdown voltage. Based on the proposed IFO technology and the conforming technology of isolation and oxidation, we develop a new thin layer SOI high and low voltage compatible process, which offers NLDMOS (N-channel Lateral Double-diffused MOSFET), PLDMOS (P-channel Lateral Double-diffused MOSFET) and 5 V CMOS devices. The thickness of the top silicon is decreased from 1.5μm to 1μm for the existing over 100 V thin layer SOI process. The thin layer SOI high voltage and low voltage compatible process based on IFO technology is successfully used for a 64-bit PDP data drive IC and a military high voltage high current control circuit. The operating voltage and output current of the PDP data drive IC are 80 V and 20 mA, respectively. The operating voltage and output current of the high voltage high current control circuit are 120 V and 100 mA, respectively. The high voltage high current control circuit has already been used in a military installation.
3. A NFFP HVI structure is proposed to improve the breakdown characteristics of the high voltage device with HVI. An analytical model for the surface potential and electric field distribution of the single RESURF (Reduced SURface Field) device with HVI is presented by solving two-dimensional Poisson equation. Using the effects of junction termination extension of the p-top layer and the curvature of a circular structure, the breakdown voltage of the lateral high voltage device with HVI is improved by spreading the depletion region. Two- and three-dimensional simulation results are presented. The breakdown voltage of the LDMOS with HVI is not exact in the two-dimensional simulation. In agreement with the three-dimensional simulation, the experimental results show that the breakdown voltage of the LDMOS, which depends strongly on the concentration of the p-top layer, will increase with the reduction of the width of the HVI. Based on the proposed NFFP HVI structure and the developed thin epitaxial high voltage BCD process, an 880 V half bridge drive IC is successfully realized. The high voltage half bridge drive IC products are available for civilian areas.
引文
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