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Turbo码编译码器的研究与实现
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摘要
Turbo码1993年诞生,以其优秀的抗噪声性能在无线通信系统中广泛应用。3GPP LTE(第三代通信系统长期演进),WiMAX(全球微波接入互操作)等无线通信标准化组织或技术纷纷将Turbo码作为自己的信道编码手段。而大规模数字集成电路技术的发展,使满足各种不同性能需求的Turbo编译码器在硬件上得以实现。
     Turbo码译码算法常用的有软输出Viterbi(维特比)、Log_map(对数化最大后验概率算法)、Max_log_map(简化的最大后验概率算法)等,本文选择性能和复杂度折中的Max_log_map算法作为译法算法,并结合LTE系统规范下的二次置换多项式(QPP)交织器,分析和设计了Turbo编译码器。
     本文在Matlab环境下,从算法选择、交织长度、迭代次数、数据量化及归一化等角度,对Turbo编译器的架构及算法进行仿真分析,确定适合FPGA实现的参数。在选定硬件实现参数的基础上,以FPGA:现场可编程门阵列)为目标平台,用硬件描述语言(HDL)对Turbo编译码器进行了寄存器传输级的(RTL)详细设计。在编码器方面,优化了QPP交织器的关键路径使编码电路的最高频率由130MHz提高到200MHz左右,再结合输入双缓冲机制提高了编码器的吞吐量。在译码器方面,通过合理的并行处理优化了软输入软输出计算模块的加比选关键路径,利用滑窗法减少了存储器的使用,在单个Turbo处理机译码的情况下,本设计的译码器吞吐量接近9Mbps。
Turbo-code was borned in 1993, which has found its way in wireless communication for its outstanding performance. Many Wireless Communication Standards Organization select Turbo-code as their channel codes, like 3GPP LTE, WiMAX, etc. As the developing of VLSI technology, the Turbo-codec meet different system requirements has been implemented in hard-ware.
     The generally used decoding algorithm for Turbo-code include siso-Viterbi, LogMap, Max_Log_Map and so on. This thesis select QPP as the interleaver and use Max_Log_Map as the decoding algorithm for which has a more acceptable complexity and performance.
     Also, some important parameters of Turbo-code like the length of interleaver, iteration times, quantitative of datas and normalized have been anylysised in Matlab. Then, a RTL design of Turbo-code has been done by Verilog-HDL with those special parameters above. Under the platform of FPGA,this thesis get a Turbo encoder with the maximum clock rate at 200MHz, by the optimization for QPP's critical path. As for Turbo-decoder, some ctitical path in SISO'S ACSO cicurit were been parallelzied, and the sliding-window method was employed to reduce the area of RAM and the dual-buffer mechanism was applyed in the Turbo-codec. Finally,this thesis get a Turbo-decoder with the throughput at 9Mbps.
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