高κ栅介质Ge基MOS器件模型及制备工艺研究
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摘要
随着互补金属氧化物半导体(CMOS)器件特征尺寸的不断缩小,Si基MOS器件的发展达到了其物理极限,新的沟道材料,如应力Si、应力SiGe合金、Ge衬底等,因其较高的载流子迁移率而被采用来提高器件的驱动性能。最近几年,高κ栅介质Ge和SiGe MOSFETs的研究是微电子学领域的热点,主要集中于高κ栅介质的制备工艺及其电特性研究。但对淀积后退火工艺,表面预处理工艺,掺Ti的Hf系氧化物等方面的研究较少。而且,在高κ栅介质Ge MOS器件模型研究方面,如阈值电压模型、栅极漏电流模型等,未见到相关报道。本论文即从理论和实验两方面对上述内容进行了相关研究。主要内容分为三个部分:1) SiGe MOSFET的阈值电压模型;2) Ge MOS器件栅极漏电流模型;3) Hf系高κ栅介质Ge MOS器件的制备及其电特性、界面特性的刻化。
本文通过考虑量子效应,提出了一种深亚微米SiGe沟道pMOSFET阈值电压模型,分别考虑了有Si盖帽层和无Si盖帽层两种情况,并讨论了高κ栅介质、短沟道效应和漏致势垒降低效应对阈值电压的影响。模拟结果和实验数据符合良好。利用此模型对器件的主要参数进行了优化设计。
基于WKB近似,在分析高κ栅介质/界面层/Ge衬底能带结构的基础上,提出综合考虑直接隧穿和F-N隧穿的栅极漏电流解析模型,模拟结果与实验数据符合较好,表明该模型对于模拟深亚微米叠层高κ栅介质Ge MOS器件在强反型时的栅极漏电较为准确,但在小栅偏压下(Vg < 0.3 V)存在一定的误差,可能的原因是没有充分考虑空穴密度和陷阱电荷对栅极漏电的影响。实验方面,研究了Ge MOS器件的制备工艺,在Ge衬底上制备出了性能良好的HfTiON、HfTiO以及叠层GeON/HfTiO等高κ栅介质:(1)采用反应磁控溅射方法在Ge衬底上生长HfTiN薄膜,然后利用淀积后退火(PDA)工艺,在湿N2气氛中,利用退火系统中剩余的O2将HfTiN薄膜转化成HfTiON栅介质,制备了性能良好的Ge MOS器件,等效氧化物厚度为2.4nm,等效氧化物电荷密度2. 8×1011 cm-2,界面态密度5.9×1011 eV-1 cm-2,栅极漏电流密度4.7×10-4 Acm-2 (Vg = 1V)。并研究了干湿N2退火对器件性能的影响。结果显示,由于GeOx的易水解特性,湿N2退火有效抑制了低κGeOx界面层的生长,大大降低了界面态和等效氧化物电荷密度,进而降低了栅极漏电流;(2)利用反应磁控溅射方法在Ge衬底上制备超薄HfTiO栅介质,通过调节Ti靶的溅射功率研究了Ti浓度对HfTiO介质性能的影响。实验结果表明,在所研究范围内,随着Ti浓度的增加,HfTiO的介电常数增加到40,但高浓度的Ti引起界面特性的恶化和栅极漏电流密度的增加。为了进一步研究淀积后退火对器件电特性的影响,PDA分别在500°C的湿N2、NH3、NO、N2O气氛中进行300s。实验结果表明,湿N2退火样品呈现出最优的电性能:等效氧化物厚度0.81nm,相对介电常数~35,界面态密度~6.4×1011 eV-1 cm-2,等效氧化物电荷密度~1.96×1011 cm-2,+1V栅压时的栅极漏电流~2.71×10-4 Acm-2;(3)研究了湿NO、N2O、NH3表面预处理工艺对器件性能的影响。采用表面预处理工艺制备了GeOxNy以及GeOxNy/HfTiO叠层栅介质MOS器件。结果表明,湿NO表面预处理对制备亚2nm GeOxNy/HfTiO叠层高κ栅介质,降低其界面态密度和等效氧化物电荷密度,从而减小栅极漏电、增强器件可靠性有着十分重要的作用,其电参数达到:等效氧化物厚度1.88nm,等效氧化物电荷密度9.77×1010cm-2,界面态密度2.41×1011 cm-2eV-1,栅极漏电流4.95×10-5 Acm-2。
As the continual scaling of complementary metal-oxide-semiconductor (CMOS), Si MOS device approaches its fundamental limits, and new channel materials, such as strained Si, strained SiGe alloy and Ge substrate and so on, are explored to improve device performance by enhancing carrier mobility in the channel region. Recently, study on SiGe or Ge MOSFETs with high-κgate dielectric have become hot point, which mainly be focused on fabrication processes and electrical properties of high-κgate dielectric. However, post-deposition anneal, surface pretreatment of substrate, and Hf-based oxides doped Ti, were less involved. Also, the studies on modeling of Ge MOS devices, e.g. threshold voltage model and gate leakage model, were rarely reported too. In this thesis, theoritical and experiment work related to above problems is performed to find relevant solutions. Content of the thesis is devided into three parts: 1) threshold voltage model on SiGe pMOSFET, 2) gate leakage model on Ge MOS, 3) preparations and electrical properties of high-κgate dielectric MOS devices with Hf- and HfTi-based oxide and oxynitride as gate dielectric.
In this work, analytical models on threshold voltage of deep sub-micron SiGe pMOSFETs with high-κgate-dielectric and Si cap layer or without Si cap layer are respectively proposed by considering short-channel effect (SCE), drain-induced barrier lowing (DIBL) and quantumn effect. The simulated results are in good agreement with experimental data. Based on the model, the main parameters of high-κgate dielectric SiGe pMOSFET can be reasonably determined.
For gate-leakage current model, based on the Wentzel-Kramer-Brillouin (WKB) approach, a compact analytical model of Ge MOS device has been developed by taking direct and F-N tunnels into account. Simulated results exhibit a good agreement with experimental data, indicating that the model is suitable for simulating gate leakage current in inversion for deep-submicron Ge MOSFET with stack high-κgate dielectric. However, small error occurs for low gate bias below 0.3 V, probably due to deficiently calculating effects of hole density and trap charges.
MOS devices fabricating process and electric charactristic with HfTi oxidation and oxynitride gate dielectric is investigated as followed. (1) HfTiN gate dielectric films are deposited on n-Ge substrates by the method of reacting magnetron sputtering in N2+Ar ambient, followed by PDA which was carried out at 550°C for 300s in a wet N2 ambient instead of O2 to convert HfTiN into HfTiON by utilizing the residual O2 in PDA system, and super performace for Ge MOS capacitor with HfTiON gate dielectric have been achieved with equivalent oxide thickness of 2.4 nm, equivalent oxide charge density of 2.8×1011 cm-2, interface-state density of 5.9×1011 eV-1 cm-2 and gate leakage current of 4.7×10-4 A cm2 at Vg = 1 V. The effects of dry and wet N2 anneal on dielectrice perporities have been investigated too, results indicate that wet N2 anneal for deposited HfTiN film can induce a great reduction of interface-state/dielectric-charge densities and gate leakage current due to the suppressed growth of the GeOx interlayer in the wet ambient. This should be attributed to the hydrolysable property of GeOx in water-vapor. (2) Ultra-thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet N2 anneal. The effects of Ti content on the performances of HfTiO gate dielectricd are analysed by using different sputtering powers of the Ti target. Experimental results indicate that as the Ti content increases, theκvalue can increase up to 40 for the highest Ti content being studied in this paper. However, while the Ti content is too high, the interface properties and gate leakage properties are deteriorated severely. To inspect the influences of PDA on MOS capacitors, PDA was comparatively carried out in wet N2, NH3, NO and N2O ambiences respectively. Results show that excellent dielectric performance is achieved by wet N2 annealing: equivalent oxide thickness of 0.81 nm, relative permittitivy of 35, interface-state density of 6.4×1011 eV-1 cm-2, equivalent oxide charge density of 1.96×1011 cm-2 and gate leakage current of 2.71×10-4 Acm-2 at Vg = 1 V. (3) GeOxNy and GeOxNy /HfTiO stack gate dielectric has been fabricated on Ge substrate with substrate surface pretreatment.
Results indicate that surface pretreatment in wet NO ambient is propitious to fabricate sub-2nm high-κGeOxNy/HfTiO gate stack Ge MOSFETs by decreasing density of interface state and equivalent oxide charge, thus reduces gate leakage current and enhances reliability of device.Excellent device performances of GeOxNy/HfTiO Ge MOS capacitor have been achieved with equivalent oxide thickness of 1.88 nm, equivalent oxide charge density of 9.77×1010 cm-2, interface-state density of 2.41×1011 eV-1 cm-2 and gate leakage current of 4.75×10-5 Acm-2 at Vg = 1 V.
本文通过考虑量子效应,提出了一种深亚微米SiGe沟道pMOSFET阈值电压模型,分别考虑了有Si盖帽层和无Si盖帽层两种情况,并讨论了高κ栅介质、短沟道效应和漏致势垒降低效应对阈值电压的影响。模拟结果和实验数据符合良好。利用此模型对器件的主要参数进行了优化设计。
基于WKB近似,在分析高κ栅介质/界面层/Ge衬底能带结构的基础上,提出综合考虑直接隧穿和F-N隧穿的栅极漏电流解析模型,模拟结果与实验数据符合较好,表明该模型对于模拟深亚微米叠层高κ栅介质Ge MOS器件在强反型时的栅极漏电较为准确,但在小栅偏压下(Vg < 0.3 V)存在一定的误差,可能的原因是没有充分考虑空穴密度和陷阱电荷对栅极漏电的影响。实验方面,研究了Ge MOS器件的制备工艺,在Ge衬底上制备出了性能良好的HfTiON、HfTiO以及叠层GeON/HfTiO等高κ栅介质:(1)采用反应磁控溅射方法在Ge衬底上生长HfTiN薄膜,然后利用淀积后退火(PDA)工艺,在湿N2气氛中,利用退火系统中剩余的O2将HfTiN薄膜转化成HfTiON栅介质,制备了性能良好的Ge MOS器件,等效氧化物厚度为2.4nm,等效氧化物电荷密度2. 8×1011 cm-2,界面态密度5.9×1011 eV-1 cm-2,栅极漏电流密度4.7×10-4 Acm-2 (Vg = 1V)。并研究了干湿N2退火对器件性能的影响。结果显示,由于GeOx的易水解特性,湿N2退火有效抑制了低κGeOx界面层的生长,大大降低了界面态和等效氧化物电荷密度,进而降低了栅极漏电流;(2)利用反应磁控溅射方法在Ge衬底上制备超薄HfTiO栅介质,通过调节Ti靶的溅射功率研究了Ti浓度对HfTiO介质性能的影响。实验结果表明,在所研究范围内,随着Ti浓度的增加,HfTiO的介电常数增加到40,但高浓度的Ti引起界面特性的恶化和栅极漏电流密度的增加。为了进一步研究淀积后退火对器件电特性的影响,PDA分别在500°C的湿N2、NH3、NO、N2O气氛中进行300s。实验结果表明,湿N2退火样品呈现出最优的电性能:等效氧化物厚度0.81nm,相对介电常数~35,界面态密度~6.4×1011 eV-1 cm-2,等效氧化物电荷密度~1.96×1011 cm-2,+1V栅压时的栅极漏电流~2.71×10-4 Acm-2;(3)研究了湿NO、N2O、NH3表面预处理工艺对器件性能的影响。采用表面预处理工艺制备了GeOxNy以及GeOxNy/HfTiO叠层栅介质MOS器件。结果表明,湿NO表面预处理对制备亚2nm GeOxNy/HfTiO叠层高κ栅介质,降低其界面态密度和等效氧化物电荷密度,从而减小栅极漏电、增强器件可靠性有着十分重要的作用,其电参数达到:等效氧化物厚度1.88nm,等效氧化物电荷密度9.77×1010cm-2,界面态密度2.41×1011 cm-2eV-1,栅极漏电流4.95×10-5 Acm-2。
As the continual scaling of complementary metal-oxide-semiconductor (CMOS), Si MOS device approaches its fundamental limits, and new channel materials, such as strained Si, strained SiGe alloy and Ge substrate and so on, are explored to improve device performance by enhancing carrier mobility in the channel region. Recently, study on SiGe or Ge MOSFETs with high-κgate dielectric have become hot point, which mainly be focused on fabrication processes and electrical properties of high-κgate dielectric. However, post-deposition anneal, surface pretreatment of substrate, and Hf-based oxides doped Ti, were less involved. Also, the studies on modeling of Ge MOS devices, e.g. threshold voltage model and gate leakage model, were rarely reported too. In this thesis, theoritical and experiment work related to above problems is performed to find relevant solutions. Content of the thesis is devided into three parts: 1) threshold voltage model on SiGe pMOSFET, 2) gate leakage model on Ge MOS, 3) preparations and electrical properties of high-κgate dielectric MOS devices with Hf- and HfTi-based oxide and oxynitride as gate dielectric.
In this work, analytical models on threshold voltage of deep sub-micron SiGe pMOSFETs with high-κgate-dielectric and Si cap layer or without Si cap layer are respectively proposed by considering short-channel effect (SCE), drain-induced barrier lowing (DIBL) and quantumn effect. The simulated results are in good agreement with experimental data. Based on the model, the main parameters of high-κgate dielectric SiGe pMOSFET can be reasonably determined.
For gate-leakage current model, based on the Wentzel-Kramer-Brillouin (WKB) approach, a compact analytical model of Ge MOS device has been developed by taking direct and F-N tunnels into account. Simulated results exhibit a good agreement with experimental data, indicating that the model is suitable for simulating gate leakage current in inversion for deep-submicron Ge MOSFET with stack high-κgate dielectric. However, small error occurs for low gate bias below 0.3 V, probably due to deficiently calculating effects of hole density and trap charges.
MOS devices fabricating process and electric charactristic with HfTi oxidation and oxynitride gate dielectric is investigated as followed. (1) HfTiN gate dielectric films are deposited on n-Ge substrates by the method of reacting magnetron sputtering in N2+Ar ambient, followed by PDA which was carried out at 550°C for 300s in a wet N2 ambient instead of O2 to convert HfTiN into HfTiON by utilizing the residual O2 in PDA system, and super performace for Ge MOS capacitor with HfTiON gate dielectric have been achieved with equivalent oxide thickness of 2.4 nm, equivalent oxide charge density of 2.8×1011 cm-2, interface-state density of 5.9×1011 eV-1 cm-2 and gate leakage current of 4.7×10-4 A cm2 at Vg = 1 V. The effects of dry and wet N2 anneal on dielectrice perporities have been investigated too, results indicate that wet N2 anneal for deposited HfTiN film can induce a great reduction of interface-state/dielectric-charge densities and gate leakage current due to the suppressed growth of the GeOx interlayer in the wet ambient. This should be attributed to the hydrolysable property of GeOx in water-vapor. (2) Ultra-thin HfTiO gate dielectric is deposited by reactive co-sputtering method followed by wet N2 anneal. The effects of Ti content on the performances of HfTiO gate dielectricd are analysed by using different sputtering powers of the Ti target. Experimental results indicate that as the Ti content increases, theκvalue can increase up to 40 for the highest Ti content being studied in this paper. However, while the Ti content is too high, the interface properties and gate leakage properties are deteriorated severely. To inspect the influences of PDA on MOS capacitors, PDA was comparatively carried out in wet N2, NH3, NO and N2O ambiences respectively. Results show that excellent dielectric performance is achieved by wet N2 annealing: equivalent oxide thickness of 0.81 nm, relative permittitivy of 35, interface-state density of 6.4×1011 eV-1 cm-2, equivalent oxide charge density of 1.96×1011 cm-2 and gate leakage current of 2.71×10-4 Acm-2 at Vg = 1 V. (3) GeOxNy and GeOxNy /HfTiO stack gate dielectric has been fabricated on Ge substrate with substrate surface pretreatment.
Results indicate that surface pretreatment in wet NO ambient is propitious to fabricate sub-2nm high-κGeOxNy/HfTiO gate stack Ge MOSFETs by decreasing density of interface state and equivalent oxide charge, thus reduces gate leakage current and enhances reliability of device.Excellent device performances of GeOxNy/HfTiO Ge MOS capacitor have been achieved with equivalent oxide thickness of 1.88 nm, equivalent oxide charge density of 9.77×1010 cm-2, interface-state density of 2.41×1011 eV-1 cm-2 and gate leakage current of 4.75×10-5 Acm-2 at Vg = 1 V.
引文
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