MCS-51单片机芯片反向解剖以及正向设计的研究
摘要
在过去的几十年中，电子工业飞速发展。集成电路制造工艺已经通过了深亚微米极限，使得IC设计者可以在单个芯片上集成上千万个晶体管，集成电路进入了片上系统(SOC)王国。IP核的设计也就越来越受到理论界和工业界的关注，而MCS—51单片机芯片应用非常广泛，同时掌握MCU设计技术也非常重要。因此，本论文对MCS—51单片机芯片进行了反向解剖和正向设计的研究。
本论文的目的是设计MCS—51单片机芯片，主要工作和取得的成果如下：
①对MCS—51单片机进行分析研究，包括MCS—51单片机工作原理、指令系统、时序分析、特征提取等。并在此基础上完成反向解剖和正向设计MCS—51芯片。
②对MCS—5l单片机进行反向解剖，根据解剖芯片的照片提取电路图，并利用L-Edit完成版图设计。版图设计过程中要进行设计规则检查、电气规则检查等。完成逻辑图划分、整理功能块以及版图与逻辑图一致性验证后，进行硬核仿真，以便于确保芯片功能完全正确。
③对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。在设计的不同阶段分别使用了Cadence、Modelsim、Synplify6.0、MaxplusⅡ10.0等EDA工具。同时基于MCS-51单片机的反向解剖讨论了优化正向设计，减少综合后门数的设计方法。
总之，通过反向解剖和正向设计，我们得到一个即将投入市场的MCS—51单片机芯片，初步实现一个可以重复使用的硬核和软核模块。
The worldwide electronics industry is rapidly moving forward over the past decades. As silicon technology has crossed the deep-submicron threshold,we can design tens of millions of transistors on a single chip. That is to say semiconductor has entered into the realm of "System on a Chip (SoC)" . The research on the technology of IP core design is concerned by both research society and industry world. Because of the wide use of MCS-51 Microcontroller and the important meaning of MCU core design,we study on MCS-51 reverse anatomization and Top-Down Design
The goal of this article is to design a MCS-51 Microcontroller chip. The Main work and achievements are as followS
MCS-51 Microcontroller is studied. The result of the research is included MCS-51 Microcontroller work princip instruction system timing analysis feature picking up;etc
MCS-51 Microcontroller chip has been anatomized. Based on the chip' s photo,we get the whole schematics and finished the layout design. During the layout design,using L-Edit tools,DRC and ERC have been done. The design of the chip is totally accomplished by detail simulation.
The design of MCS-51 Microcontroller is followed the Top-Down design way,including system partition coding (VHDL) RTL simulation synthesis,gate level simulation ect. Different EDA tools are used in different phase,such as Cadem Modelsirru Synplify 6.0 Maxplus II 10.0 and so on. The technology of optimization design based on MCS-51 Microcontroller reserve anatomization is also discussed.
In a word,the chip will be sold openly in the market soon. The reuse hardware core and software core are primarily succeeded.
本论文的目的是设计MCS—51单片机芯片，主要工作和取得的成果如下：
①对MCS—51单片机进行分析研究，包括MCS—51单片机工作原理、指令系统、时序分析、特征提取等。并在此基础上完成反向解剖和正向设计MCS—51芯片。
②对MCS—5l单片机进行反向解剖，根据解剖芯片的照片提取电路图，并利用L-Edit完成版图设计。版图设计过程中要进行设计规则检查、电气规则检查等。完成逻辑图划分、整理功能块以及版图与逻辑图一致性验证后，进行硬核仿真，以便于确保芯片功能完全正确。
③对MCS—51单片机进行正向设计，包括系统划分、编写代码、RTL级仿真与综合、门级仿真等。在设计的不同阶段分别使用了Cadence、Modelsim、Synplify6.0、MaxplusⅡ10.0等EDA工具。同时基于MCS-51单片机的反向解剖讨论了优化正向设计，减少综合后门数的设计方法。
总之，通过反向解剖和正向设计，我们得到一个即将投入市场的MCS—51单片机芯片，初步实现一个可以重复使用的硬核和软核模块。
The worldwide electronics industry is rapidly moving forward over the past decades. As silicon technology has crossed the deep-submicron threshold,we can design tens of millions of transistors on a single chip. That is to say semiconductor has entered into the realm of "System on a Chip (SoC)" . The research on the technology of IP core design is concerned by both research society and industry world. Because of the wide use of MCS-51 Microcontroller and the important meaning of MCU core design,we study on MCS-51 reverse anatomization and Top-Down Design
The goal of this article is to design a MCS-51 Microcontroller chip. The Main work and achievements are as followS
MCS-51 Microcontroller is studied. The result of the research is included MCS-51 Microcontroller work princip instruction system timing analysis feature picking up;etc
MCS-51 Microcontroller chip has been anatomized. Based on the chip' s photo,we get the whole schematics and finished the layout design. During the layout design,using L-Edit tools,DRC and ERC have been done. The design of the chip is totally accomplished by detail simulation.
The design of MCS-51 Microcontroller is followed the Top-Down design way,including system partition coding (VHDL) RTL simulation synthesis,gate level simulation ect. Different EDA tools are used in different phase,such as Cadem Modelsirru Synplify 6.0 Maxplus II 10.0 and so on. The technology of optimization design based on MCS-51 Microcontroller reserve anatomization is also discussed.
In a word,the chip will be sold openly in the market soon. The reuse hardware core and software core are primarily succeeded.
引文
[1] 王阳元，二十一世纪硅微电子技术发展的主要趋势和方向，http://www.ctilz.com.cn，2001年4月
[2] Bob Schallar. The Origin, Nature and Implications of "Moore's Law", http://www.advtech.microsoft.com/research/barc/gray/moore.law.html,1996
[3] IEEE Design Automation Standard Committee, IEEE Standard Hardware Description Language based on Verilog Hardware Description Language, IEEE 1996
[4] ModelSim EE/PLUS Reference Manual, Version 5.4 Model Technology Incorporated
[5] Synplicity Synthesis Reference Manual. Version 6.0, Synplicity Inc.May 2000
[6] 宋万杰、罗丰、吴顺君编著，CPLD技术及其应用，西安电子科技大学出版社，1999年9月
[7] Michael John Sebastian Smith, Application-Specific Integrated Circuits, May 2000
[8] Michael Payer, Approach to System-on-Chip Design VSIA Member Meeting, August 2000
[9] 魏少军，系统集成芯片及其设计方法学，2000年全国“百千万人才工程”微电子光电子技术高级研讨班论文集，2000年11月
[10] 胡永华，深亚微米理论及IP核设计技术的研究，博士学位论文
[11] 王志华、邓仰东，数字集成系统的结构化设计与高层次综合，清华大学出版社，2000
[12] 慈艳柯、陈秀英、吴孙桃、郭东辉，片上系统的设计技术及其研究进展，半导体技术，2001：7(12～16)
[13] 侯伯亨、顾新编著，VHDL硬件描述语言与数字逻辑电路设计，西安电子科技大学出版社，1999
[14] 魏少军，21世纪的电信发展对集成电路技术的要求，半导体情报，2001：1(8～11)，第38卷
[15] 何立民编著，MCS-51系列单片机应用系统设计系统配置与接口技术，北京航空航天大学出版社，1993
[16] Intel,MCS(?)51 MicroController Family User's Manual,Order No:272383-002,February 1994
[17] 孙涵芳、徐爱卿编著，MCS-51／96系列单片机原理及应用，北京航空航天大学出版社，1994
[18] 陈剑、洪一，IC设计流程与技术实现，中国集成电路，2002：4(56～61)
[19] P．E．艾伦、D．R．霍尔伯格，CMOS模拟电路设计，科学出版社，1995
[20] 张建入，MOS集成电路分析与设计基础，电子工业出版社，1994
[21] 张延庆、张开华、朱兆宗，半导体集成电路，上海科学技术出版社，1986
[22] Jan M.Rabaey，数字集成电路设计透视，清华大学出版社，1999
[23] 吴孙桃、慈艳柯、郭东辉，CMOS的异或电路设计与应用，半导体技术，2002：7
[24] 洪先龙、刘伟平、边计年等，超大规模集成电路计算机辅助设计技术，国防工业出版社，1998
[25] 李玉山、来新泉、许东来等，电子系统及专用集成电路CAD技术，西安电子科技大学出版社，1997
[26] 0.6μm技术布局设计规则，无锡华晶上华半导体有限公司(Wuxi CSMC-HJ Co.Ltd.)，2000
[27] S.Olcoz, A.Castellvi、M.Garcia, Improving VHDL Soft-cores with Software-like Reviews and Audits Procedures, Santa Clara, CA (VIUF'98), March 1998 (143-146)
[28] IEEE, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, Copyright (?)2000 IEEE. All rights reserved.
[29] 朱正涌编著，半导体集成电路，清华大学出版社，2001
[30] IEEE Inc. 1076-93 IEEE Standard VHDL Language Reference Manual, New York, N.Y., USA.,September 1993.
[31] S.Meiyappan、K.Jaramillo、P.Chambers, VHDL Coding Styles for Reusable, Synthesizable Designs, SNUG'99, Boston, Oct.7-8 1999
[32] 钟旭恒、高明伦，基于数据通道流程图的硬布线控制设计，微电子与计算机，2001：5
[33] Z.Navabi, VHDL: Analysis and Modeling of Digital Systems,McGraw-Hill, 1993
[34] 吴玉平译，MCS-51微控制器系列用户指南，电子工业出版社，1995
[35] Mentor, ModelSim SE PLUS 5.5d Reference Manual. Revision: 2001.09, Model Technology Incorporated, 2001
[36] 朱明程编著，现场可编程门阵列FPGA原来及应用设计，电子工业出版社，1994
[37] Farzad Nekoogar, Timing Verification of Application Specific Integrated Circuits (ASICs), Prentice Hall, September 1999
[38] 阎石主编，数字电子技术基础(第三版)，高等教育出版社，1994
[39] Ian Phillips, Changing Company Culture from 'Design for One Chip' to 'Design for Reuse' VLSI Members Meeting, April 1999
[40] Seongmo Park, Seongmin Kim、lgkyun Kim、Kyungjin Byun、Jin Jong Cha and Hanjin Cho, A Single-Chip Video/Audio CODEC for Low Bit Rate Application, ETRI Journal, March 2000, Volume 22, Number 1 (20-29)
[2] Bob Schallar. The Origin, Nature and Implications of "Moore's Law", http://www.advtech.microsoft.com/research/barc/gray/moore.law.html,1996
[3] IEEE Design Automation Standard Committee, IEEE Standard Hardware Description Language based on Verilog Hardware Description Language, IEEE 1996
[4] ModelSim EE/PLUS Reference Manual, Version 5.4 Model Technology Incorporated
[5] Synplicity Synthesis Reference Manual. Version 6.0, Synplicity Inc.May 2000
[6] 宋万杰、罗丰、吴顺君编著，CPLD技术及其应用，西安电子科技大学出版社，1999年9月
[7] Michael John Sebastian Smith, Application-Specific Integrated Circuits, May 2000
[8] Michael Payer, Approach to System-on-Chip Design VSIA Member Meeting, August 2000
[9] 魏少军，系统集成芯片及其设计方法学，2000年全国“百千万人才工程”微电子光电子技术高级研讨班论文集，2000年11月
[10] 胡永华，深亚微米理论及IP核设计技术的研究，博士学位论文
[11] 王志华、邓仰东，数字集成系统的结构化设计与高层次综合，清华大学出版社，2000
[12] 慈艳柯、陈秀英、吴孙桃、郭东辉，片上系统的设计技术及其研究进展，半导体技术，2001：7(12～16)
[13] 侯伯亨、顾新编著，VHDL硬件描述语言与数字逻辑电路设计，西安电子科技大学出版社，1999
[14] 魏少军，21世纪的电信发展对集成电路技术的要求，半导体情报，2001：1(8～11)，第38卷
[15] 何立民编著，MCS-51系列单片机应用系统设计系统配置与接口技术，北京航空航天大学出版社，1993
[16] Intel,MCS(?)51 MicroController Family User's Manual,Order No:272383-002,February 1994
[17] 孙涵芳、徐爱卿编著，MCS-51／96系列单片机原理及应用，北京航空航天大学出版社，1994
[18] 陈剑、洪一，IC设计流程与技术实现，中国集成电路，2002：4(56～61)
[19] P．E．艾伦、D．R．霍尔伯格，CMOS模拟电路设计，科学出版社，1995
[20] 张建入，MOS集成电路分析与设计基础，电子工业出版社，1994
[21] 张延庆、张开华、朱兆宗，半导体集成电路，上海科学技术出版社，1986
[22] Jan M.Rabaey，数字集成电路设计透视，清华大学出版社，1999
[23] 吴孙桃、慈艳柯、郭东辉，CMOS的异或电路设计与应用，半导体技术，2002：7
[24] 洪先龙、刘伟平、边计年等，超大规模集成电路计算机辅助设计技术，国防工业出版社，1998
[25] 李玉山、来新泉、许东来等，电子系统及专用集成电路CAD技术，西安电子科技大学出版社，1997
[26] 0.6μm技术布局设计规则，无锡华晶上华半导体有限公司(Wuxi CSMC-HJ Co.Ltd.)，2000
[27] S.Olcoz, A.Castellvi、M.Garcia, Improving VHDL Soft-cores with Software-like Reviews and Audits Procedures, Santa Clara, CA (VIUF'98), March 1998 (143-146)
[28] IEEE, IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis, Copyright (?)2000 IEEE. All rights reserved.
[29] 朱正涌编著，半导体集成电路，清华大学出版社，2001
[30] IEEE Inc. 1076-93 IEEE Standard VHDL Language Reference Manual, New York, N.Y., USA.,September 1993.
[31] S.Meiyappan、K.Jaramillo、P.Chambers, VHDL Coding Styles for Reusable, Synthesizable Designs, SNUG'99, Boston, Oct.7-8 1999
[32] 钟旭恒、高明伦，基于数据通道流程图的硬布线控制设计，微电子与计算机，2001：5
[33] Z.Navabi, VHDL: Analysis and Modeling of Digital Systems,McGraw-Hill, 1993
[34] 吴玉平译，MCS-51微控制器系列用户指南，电子工业出版社，1995
[35] Mentor, ModelSim SE PLUS 5.5d Reference Manual. Revision: 2001.09, Model Technology Incorporated, 2001
[36] 朱明程编著，现场可编程门阵列FPGA原来及应用设计，电子工业出版社，1994
[37] Farzad Nekoogar, Timing Verification of Application Specific Integrated Circuits (ASICs), Prentice Hall, September 1999
[38] 阎石主编，数字电子技术基础(第三版)，高等教育出版社，1994
[39] Ian Phillips, Changing Company Culture from 'Design for One Chip' to 'Design for Reuse' VLSI Members Meeting, April 1999
[40] Seongmo Park, Seongmin Kim、lgkyun Kim、Kyungjin Byun、Jin Jong Cha and Hanjin Cho, A Single-Chip Video/Audio CODEC for Low Bit Rate Application, ETRI Journal, March 2000, Volume 22, Number 1 (20-29)