片内互连频变电磁参数（R和L）提取及软件的制作
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摘要
互连封装结构的电特性对当前高速电路系统的总体性能具有
至关重要的作用。本论文主要针对高速集成电路片内互连的结构
进行了电磁参数的提取，并在此基础上开发了一个用于片内互连
频变电磁参数（R和L）提取的软件。该软件界面简洁友好，功
能强大，易于操作，适于工程应用。
本文的工作主要如下：第二章介绍了电磁参数提取方法，第
三章介绍了软件的设计及使用方法，第四章介绍了一些软件应用
实例，并将结果与文献或其它软件的结果进行了比较。
The electric properties of interconnects and packaging are very
important for the performance of high-speed integrated circuits. This
thesis is oriented for the electronic modeling and parameters
extraction of on-chip interconnects. A software is developed for the
extraction of the frequency-dependent parameters R and L under such
circumstance. It抯 user-friendly, powerful and easy for engineering
application.
The contents are arranged as followings: In chapter two, the method of
electromagnetic parameters extraction is introduced; Chapter three
illustrates how the software was designed and how to use it; In
chapter four, results for various interconnects are compared with those
given in the literatures or by other softwares.
至关重要的作用。本论文主要针对高速集成电路片内互连的结构
进行了电磁参数的提取，并在此基础上开发了一个用于片内互连
频变电磁参数（R和L）提取的软件。该软件界面简洁友好，功
能强大，易于操作，适于工程应用。
本文的工作主要如下：第二章介绍了电磁参数提取方法，第
三章介绍了软件的设计及使用方法，第四章介绍了一些软件应用
实例，并将结果与文献或其它软件的结果进行了比较。
The electric properties of interconnects and packaging are very
important for the performance of high-speed integrated circuits. This
thesis is oriented for the electronic modeling and parameters
extraction of on-chip interconnects. A software is developed for the
extraction of the frequency-dependent parameters R and L under such
circumstance. It抯 user-friendly, powerful and easy for engineering
application.
The contents are arranged as followings: In chapter two, the method of
electromagnetic parameters extraction is introduced; Chapter three
illustrates how the software was designed and how to use it; In
chapter four, results for various interconnects are compared with those
given in the literatures or by other softwares.
引文
1． A. Deutsch, "Electrical characteristic of interconnections for high-performance systems," Procedings of the IEEE, vol. 86, no.2, pp.315-355, February 1998．
2． X. W. Lin and D. Pramanik, "Future interconnect technologies and copper metallization," Solid State Technology, vol.41, no.10, pp.63-79, Oct. 1998．
3． K. Lee, "On-chip interconnects-gigahertz and beyond,". Solid State Technology, vol.41, no.9, pp.85-89, Sept. 1998．
4． R. J. Gutmann, T. P. Chow and A. E. Kasoyeros, etc., "Thermal stability of on-chip copper interconnect structures," Thin Solid Films, vol.262, no.1-2, pp.177-178, 1995．
5． A. Deutsch, G. V. Kopcsay and P. J. Restle, etc., "When are transmission-line effects important for on-chip interconnections," IEEE Trans. Microwave Theory Tech., vol.45, no.10, pp.1836-1846, Oct., 1997．
6． A. Deutsch, G. V. Kopcsay and C. W. Surovic, etc., "Modeling and characterization of long on-chip interconnections for high performance microprocessors," IBMJ. Res. Develop., vol.39, no.5, pp.547-567, 1995．
7． C. K. Cheng, J. Lillis, S. Lin, and N. H. Chang, Interconnect Analysis and Synthesis. New York: Wiley, 2000, ch.5．
8． W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, "Resistive and inductive skin effect in rectangular conductors," IBM J. Res. Develop., vol.23, no.6, pp.652-660, November 1979．
9． L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An efficient inductance modeling for on-chip interconnects," IEEE 1999 Custom Integrated Circuits Conferrence, pp.457-460．
10． M. J. Tsuk, and J. A. Kong," A hybrid method for the caculation of the resistance and inductance of transmission lines with arbitrary cross sections," IEEE Transctions Microwave Theory and Techniques, vol.39, no.8, pp.1338-1347, August 1991．
11． B. Krauter and S. Mehrotra, "Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis," IEEE 1998 PROC DES AUTOM CONF, pp.303-308．
12． P. Restle, A. Ruehli and S. G. Walker, "Dealing with inductance in high-speed chip design,"IEEE 1999 PROC DES AUTOM CONF. pp.904-909．
13． M. Lee, A. Hill and M. H. Darley, "Interconnect inductance effects on delay
and crosstalks for long on-chip nets with fast slew rates." Procedings of the IEEE Circuits and Systems Conference, pp.II-248-II-251, May 31-June 3． 1998．
14． K. Yip, "Clock tree distribution," IEEE Potentials, vol.16, no.2． pp.11-14, 1997．
15． D. J. Restle, K. A. Jenkins and A. Deutsch. etc., "Measurement and modeling of on-chip transmission line effects in a 400MHz microprocessor," IEEE. J. of Solid-state Circuits, vol.33, no.4． pp.662-665． Apr. 1998．
16． H. Krishnanurthy, M. B. Maaz and M.A.Bayoumi, "A new partitioning framework for uniform clock distribution during high-level synthesis," Proceedings-IEEE International Symposium on Circuits and Systems, vol.6, pp.381-384, Apr. 1998．
17． Y. Massoud, S. Majors, T. Bustami, and J. White, "Layout techniques for minimizing on-chip interconnect self inductance," PROC DES AUTOM CONF, IEEE, pp.566-571． 1998．
18． K. L. Shepard and V. Narayanan, "Noise in deep design," IEEE ACM INT CONF AIDED DES DIG TECH PAP, pp.524-531, 1996．
19． 李炳宗，“深亚微米超大规模集成电路多层互连技术新进展”，《上海微电 子技术和应用》，no．4． pp．2-9． 1997
20． 翁寿松，“深亚微米半导体器件制备的最新工艺及设备”，《半导体杂 志》，vol．22． no．4，pp．27-33，1997
21． 袁寿财，朱长纯，“集成电路技术：过去与未来”，《半导体杂志》，vol．23． no．2． pp．19-33． 1998
22． M. Lee, "A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation," IEEE J. Solid-State Circuits, vol.33, no.4, pp.657-661, Apr., 1998．
23． M. Celik, A.C Cangellaris and A. Deutsch, "New moment technique for interconnects characterized by measured or calculated s-parameters," IEEE Multipchip Module Conference, pp. 196-201, 1996．
24． V. Veremey and R. Mittra, "A technique for fast calculation for fast calcultion of capacitance matrics of interconnect structure," IEEE Trans. Components, Packging and Manufacturing Technology-Part B, vol.21, no.3, pp.241-249, Aug, 1998．
25． A. Deutsch, G. V. Kopcsay and C. W. Surovic, etc., "Challenges raised by long on chip wiring for CMOS mcroprocessor application," IEEE TOP MEET EKECTR PERFORM ELECTRON PACKAG, pp.303-308, 1998．
26． 王秉中，《计算电磁学》，电子科技大学研究生讲义，2000年
27． G．Perry编著，戴红，陈哲，姚娜译，《学用Visual Basic 6． 0》，清华大学 出版社，1999年
28． 宋伟，吴建国等编著，《中文Visual Basic 6． 0编程基础》，清华大学出版 社，1999年
29． 李兰友，庄国瑜，秦卫光编著，《Visual Basic绘图与图象处理》，人民邮 电出版社，1999年
30． 李怀明，骆原，王育新编著，《Visual Basic 6． 0中文版参考详解》，清华 大学出版社，1999年
31． B．Reselman，R．Peasley，W．Pruchniak著，田金兰，李从蓉，王一川等译， 《Visual Basic 6使用指南》，电子工业出版社，1999年
32． 桂良进，王军，董波等著，《Fortran PowerStation 4． 0使用与编程》，北京 航天大学出版社，1997年
33． 谭浩强，田淑清，《FORTRAN语言》，清华大学出版社，1995年
34． 程卫国，冯峰，姚东，徐听等编著，“MATLAB 5． 3应用指南”，人民邮 电出版社，1999年
35． 施阳，李俊等编著，《MATLAB语言工具箱》，西北工业大学出版社，1998 年
2． X. W. Lin and D. Pramanik, "Future interconnect technologies and copper metallization," Solid State Technology, vol.41, no.10, pp.63-79, Oct. 1998．
3． K. Lee, "On-chip interconnects-gigahertz and beyond,". Solid State Technology, vol.41, no.9, pp.85-89, Sept. 1998．
4． R. J. Gutmann, T. P. Chow and A. E. Kasoyeros, etc., "Thermal stability of on-chip copper interconnect structures," Thin Solid Films, vol.262, no.1-2, pp.177-178, 1995．
5． A. Deutsch, G. V. Kopcsay and P. J. Restle, etc., "When are transmission-line effects important for on-chip interconnections," IEEE Trans. Microwave Theory Tech., vol.45, no.10, pp.1836-1846, Oct., 1997．
6． A. Deutsch, G. V. Kopcsay and C. W. Surovic, etc., "Modeling and characterization of long on-chip interconnections for high performance microprocessors," IBMJ. Res. Develop., vol.39, no.5, pp.547-567, 1995．
7． C. K. Cheng, J. Lillis, S. Lin, and N. H. Chang, Interconnect Analysis and Synthesis. New York: Wiley, 2000, ch.5．
8． W. T. Weeks, L. L. Wu, M. F. McAllister, and A. Singh, "Resistive and inductive skin effect in rectangular conductors," IBM J. Res. Develop., vol.23, no.6, pp.652-660, November 1979．
9． L. He, N. Chang, S. Lin, and O. S. Nakagawa, "An efficient inductance modeling for on-chip interconnects," IEEE 1999 Custom Integrated Circuits Conferrence, pp.457-460．
10． M. J. Tsuk, and J. A. Kong," A hybrid method for the caculation of the resistance and inductance of transmission lines with arbitrary cross sections," IEEE Transctions Microwave Theory and Techniques, vol.39, no.8, pp.1338-1347, August 1991．
11． B. Krauter and S. Mehrotra, "Layout based frequency dependent inductance and resistance extraction for on-chip interconnect timing analysis," IEEE 1998 PROC DES AUTOM CONF, pp.303-308．
12． P. Restle, A. Ruehli and S. G. Walker, "Dealing with inductance in high-speed chip design,"IEEE 1999 PROC DES AUTOM CONF. pp.904-909．
13． M. Lee, A. Hill and M. H. Darley, "Interconnect inductance effects on delay
and crosstalks for long on-chip nets with fast slew rates." Procedings of the IEEE Circuits and Systems Conference, pp.II-248-II-251, May 31-June 3． 1998．
14． K. Yip, "Clock tree distribution," IEEE Potentials, vol.16, no.2． pp.11-14, 1997．
15． D. J. Restle, K. A. Jenkins and A. Deutsch. etc., "Measurement and modeling of on-chip transmission line effects in a 400MHz microprocessor," IEEE. J. of Solid-state Circuits, vol.33, no.4． pp.662-665． Apr. 1998．
16． H. Krishnanurthy, M. B. Maaz and M.A.Bayoumi, "A new partitioning framework for uniform clock distribution during high-level synthesis," Proceedings-IEEE International Symposium on Circuits and Systems, vol.6, pp.381-384, Apr. 1998．
17． Y. Massoud, S. Majors, T. Bustami, and J. White, "Layout techniques for minimizing on-chip interconnect self inductance," PROC DES AUTOM CONF, IEEE, pp.566-571． 1998．
18． K. L. Shepard and V. Narayanan, "Noise in deep design," IEEE ACM INT CONF AIDED DES DIG TECH PAP, pp.524-531, 1996．
19． 李炳宗，“深亚微米超大规模集成电路多层互连技术新进展”，《上海微电 子技术和应用》，no．4． pp．2-9． 1997
20． 翁寿松，“深亚微米半导体器件制备的最新工艺及设备”，《半导体杂 志》，vol．22． no．4，pp．27-33，1997
21． 袁寿财，朱长纯，“集成电路技术：过去与未来”，《半导体杂志》，vol．23． no．2． pp．19-33． 1998
22． M. Lee, "A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation," IEEE J. Solid-State Circuits, vol.33, no.4, pp.657-661, Apr., 1998．
23． M. Celik, A.C Cangellaris and A. Deutsch, "New moment technique for interconnects characterized by measured or calculated s-parameters," IEEE Multipchip Module Conference, pp. 196-201, 1996．
24． V. Veremey and R. Mittra, "A technique for fast calculation for fast calcultion of capacitance matrics of interconnect structure," IEEE Trans. Components, Packging and Manufacturing Technology-Part B, vol.21, no.3, pp.241-249, Aug, 1998．
25． A. Deutsch, G. V. Kopcsay and C. W. Surovic, etc., "Challenges raised by long on chip wiring for CMOS mcroprocessor application," IEEE TOP MEET EKECTR PERFORM ELECTRON PACKAG, pp.303-308, 1998．
26． 王秉中，《计算电磁学》，电子科技大学研究生讲义，2000年
27． G．Perry编著，戴红，陈哲，姚娜译，《学用Visual Basic 6． 0》，清华大学 出版社，1999年
28． 宋伟，吴建国等编著，《中文Visual Basic 6． 0编程基础》，清华大学出版 社，1999年
29． 李兰友，庄国瑜，秦卫光编著，《Visual Basic绘图与图象处理》，人民邮 电出版社，1999年
30． 李怀明，骆原，王育新编著，《Visual Basic 6． 0中文版参考详解》，清华 大学出版社，1999年
31． B．Reselman，R．Peasley，W．Pruchniak著，田金兰，李从蓉，王一川等译， 《Visual Basic 6使用指南》，电子工业出版社，1999年
32． 桂良进，王军，董波等著，《Fortran PowerStation 4． 0使用与编程》，北京 航天大学出版社，1997年
33． 谭浩强，田淑清，《FORTRAN语言》，清华大学出版社，1995年
34． 程卫国，冯峰，姚东，徐听等编著，“MATLAB 5． 3应用指南”，人民邮 电出版社，1999年
35． 施阳，李俊等编著，《MATLAB语言工具箱》，西北工业大学出版社，1998 年