基于FPGA的可重构系统及CAD技术研究
摘要
可重构计算同时具有软件的灵活性和硬件的高性能,是一种新型的计算模式,目前已成为一个研究热点。由于可重构计算的研究仍处于发展阶段,还面临很多问题需要解决,如在可重构应用设计过程中,缺乏便捷、通用的计算机辅助设计工具来将应用设计映射到可重构系统,包括任务划分、映射等。此外,如何缩短系统重构时间,提高可重构系统性能是可重构计算所面临的一个关键问题。本文针对这些问题开展研究,并主要完成了以下工作:
(1)采用Xilinx公司支持二维区域部分可重构的Virtex-4 FPGA,设计了一个可重构系统硬件平台,作为研究面向可重构系统的操作系统和其他应用的硬件基础。本论文详细介绍了该硬件平台的功能结构、配置方法、以及系统的体系结构和系统开发流程。
(2)针对可重构计算中的硬件任务划分问题,提出一种概率构造算法与遗传算法融合的算法,通过引入表示划分结果多样性的度量方法,利用概率构造算法产生具有多样性的较优的初始群体,并在此基础上利用遗传算法寻求最优解。实验表明,该算法在求解质量上高于列表算法;在同等解质量的情况下,比随机产生初始群体的遗传算法运行时间提高一倍以上,并且划分问题规模越大,优势越明显。
(3)基于FPGA的可重构系统的重构时间与配置文件的大小直接相关,为了缩短系统重构时间,从布局的角度提出了一种缩小FPGA配置文件的算法。该算法是针对基于查找表的FPGA,并在VPR布局算法的基础上进行改进。该算法除了考虑减少连线长度和关键路径延时之外,还通过将前一个电路的查找表配置信息引入到布局算法的价格函数中,以尽量减少前后两个电路在FPGA中布局后所对应的查找表配置信息的差异。实验结果表明,当采用差量配置方式对FPGA进行配置时,该算法能缩小整个差量配置文件的长度,从而缩短系统重构时间。
(4)为了缩短基于FPGA的可重构系统重构时间,提出了一种在差量配置模式下缩小FPGA配置文件的布线算法。在经典的FPGA布线算法考虑的主要因素(提高布线资源的利用率和减少关键路径延时)之外,该算法还考虑了前后两个电路在布线资源利用上的相关性,使后一个电路尽量重用前一个电路已使用的布线资源,以减少前后两个电路布线资源配置信息的差异。由于在配置文件中,布线资源的配置信息所占的比例一般要达到70%以上,因此在使用差量配置方式对FPGA进行配置时,就能有效地缩小整个差量配置文件的长度。该算法在VPR算法基础上进行改进,实验结果表明了该算法的有效性。
As a new computing architecture, reconfigurable computing can achieve potentially much higher performance than software, while maintain a higher level of flexibility than hardware, so it has become a hotspot of current computer architecture research field. Because the development of reconfigurable systems is still a maturing field, many problems need to be sloved. One problem is absence of computer-aided design and compilation tools that conveniently map an application to a reconfigurable computing system, including task partition and mapping. Another key problem is how to reduce the reconfiguration time to increase the performance of reconfigurable system. This paper focuses on these problems, and the main works are shown as follow:
Firstly, a reconfigurable system prototype platform is designed by using Xilinx Virtex-4 FPGA. This platform is used as the hardware base to research operating system supporting for reconfigurable computing and other applications. The function of this platform、the configure technique、system architecture and design flow are introduced in details in the paper.
Secondly, a partitioning algorithm is proposed to partition an entire hardware task into interconnected subtasks for reconfigurable computing. The algorithm, called PCGA, syncretizes probabilistic constructive (PC) algorithm and genetic algorithm (GA). A new approach is proposed to measure the variety of partitions, and an initial population with a variety of better individuals is produced by PC algorithm. Then, the optimal solution is captured by GA based on these initial population.The experimental results show that PCGA can get better results of graph partitioning than those list-based partitioning algorithms; for the same solution quality, the PCGA has short execution time and it is discovered that the bigger the size of partitioning problem is, the better the PCGA performs.
Thirdly, the reconfiguration time of FPGA-based reconfigurable systems is directly related to the size of the reconfiguration bitstream. In order to reduce reconfiguration time, a placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm aims at LUT-based FPGAs, and is modified on the existing placement algorithm within VPR. Besides the connection length and the critical path delay, it also introduces the LUTs configuration of the previous circuit into cost function to reduce the difference of LUTs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow, the proposed approach is validated by experiments. The experimental results show that the size of reconfiguration bitstream can be reduced, and consequently, the reconfiguration time is reduced.
Finally, in order to reduce reconfiguration time, a routing algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. Besides considering the factors of effectively using FPGA routing resources and minimizing critical path delay, the algorithm also considers the relation of routing resources used by subsequent circuits. By making the most of routing resources that have been used for the previous circuit, the algorithm reduces the configuration difference of routing resources between subsequent circuits. Because about 70-90% of configuration bitstream relates to routing resources, by using difference-based design flow, the algorithm can effectively reduce the size of reconfiguration bitstream. The algorithm is modified on the existing routing algorithm within VPR, and experimental results show the availability of the algorithm.
(1)采用Xilinx公司支持二维区域部分可重构的Virtex-4 FPGA,设计了一个可重构系统硬件平台,作为研究面向可重构系统的操作系统和其他应用的硬件基础。本论文详细介绍了该硬件平台的功能结构、配置方法、以及系统的体系结构和系统开发流程。
(2)针对可重构计算中的硬件任务划分问题,提出一种概率构造算法与遗传算法融合的算法,通过引入表示划分结果多样性的度量方法,利用概率构造算法产生具有多样性的较优的初始群体,并在此基础上利用遗传算法寻求最优解。实验表明,该算法在求解质量上高于列表算法;在同等解质量的情况下,比随机产生初始群体的遗传算法运行时间提高一倍以上,并且划分问题规模越大,优势越明显。
(3)基于FPGA的可重构系统的重构时间与配置文件的大小直接相关,为了缩短系统重构时间,从布局的角度提出了一种缩小FPGA配置文件的算法。该算法是针对基于查找表的FPGA,并在VPR布局算法的基础上进行改进。该算法除了考虑减少连线长度和关键路径延时之外,还通过将前一个电路的查找表配置信息引入到布局算法的价格函数中,以尽量减少前后两个电路在FPGA中布局后所对应的查找表配置信息的差异。实验结果表明,当采用差量配置方式对FPGA进行配置时,该算法能缩小整个差量配置文件的长度,从而缩短系统重构时间。
(4)为了缩短基于FPGA的可重构系统重构时间,提出了一种在差量配置模式下缩小FPGA配置文件的布线算法。在经典的FPGA布线算法考虑的主要因素(提高布线资源的利用率和减少关键路径延时)之外,该算法还考虑了前后两个电路在布线资源利用上的相关性,使后一个电路尽量重用前一个电路已使用的布线资源,以减少前后两个电路布线资源配置信息的差异。由于在配置文件中,布线资源的配置信息所占的比例一般要达到70%以上,因此在使用差量配置方式对FPGA进行配置时,就能有效地缩小整个差量配置文件的长度。该算法在VPR算法基础上进行改进,实验结果表明了该算法的有效性。
As a new computing architecture, reconfigurable computing can achieve potentially much higher performance than software, while maintain a higher level of flexibility than hardware, so it has become a hotspot of current computer architecture research field. Because the development of reconfigurable systems is still a maturing field, many problems need to be sloved. One problem is absence of computer-aided design and compilation tools that conveniently map an application to a reconfigurable computing system, including task partition and mapping. Another key problem is how to reduce the reconfiguration time to increase the performance of reconfigurable system. This paper focuses on these problems, and the main works are shown as follow:
Firstly, a reconfigurable system prototype platform is designed by using Xilinx Virtex-4 FPGA. This platform is used as the hardware base to research operating system supporting for reconfigurable computing and other applications. The function of this platform、the configure technique、system architecture and design flow are introduced in details in the paper.
Secondly, a partitioning algorithm is proposed to partition an entire hardware task into interconnected subtasks for reconfigurable computing. The algorithm, called PCGA, syncretizes probabilistic constructive (PC) algorithm and genetic algorithm (GA). A new approach is proposed to measure the variety of partitions, and an initial population with a variety of better individuals is produced by PC algorithm. Then, the optimal solution is captured by GA based on these initial population.The experimental results show that PCGA can get better results of graph partitioning than those list-based partitioning algorithms; for the same solution quality, the PCGA has short execution time and it is discovered that the bigger the size of partitioning problem is, the better the PCGA performs.
Thirdly, the reconfiguration time of FPGA-based reconfigurable systems is directly related to the size of the reconfiguration bitstream. In order to reduce reconfiguration time, a placement algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. The algorithm aims at LUT-based FPGAs, and is modified on the existing placement algorithm within VPR. Besides the connection length and the critical path delay, it also introduces the LUTs configuration of the previous circuit into cost function to reduce the difference of LUTs configuration for subsequent circuits at the layout level. By using difference-based partial reconfiguration design flow, the proposed approach is validated by experiments. The experimental results show that the size of reconfiguration bitstream can be reduced, and consequently, the reconfiguration time is reduced.
Finally, in order to reduce reconfiguration time, a routing algorithm is proposed to reduce the size of FPGA reconfiguration bitstream. Besides considering the factors of effectively using FPGA routing resources and minimizing critical path delay, the algorithm also considers the relation of routing resources used by subsequent circuits. By making the most of routing resources that have been used for the previous circuit, the algorithm reduces the configuration difference of routing resources between subsequent circuits. Because about 70-90% of configuration bitstream relates to routing resources, by using difference-based design flow, the algorithm can effectively reduce the size of reconfiguration bitstream. The algorithm is modified on the existing routing algorithm within VPR, and experimental results show the availability of the algorithm.
引文
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