SRAM型FPGA的单粒子效应评估技术研究
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摘要
SRAM型FPGA的单粒子效应是近年来星载电子设备失效的主要原因之一。配置存储器中的单粒子翻转有可能彻底改变电路的结构，导致系统功能持续出错。这种特点使得FPGA中的单粒子效应分析起来更为复杂，如何准确评价器件对单粒子效应的敏感程度以及分析单粒子翻转对用户电路造成的影响就成了一个值得研究的问题。本文针对这一问题开展了以下研究：
(1)根据FPGA的结构特点，提出将其中的单粒子效应分为器件与应用两个层面进行分析。用传统的翻转截面表征器件本身对单粒子效应的敏感程度，用动态翻转截面来预估由FPGA实现的系统在空间中的失效率。并且明确定义了“敏感位”的概念，指出了敏感位与两种翻转截面的数值关系，建立了辐照试验与模拟方法之间的桥梁。
(2)研制了一套通用的FPGA辐射效应测试系统。系统能够对FPGA的配置存储器、块存储器、系统功能、功耗电流等重要辐射敏感参数进行实时监测。利用该系统在北京串列加速器上开展了多次单粒子效应试验，获得了多种器件的单粒子翻转截面曲线，并且针对几个测试电路的动态单粒子特性进行了试验研究。
(3)加速器束流时间有限、价格昂贵，不宜用于整机单粒子效应的考核。本文研究了一种通过主动向FPGA的配置存储器中写入错误以模拟单粒子效应的故障注入方法。这种方法能够对任意一个设计中的敏感位进行精确定位，因此可以用来预估系统的失效率以及验证各种容错方法的有效性。
(4)利用JBits类库对Xilinx典型的Virtex系列FPGA进行了配置文件的反向解码，得到了配置位的偏移地址与其控制的可编程资源之间的对应关系。这种对应关系从底层揭示了单粒子翻转在用户电路中造成的失效模式，为FPGA单粒子失效分析程序的开发奠定了基础。
(5)提出了一种全新的FPGA单粒子软错误分析方法。这种方法利用面向对象方式对真实的器件结构进行建模，解决了单粒子翻转在系统中传递的问题。论文工作中开发的原型程序能够读入电路设计的网表文件，解析用到的可编程资源，并且根据这些资源的失效模式以及冗余情况确定可能影响该电路拓扑结构的敏感逻辑和路径，最后从解码的数据库中找出这些结构对应的配置位。这样不仅可以得到该设计的敏感位，而且从微观上阐明了系统失效的根本原因。
Single-Event Upset in SRAM-based FPGAs is an important threat for spaceelectronic systems. The upsets in FPGA’s configuration memory may alter circuitstructures and lead to persistent functional error. This phenomenon is much morecomplicated than upsets in traditional memory devices. How to evaluate this kind ofeffect has become a major concern. The contributions of this paper include:
(1) A two-layer model is proposed. The static upset cross section of physical layeris adopted to describe the sensitivity of different device series, and the dynamic crosssection of application layer is used for predicting the system failure rate on certain orbits.The concept of sensitive bits is defined to build a connection between the two crosssections, as well as the results of irradiation test and simulation methods.
(2) The hardware and software platform is developed for testing radiation effectsin SRAM-based FPGAs. The internal memory upsets, circuit function and powercurrent can be monitored during the irradiation test. Accelerator experiment has beendone on HI-13. The static cross sections for several device series were measured and thedynamic Single-Event behaviors for some benchmark circuits were also studied.
(3) Due to the limitation of beam time and expense, it is not wise to assess thereliability for systems implemented on SRAM-based FPGAs using accelerators. A faultinjection system is established to simulate SEUs in FPGA’s configuration memory. Thismethod is able to find all the sensitive bits in a certain design. Therefore, it can be usedto predict the dynamic cross section and verify the effectiveness of redundant strategies.
(4) JBits SDK is adopted to decode the bitstream of Xilinx Virtex FPGA series.The decoded results find the relationship between programmable structures andaddresses in the bitstream. It also identifies different failure modes induced by SEUs,which constitutes the basis of soft error analysis tool in the following sections.
(5) A soft error analysis tool is proposed. The structures inside an FPGA aremodeled using Objective-Oriented way. The programs read in the netlist of circuitdesigns to get the configured resources and their logic states, and search for all thecritical nodes and routings which might destroy the circuit structure. The sensitive bitscan be queried from the database containing the decoded results.
(1)根据FPGA的结构特点，提出将其中的单粒子效应分为器件与应用两个层面进行分析。用传统的翻转截面表征器件本身对单粒子效应的敏感程度，用动态翻转截面来预估由FPGA实现的系统在空间中的失效率。并且明确定义了“敏感位”的概念，指出了敏感位与两种翻转截面的数值关系，建立了辐照试验与模拟方法之间的桥梁。
(2)研制了一套通用的FPGA辐射效应测试系统。系统能够对FPGA的配置存储器、块存储器、系统功能、功耗电流等重要辐射敏感参数进行实时监测。利用该系统在北京串列加速器上开展了多次单粒子效应试验，获得了多种器件的单粒子翻转截面曲线，并且针对几个测试电路的动态单粒子特性进行了试验研究。
(3)加速器束流时间有限、价格昂贵，不宜用于整机单粒子效应的考核。本文研究了一种通过主动向FPGA的配置存储器中写入错误以模拟单粒子效应的故障注入方法。这种方法能够对任意一个设计中的敏感位进行精确定位，因此可以用来预估系统的失效率以及验证各种容错方法的有效性。
(4)利用JBits类库对Xilinx典型的Virtex系列FPGA进行了配置文件的反向解码，得到了配置位的偏移地址与其控制的可编程资源之间的对应关系。这种对应关系从底层揭示了单粒子翻转在用户电路中造成的失效模式，为FPGA单粒子失效分析程序的开发奠定了基础。
(5)提出了一种全新的FPGA单粒子软错误分析方法。这种方法利用面向对象方式对真实的器件结构进行建模，解决了单粒子翻转在系统中传递的问题。论文工作中开发的原型程序能够读入电路设计的网表文件，解析用到的可编程资源，并且根据这些资源的失效模式以及冗余情况确定可能影响该电路拓扑结构的敏感逻辑和路径，最后从解码的数据库中找出这些结构对应的配置位。这样不仅可以得到该设计的敏感位，而且从微观上阐明了系统失效的根本原因。
Single-Event Upset in SRAM-based FPGAs is an important threat for spaceelectronic systems. The upsets in FPGA’s configuration memory may alter circuitstructures and lead to persistent functional error. This phenomenon is much morecomplicated than upsets in traditional memory devices. How to evaluate this kind ofeffect has become a major concern. The contributions of this paper include:
(1) A two-layer model is proposed. The static upset cross section of physical layeris adopted to describe the sensitivity of different device series, and the dynamic crosssection of application layer is used for predicting the system failure rate on certain orbits.The concept of sensitive bits is defined to build a connection between the two crosssections, as well as the results of irradiation test and simulation methods.
(2) The hardware and software platform is developed for testing radiation effectsin SRAM-based FPGAs. The internal memory upsets, circuit function and powercurrent can be monitored during the irradiation test. Accelerator experiment has beendone on HI-13. The static cross sections for several device series were measured and thedynamic Single-Event behaviors for some benchmark circuits were also studied.
(3) Due to the limitation of beam time and expense, it is not wise to assess thereliability for systems implemented on SRAM-based FPGAs using accelerators. A faultinjection system is established to simulate SEUs in FPGA’s configuration memory. Thismethod is able to find all the sensitive bits in a certain design. Therefore, it can be usedto predict the dynamic cross section and verify the effectiveness of redundant strategies.
(4) JBits SDK is adopted to decode the bitstream of Xilinx Virtex FPGA series.The decoded results find the relationship between programmable structures andaddresses in the bitstream. It also identifies different failure modes induced by SEUs,which constitutes the basis of soft error analysis tool in the following sections.
(5) A soft error analysis tool is proposed. The structures inside an FPGA aremodeled using Objective-Oriented way. The programs read in the netlist of circuitdesigns to get the configured resources and their logic states, and search for all thecritical nodes and routings which might destroy the circuit structure. The sensitive bitscan be queried from the database containing the decoded results.
引文
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