移动数字电视接收前端芯片的数字控制电路设计
摘要
移动数字电视接收前端芯片是移动数字电视终端的重要组成部分,它负责将接收到的移动数字电视信号从射频频段搬移到基带频段,以供基带解调芯片进行相应的处理。为了实现对移动数字电视接收前端芯片工作状态的控制,芯片内置数字控制电路模块。
针对移动数字电视接收前端芯片的需要,描述了芯片当中数字控制电路模块的总体架构,分配了寄存器组当中的控制寄存器,然后给出了I2C总线接口电路模块和寄存器组电路模块的设计方法。借助EDA工具,实现了对数字控制电路模块从数字前端设计到数字后端设计的ASIC全流程设计,并对设计进行了逻辑功能验证、FPGA验证、综合后时序仿真、版图后时序仿真以及晶体管级仿真。最后通过联合仿真对数字控制电路模块进行仿真验证。
电路设计采用TSMC 0.13μm CMOS工艺,设计电压为1.2V。布局布线后得到较为理想的版图面积。整个数字控制电路模块的最终版图面积为17360μm2。晶体管级仿真结果显示平均功耗为382.44μW,功耗满足设计要求。
验证与仿真的结果均表明,所设计的I2C接口电路模块符合I2C总线2.1规范并正常工作在I2C总线上。所设计的寄存器组模块能够通过I2C接口电路正确接收和发送数据。所设计的数字控制电路完全可以实现移动数字电视接收前端芯片的数字控制功能。
Mobile digital TV receiver front-end chip is an important part of the mobile digital TV terminal, which is responsible for receiving mobile digital television signals to the baseband demodulator chip for the treatment accordingly from RF to baseband frequency band. In order to control working states of the mobile digital TV receiver front-end chip, the chip built-in digital control circuit module.
For the requirements of mobile digital TV receiver Front-end chip, this paper presented the chip's overall digital control circuit module architecture and control registers allocation, then the design methods of I2C bus interface circuit module and the register circuit module. In accordance with the ASIC design flow, the digital control circuit module from the digital front-end design to the digital back-end design were realized with EDA tools. Logic verification, FPGA verification, timing simulation after synthesis, post-layout timing simulation and transistor-level simulation have also been done well. Finally, digital control circuit module is verified through co-simulation.
Using TSMC 0.13μm CMOS technology and 1.2V design voltage, ideal layout area has been gained after placement and routing. The area of ultimate digital control circuit block layout is 17360μm2. Transistor level simulation results show that average power consumption is 382.44μW and the total power consumption met to the design requirements.
Validation and simulation results show that the design of the I2C interface circuit module is suitable for I2C-bus specification 2.1 and working well on the I2C bus. The design of registers module can send and receive data correctly through the I2C interface circuit module. The design of digital control circuit can achieve the function of digital control of mobile digital TV front-end receiver chip.
针对移动数字电视接收前端芯片的需要,描述了芯片当中数字控制电路模块的总体架构,分配了寄存器组当中的控制寄存器,然后给出了I2C总线接口电路模块和寄存器组电路模块的设计方法。借助EDA工具,实现了对数字控制电路模块从数字前端设计到数字后端设计的ASIC全流程设计,并对设计进行了逻辑功能验证、FPGA验证、综合后时序仿真、版图后时序仿真以及晶体管级仿真。最后通过联合仿真对数字控制电路模块进行仿真验证。
电路设计采用TSMC 0.13μm CMOS工艺,设计电压为1.2V。布局布线后得到较为理想的版图面积。整个数字控制电路模块的最终版图面积为17360μm2。晶体管级仿真结果显示平均功耗为382.44μW,功耗满足设计要求。
验证与仿真的结果均表明,所设计的I2C接口电路模块符合I2C总线2.1规范并正常工作在I2C总线上。所设计的寄存器组模块能够通过I2C接口电路正确接收和发送数据。所设计的数字控制电路完全可以实现移动数字电视接收前端芯片的数字控制功能。
Mobile digital TV receiver front-end chip is an important part of the mobile digital TV terminal, which is responsible for receiving mobile digital television signals to the baseband demodulator chip for the treatment accordingly from RF to baseband frequency band. In order to control working states of the mobile digital TV receiver front-end chip, the chip built-in digital control circuit module.
For the requirements of mobile digital TV receiver Front-end chip, this paper presented the chip's overall digital control circuit module architecture and control registers allocation, then the design methods of I2C bus interface circuit module and the register circuit module. In accordance with the ASIC design flow, the digital control circuit module from the digital front-end design to the digital back-end design were realized with EDA tools. Logic verification, FPGA verification, timing simulation after synthesis, post-layout timing simulation and transistor-level simulation have also been done well. Finally, digital control circuit module is verified through co-simulation.
Using TSMC 0.13μm CMOS technology and 1.2V design voltage, ideal layout area has been gained after placement and routing. The area of ultimate digital control circuit block layout is 17360μm2. Transistor level simulation results show that average power consumption is 382.44μW and the total power consumption met to the design requirements.
Validation and simulation results show that the design of the I2C interface circuit module is suitable for I2C-bus specification 2.1 and working well on the I2C bus. The design of registers module can send and receive data correctly through the I2C interface circuit module. The design of digital control circuit can achieve the function of digital control of mobile digital TV front-end receiver chip.
引文
[1]王燕,谭泽富.中国移动多媒体广播(CMMB)技术分析[J].广东通信技术, 2009,(04)
[2]帅炜.手机电视标准的传输系统研究[D].北京邮电大学, 2008
[3]张超.基于DMB_TH的移动数字电视接收机的设计与实现[D].北京邮电大学, 2008
[4]李金秋.中国手机电视发展现状研究[D].北京师范大学, 2008
[5]刘文慧,王颖.移动数字电视发展状况分析[J].改革与开放, 2009.05
[6] M. John S. Smith. Application-Specific Integrated Circuits. Addison-Wesley, 1997
[7]刘丽华,辛德禄,李本俊.专用集成电路设计方法.北京:北京邮电出版社, 2000, 5-9, 104-107
[8]蔡懿慈,周强.超大规模集成电路设计导论.北京:清华大学出版社, 2005.1, 89-97
[9] Verilog-2001[S], IEEE Standard 1364-2001, 2001
[10]俞国亮.一种I2C总线竞争与仲裁电路的设计.计算机工程与应用, 2005.08
[11]胡文静,李外云,刘锦高. I2C总线接口的FPGA实现研究.计算机工程与应用, 2005.12
[12] J BHASKER. A Verilog HDL Printer (second Edition).徐振林译. Verilog HDL硬件描述语言.北京:机械工业出版社,2000, 22-34, 63-64
[13] IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std1364-1995, 1995
[14] Arnold M. , Verilog Digital Computer Design: Algorithms to Hardware, Prentice Hall, NJ,1998.
[15] Michael D. Ciletti. Verilog HDL高级数字设计[M].张雅绮,李锵译.北京:电子工业出版社, 2005, 18-19, 31-33, 79-82
[16]张延伟,杨金岩,葛爱学. Verilog HDL程序设计实例详解[M].北京:人民邮电出版社, 2008, 156-179
[17]林丰成. Verilog HDL Coding Style Specification. Teralance Semiconductor Internal Training Material, 2005, 44-57
[18] Zainalabedin Navabi. Verilog数字系统设计——RTL综合、测试平台与验证[M].李广军,陈亦欧译.北京:电子工业出版社, 2007, 38-49
[19]吴继华,王诚.设计与验证Verilog HDL.北京:人民邮电出版社, 2006, 51-53
[20] Uwe Meyer-Basese著.数字信号处理的FPGA实现.刘凌,胡永生译.北京:清华大学出版社, 2002, 4-7, 132-149
[21]刘韬,楼兴华. FPGA数字电子系统设计与开发实例导航.北京:人民邮电出版社, 2005, 12-14, 106-121
[22]田耘,徐文波,胡彬. Xilinx ISE Design Suite 10.x FPGA开发指南——逻辑设计篇[M].北京:人民邮电出版社, 2008, 72-81
[23] Hassoum S, Sasao T. Logic Synthesis and Verification. Kluwer Academic Publushers, Dordrecht, 2002, 23-26
[24]林丰成,竺红卫,李立.数字集成电路设计与技术.北京:科学出版社, 2008. 190-195.
[25] Bhatnagar H. Advanced ASIC CHIP Synthesis: Using Synopsys’Design Compiler and Prime Time. 2nd Edition. Kluwer Academic Publishers, 2001
[26] Cadence. SoC Encounter XL RTL-to-GDSII Hierarchical Flow. Manual version 5.2, 2006.3
[27] Sarrafzadeh M, Wang M, Yang X. Moden Placement Techniques. Springer, 2002: 320
[28] Iwauchi A. A Timing-Driven Standard-Cell Placement Method Based on a New Clustering Placement Model(Master thesis). Graduate School of Engineering, Hiroshima University, 2002
[29] Santarini M. Taking a Bite Out of Power: Techniques for Low-Power-ASIC Design. EDN Europe, 2007
[30]陈春章,艾霞,王国雄.数字集成电路物理设计.北京:科学出版社, 2008, 152-166
[31] Erik Brunvand. Digital VLSI Chip Design with Cadence and Synopsys CAD Tools[M]. America, 2009, 137-143
[2]帅炜.手机电视标准的传输系统研究[D].北京邮电大学, 2008
[3]张超.基于DMB_TH的移动数字电视接收机的设计与实现[D].北京邮电大学, 2008
[4]李金秋.中国手机电视发展现状研究[D].北京师范大学, 2008
[5]刘文慧,王颖.移动数字电视发展状况分析[J].改革与开放, 2009.05
[6] M. John S. Smith. Application-Specific Integrated Circuits. Addison-Wesley, 1997
[7]刘丽华,辛德禄,李本俊.专用集成电路设计方法.北京:北京邮电出版社, 2000, 5-9, 104-107
[8]蔡懿慈,周强.超大规模集成电路设计导论.北京:清华大学出版社, 2005.1, 89-97
[9] Verilog-2001[S], IEEE Standard 1364-2001, 2001
[10]俞国亮.一种I2C总线竞争与仲裁电路的设计.计算机工程与应用, 2005.08
[11]胡文静,李外云,刘锦高. I2C总线接口的FPGA实现研究.计算机工程与应用, 2005.12
[12] J BHASKER. A Verilog HDL Printer (second Edition).徐振林译. Verilog HDL硬件描述语言.北京:机械工业出版社,2000, 22-34, 63-64
[13] IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std1364-1995, 1995
[14] Arnold M. , Verilog Digital Computer Design: Algorithms to Hardware, Prentice Hall, NJ,1998.
[15] Michael D. Ciletti. Verilog HDL高级数字设计[M].张雅绮,李锵译.北京:电子工业出版社, 2005, 18-19, 31-33, 79-82
[16]张延伟,杨金岩,葛爱学. Verilog HDL程序设计实例详解[M].北京:人民邮电出版社, 2008, 156-179
[17]林丰成. Verilog HDL Coding Style Specification. Teralance Semiconductor Internal Training Material, 2005, 44-57
[18] Zainalabedin Navabi. Verilog数字系统设计——RTL综合、测试平台与验证[M].李广军,陈亦欧译.北京:电子工业出版社, 2007, 38-49
[19]吴继华,王诚.设计与验证Verilog HDL.北京:人民邮电出版社, 2006, 51-53
[20] Uwe Meyer-Basese著.数字信号处理的FPGA实现.刘凌,胡永生译.北京:清华大学出版社, 2002, 4-7, 132-149
[21]刘韬,楼兴华. FPGA数字电子系统设计与开发实例导航.北京:人民邮电出版社, 2005, 12-14, 106-121
[22]田耘,徐文波,胡彬. Xilinx ISE Design Suite 10.x FPGA开发指南——逻辑设计篇[M].北京:人民邮电出版社, 2008, 72-81
[23] Hassoum S, Sasao T. Logic Synthesis and Verification. Kluwer Academic Publushers, Dordrecht, 2002, 23-26
[24]林丰成,竺红卫,李立.数字集成电路设计与技术.北京:科学出版社, 2008. 190-195.
[25] Bhatnagar H. Advanced ASIC CHIP Synthesis: Using Synopsys’Design Compiler and Prime Time. 2nd Edition. Kluwer Academic Publishers, 2001
[26] Cadence. SoC Encounter XL RTL-to-GDSII Hierarchical Flow. Manual version 5.2, 2006.3
[27] Sarrafzadeh M, Wang M, Yang X. Moden Placement Techniques. Springer, 2002: 320
[28] Iwauchi A. A Timing-Driven Standard-Cell Placement Method Based on a New Clustering Placement Model(Master thesis). Graduate School of Engineering, Hiroshima University, 2002
[29] Santarini M. Taking a Bite Out of Power: Techniques for Low-Power-ASIC Design. EDN Europe, 2007
[30]陈春章,艾霞,王国雄.数字集成电路物理设计.北京:科学出版社, 2008, 152-166
[31] Erik Brunvand. Digital VLSI Chip Design with Cadence and Synopsys CAD Tools[M]. America, 2009, 137-143