片上网络多播通信关键技术研究
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摘要
随着亚微米技术的发展,在单个芯片上集成越来越多的晶体管成为可能,这意味着越来越多的处理器核被集成在一块芯片上。传统总线通信方式已不能满足片上系统SoC (System on chip)数据的通信要求,为了解决这个问题,提出了以通信为核心的复杂SoC的IP核集成方法,即片上网络NOC (Network on chip),以解决复杂SoC面临的各种问题。片上网络成为替代总线通信方式一个比较好的体系结构,其核心是把网络设计的思想移植到芯片设计中,将片上资源(IP核)互连起来,并将计算与通信分离。片上网络具有很好的空间可扩展性,采用的全局异步-局部同步的通信机制使并行通信效率更高。NOC带来了一种全新的片上通信方式,它的引入有利于提升可重用设计、解决通信瓶颈和全局同步等难题。
总线通信方式能有效的处理多播消息,而NOC不能直接支持多播,而随着核数增多,核间通信量增大,常规的单播通信逐渐不能满足应用需求,而片上网络的多播通信方式,能缓解资源负担,有效的利用带宽。本文在研究片上网络结构的基础上,重点讨论了几种典型的片上网络多播路由算法,分析和比较了几种多播路由算法的性能,并针对片上网络多播通信的特点提出了拥塞控制机制。本文的主要工作如下：
1.NOC体系结构基础研究,包括片上网络的拓扑结构、交换技术以及路由算法,分析和总结了各种方法的优缺点。
2.在研究NOC结构的基础上,提出了片上网络多播通信问题,它能够减少NOC总的通信量,提高片上网络的通信效率。重点研究了片上网络多播路由算法,分析和比较了几种多播路由算法的性能,实验结果表明片上网络的多播通信比单播具有更小的网络延迟和平均跳数且负载分配均匀,随着规模增大有更明显的效果。
3.构建了NOC多播通信仿真平台,能方便对片上网络单播和多播通信仿真,对本文中各种算法进行了仿真与分析。
4.研究了片上网络死锁避免和多播通信的拥塞控制机制问题,提出了片上网络两级拥塞控制机制,通过这个拥塞控制机制能进一步提高通信效率,并给出了仿真结果。
With the development of sub-micron technology, it's possible that more and more transistors can be integrated on a single chip, which means that more and more cores are integrated on a single chip. Traditional bus communication can not satisfy data transmission requirements of SoC (System on chip), in order to solve this problem, IP core integration approach of complicated SoC in which communication serves as the core be proposed, that is NOC (Network on chip) to solve the complex problems faced by SoC. NOC turns to be a better architecture replacing bus communication-based one. The core idea is to migrate network design to chip design, which interconnect IP core and separate communication from computation. NOC has good spatial scalability, communication mechanism of global asynchronous-locally synchronous makes the parallel communications more efficient. NOC has brought a new on-chip communication, its introduction can enhance reusable design, solve the problems of communication bottlenecks and global synchronization.
The bus communication can effectively deal with the multicast messages, but NOC can not directly support multicast. With the increase of IP block and communication between IP, conventional unicast communications can not meet the application requirements gradually, while multicast for NOC can ease the resource burden and use bandwidth effectively. This paper studies several typical multicast routing algorithms for NOC, analyzes and compares their performance.Finally we propose multicast congestion control mechanism according to the characteristics of multicast for NOC. The major research contents of this paper show as follows.
1. This paper researches basic architecture of NOC, including topology, switching and routing algorithm. Analyze and compare the advantages and disadvantages of each method.
2. This paper proposes multicast communication problem for NOC based on architecture of NOC, which can reduce the total network traffic and improve the efficiency of communication. Study multicast routing algorithm for NOC, analyze and compare their performance. The simulation experiment results show multicast routing algorithms have shorter average latency and higher throughput and balance applied load compared with unicast routing algorithms. SubPartition routing algorithm is confirmed to have a more stable and better performance as the network size increases.
3. Build software simulation platform for NOC, which can simulate unicast and multicast algorithms conveniently. Various multicast algorithms are simulated and analyzed in this paper.
4. Study deadlock avoidance and multicast congestion control for NOC. This paper proposes multicast congestion control mechanism based on architecture of NOC. This congestion control can improve communication efficiency further. Evaluation results also analyze through simulation platform in this paper.
总线通信方式能有效的处理多播消息,而NOC不能直接支持多播,而随着核数增多,核间通信量增大,常规的单播通信逐渐不能满足应用需求,而片上网络的多播通信方式,能缓解资源负担,有效的利用带宽。本文在研究片上网络结构的基础上,重点讨论了几种典型的片上网络多播路由算法,分析和比较了几种多播路由算法的性能,并针对片上网络多播通信的特点提出了拥塞控制机制。本文的主要工作如下：
1.NOC体系结构基础研究,包括片上网络的拓扑结构、交换技术以及路由算法,分析和总结了各种方法的优缺点。
2.在研究NOC结构的基础上,提出了片上网络多播通信问题,它能够减少NOC总的通信量,提高片上网络的通信效率。重点研究了片上网络多播路由算法,分析和比较了几种多播路由算法的性能,实验结果表明片上网络的多播通信比单播具有更小的网络延迟和平均跳数且负载分配均匀,随着规模增大有更明显的效果。
3.构建了NOC多播通信仿真平台,能方便对片上网络单播和多播通信仿真,对本文中各种算法进行了仿真与分析。
4.研究了片上网络死锁避免和多播通信的拥塞控制机制问题,提出了片上网络两级拥塞控制机制,通过这个拥塞控制机制能进一步提高通信效率,并给出了仿真结果。
With the development of sub-micron technology, it's possible that more and more transistors can be integrated on a single chip, which means that more and more cores are integrated on a single chip. Traditional bus communication can not satisfy data transmission requirements of SoC (System on chip), in order to solve this problem, IP core integration approach of complicated SoC in which communication serves as the core be proposed, that is NOC (Network on chip) to solve the complex problems faced by SoC. NOC turns to be a better architecture replacing bus communication-based one. The core idea is to migrate network design to chip design, which interconnect IP core and separate communication from computation. NOC has good spatial scalability, communication mechanism of global asynchronous-locally synchronous makes the parallel communications more efficient. NOC has brought a new on-chip communication, its introduction can enhance reusable design, solve the problems of communication bottlenecks and global synchronization.
The bus communication can effectively deal with the multicast messages, but NOC can not directly support multicast. With the increase of IP block and communication between IP, conventional unicast communications can not meet the application requirements gradually, while multicast for NOC can ease the resource burden and use bandwidth effectively. This paper studies several typical multicast routing algorithms for NOC, analyzes and compares their performance.Finally we propose multicast congestion control mechanism according to the characteristics of multicast for NOC. The major research contents of this paper show as follows.
1. This paper researches basic architecture of NOC, including topology, switching and routing algorithm. Analyze and compare the advantages and disadvantages of each method.
2. This paper proposes multicast communication problem for NOC based on architecture of NOC, which can reduce the total network traffic and improve the efficiency of communication. Study multicast routing algorithm for NOC, analyze and compare their performance. The simulation experiment results show multicast routing algorithms have shorter average latency and higher throughput and balance applied load compared with unicast routing algorithms. SubPartition routing algorithm is confirmed to have a more stable and better performance as the network size increases.
3. Build software simulation platform for NOC, which can simulate unicast and multicast algorithms conveniently. Various multicast algorithms are simulated and analyzed in this paper.
4. Study deadlock avoidance and multicast congestion control for NOC. This paper proposes multicast congestion control mechanism based on architecture of NOC. This congestion control can improve communication efficiency further. Evaluation results also analyze through simulation platform in this paper.
引文
[1]HENKEL,WOLF,CHAKRADHAR S. On-chip networks a scalable, communication-centric embedded system design paradigm[C].Proceedings of the 17th International Conference on VLSI Design. Piscataway:IEEE Press,2004.
[2]Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, et al.Outstanding Research Problems in NOC Design:System, Microarchitecture, and Circuit Perspectives[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2009,28(1):3-21.
[3]Natalie Enright-Jerger, Li-Shiuan Peh, Mikko H. Lipasti. Virtual Circuit Tree Multicasting:A Case for On-Chip Hardware Multicast Support[C].35th International Symposium on Computer Architecture. IEEE Press,2008.
[4]Umit Y. Ogras,Radu Marculescu. Prediction-based Flow Control for Network-on-Chip Traffic[C].2006 43rd ACM/IEEE Design Automation Conference. IEEE Press,2006.
[5]Samuel Rodrigo, Jos'e Flich, Jos'e Duato, et al. Efficient Unicast and Multicast Support for CMPs[C].41st IEEE/ACM International Symposium on Microarchitecture. IEEE Press, 2008.
[6]Zhonghai Lu, Rikard Thid, Mikael Millberg, etal.NNSE:Nostrum Network-on-Chip simulation environment [C]. Fifth International Workshop on System-on-Chip for Real-Time Applications. IEEE Press,2005.
[7]Mikael Millberg, Erland Nilsson, Rikard Thid, etal.The Nostrum backbone-a communication protocol stack for networks on chip [C]. Proceedings of the VLSI Design Conference, Mumbai, IEEE Press,2004.
[8]M. B. Taylor, J. Kim, J. Miller, et al. The Raw Microprocessor:A Computational Fabric for Software Circuits and General-Purpose Programs[J].Micro,2002,22(2):25-35.
[9]W. J. Bainbridge,S. B. Furber. CHAIN:A Delay Insensitive Chip Area Interconnect [J]. IEEE Micro special issue on Design and Test of System on Chip.2002,22(5):16-23.
[10]Davide Bertozzi,Luca Benini. Xpipes:A Network-on-Chip Architecture for Gigascale systems-on-Chip[J]. IEEE Circuits and Systems Magazine.2004,4(2):18-31.
[11]Adrijean Adriahantenaina, Herve Charlery, Alain Greiner, et al. SPIN:A Scalable, Packet Switched, On-Chip Micro-Network[C].Proceedings of the conference on Design, Automation and Test in Europe. IEEE Press,2003.
[12]T.Bjerregaard,K.mahadevan. A survey of research and practices of network-on-chip[J]. ACM Computing Surveys.2006,38(1):51-56.
[13]武畅,李玉柏,彭启琮.一种用于Multi-Processor测量系统的NOC结构的路由节点设计及性能评估[J].电子测量与仪器学报,2008,22(5)：101-106.
[14]林世俊,苏厉,曾烈光,等.虚通道数和时钟比率对片上网络的影响[J].清华大学学报(自然科学版),2009,49(1)：86-89.
[15]LIN Shijun,SU Li, ZENG Lieguang, et al.Universal GALS Platform and Evaluation Methodology for Networks-on-Chip[J],Journal of Tsinghua University(Science and Technology).2009,4(2):21-25.
[16]韩高飞,杜慧敏,韩俊刚,等.基于FPGA的NOC验证平台的构建[J].电子设计工程,2010,18(3)：90-93.
[17]杨晓强,谭耀东,韩俊刚,等.NOC节点编码及路由算法的研究[J].计算机科学,2009,36(3)：86-89.
[18]方芳,董建波,韩银和,等.支持多播路径传输的片上网络并行测试方法.电子测量与仪器学报[J],2010,24(10)：911-917.
[19]付斌章,韩银和,李华伟,等.面向高可靠片上网络通信的低成本可重构路由算法[C].第六届中国测试学术会议论文集,合肥：中国计算机学会,2010年.
[20]谢佩博,顾华玺,贾林.片上网络路由算法的研究[J].计算机工程与设计,2009,30(13)：3078-3082.
[21]王峥,顾华玺,杨烨,等.片上网络交换机制的研究[J].中国集成电路,2007(12)：22-28.
[22]谢斌,胡威,陈天洲.片上网络系统中动态重构性能评估模型[J].工业控制计算机,2007,23(4)：64-67.
[23]Aline Mello, LeonelTedesco, Ney Calazans, et al.Virtual Channels in Networks on Chip:Implementation and Evaluation on Hermes NOC[C].18th Symposium on Integrated Circuits and Systems Design. IEEE Press,2005.
[24]A.Jantsch, Kumar, A.Postula, et al. Network on chip:An architecture for billion transistor [C].In Proceeding of the NOC Chip Conference. IEEE Press,2000.
[25]Stanley F B, Pratim P P. Networks-on-chip in a three dimensional environment:a performance evaluation [J]. IEEE Transaction on Computer.2009,58(1):32-45.
[26]Matsutani H, Koibuchi M, Amano H. Tightly-coupled multi-layer topologies for 3D NOCs[C]. International Conference on Parallel Processing. Xi'an. IEEE Press,2007.
[27]DUATO J, YALAMANCH IL I S, L IONEL N. Interconnection networks:An engineering approach [M]. San Francisco:Morgan Kaufmann Publishers Inc,2002:28-44.
[28]ADR IAHANTENA INA A, CHARLERY H, GREINER A, et al. SPIN:A scalable, packet switched, on2chip micro2network [C] Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Washington:IEEE Computer Society,2003.
[29]张恒龙,顾华玺,王长山.片上网络拓扑结构的研究[J].中国集成电路设计,2007(11)：42-47
[30]W.J. Dally, B. Towles.Route Packets,Not Wires:On Chip Interconnection Networks[C].Proceeding of Design Automation Conference. IEEE Press,2001.
[31]陈亦欧,胡剑浩,凌翔.三维片上网络拓扑研究[J].研究与开发.2009(4)：39-45.
[32]XinPing Zhu,Wei Qin, Sharad Malik. Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation[C]. International Conference on Hardware/Software Codesign and System Synthesis. IEEE Press,2004.
[33]L.Jain."Nirgam,"in University of Southampton UK, http://www.nirgam.ecs.soton.ac.uk.
[34]G.Varatkar, R.Mareuleseu. Traffic Analysis for On-Chip Networks Design Multimedia Applications[C]. Proceeding of Design Automation Conference. IEEE Press,2002.
[35]H. Hossain, M. Ahmed, A. Al-Nayeem, et al. GPNOCSIM A General Purpose Simulator for Network-on-Chip[C]. International Conference on information and Communication Technology. IEEE Press,2007.
[36]Pablo Abad, Valentin Puente, Jose-Angel Gregorio. MRR:Enabling Fully Adaptive Multicast Routing for CMP Interconnection Networks[C]. IEEE 15th International Symposium on High Performance Computer Architecture. IEEE Press,2009.
[37]XIAOLA LIN,MCKINLEY, P.K, NI,L.M. Deadlock-Free Multicast Wormhole Routing in 2-D Mesh Multicomputers[J].IEEE Transactions on Parallel and Distributed Systems, 1994,5(8):793-804.
[38]Everton Alceu Carara, Fernando Gehm Moraes. Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh networks-on-Chip[C].IEEE Computer Society Annual Symposium on VLSI. IEEE Computer Society,2008.
[39]Elvira Baydal, Pedro Lo'pez, and Jose'Duato.A Family of Mechanisms for Congestion Control in Wormhole Networks[J].IEEE Transactions on Parallel and Distributed Systems.2005,16(9):772-785.
[40]Umit Y. Ogras,Radu Marculescu.Prediction-based Flow Control for Network-on-Chip Traffic[C].43rd ACM/IEEE Design Automation Conference. IEEE Press,2006.
[41]J.W.van den Brand, C. Ciordas, K. Goossensl, et al. Congestion-Controlled Best-Effort Communication for Networks-on-Chip[C]. Design, Automation & Test in Europe Conference & Exhibition. IEEE Press,2007.
[42]Fahimeh Jafari, Mohammad H. Yaghmaee. A Novel Flow Control Scheme for Best Effort Traffics in Network-on-Chip Based on Weighted Max-Min-Fairness[C]. Internatioal Symposium on Telecommunications. IEEE Press,2008.
[43]武畅.片上网络体系结构和关键通信技术研究[D].成都：电子科技大学,2008.
[44]Srinivasan Jagannathan, Kevin C. Almeroth.Using Tree Topology for Multicast Congestion Control [C]. International Conference on Parallel Processing. IEEE Computer Society,2001.
[45]P.Lotfi-Kamran, A.M. Rahmani, M. Daneshtalab, et al. EDXY-A low cost congestion-aware routing algorithm for network-on-chips[J]. Journal of Systems Architecture,2010,56(7): 256-264.
[46]Xu Wang, Ge Gan, Dongrui Fan, et al. GFFC:The Global Feedback Based Flow Control in the NOC Design for Many-core Processor[C].2009 Sixth IFIP International Conference on Network and Parallel Computing,IEEE Computer Society,2009.
[47]Huaxi Gu, Jiang Xu, KunWang. A new distributed congestion control mechanism for networks on chip[J]. Telecommunication Systems,2009,44(3):321-331.
[48]Jingling Yuan, Jingjing He, Luo Zhong, GA Based Congestion Aware Algorithm for Router Utilization in NOC Architecture[C]. International Conference on Computational Intelligence and Software Engineering,WuHan:IEEE Computer Society,2009:1-5.
[2]Radu Marculescu, Umit Y. Ogras, Li-Shiuan Peh, et al.Outstanding Research Problems in NOC Design:System, Microarchitecture, and Circuit Perspectives[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2009,28(1):3-21.
[3]Natalie Enright-Jerger, Li-Shiuan Peh, Mikko H. Lipasti. Virtual Circuit Tree Multicasting:A Case for On-Chip Hardware Multicast Support[C].35th International Symposium on Computer Architecture. IEEE Press,2008.
[4]Umit Y. Ogras,Radu Marculescu. Prediction-based Flow Control for Network-on-Chip Traffic[C].2006 43rd ACM/IEEE Design Automation Conference. IEEE Press,2006.
[5]Samuel Rodrigo, Jos'e Flich, Jos'e Duato, et al. Efficient Unicast and Multicast Support for CMPs[C].41st IEEE/ACM International Symposium on Microarchitecture. IEEE Press, 2008.
[6]Zhonghai Lu, Rikard Thid, Mikael Millberg, etal.NNSE:Nostrum Network-on-Chip simulation environment [C]. Fifth International Workshop on System-on-Chip for Real-Time Applications. IEEE Press,2005.
[7]Mikael Millberg, Erland Nilsson, Rikard Thid, etal.The Nostrum backbone-a communication protocol stack for networks on chip [C]. Proceedings of the VLSI Design Conference, Mumbai, IEEE Press,2004.
[8]M. B. Taylor, J. Kim, J. Miller, et al. The Raw Microprocessor:A Computational Fabric for Software Circuits and General-Purpose Programs[J].Micro,2002,22(2):25-35.
[9]W. J. Bainbridge,S. B. Furber. CHAIN:A Delay Insensitive Chip Area Interconnect [J]. IEEE Micro special issue on Design and Test of System on Chip.2002,22(5):16-23.
[10]Davide Bertozzi,Luca Benini. Xpipes:A Network-on-Chip Architecture for Gigascale systems-on-Chip[J]. IEEE Circuits and Systems Magazine.2004,4(2):18-31.
[11]Adrijean Adriahantenaina, Herve Charlery, Alain Greiner, et al. SPIN:A Scalable, Packet Switched, On-Chip Micro-Network[C].Proceedings of the conference on Design, Automation and Test in Europe. IEEE Press,2003.
[12]T.Bjerregaard,K.mahadevan. A survey of research and practices of network-on-chip[J]. ACM Computing Surveys.2006,38(1):51-56.
[13]武畅,李玉柏,彭启琮.一种用于Multi-Processor测量系统的NOC结构的路由节点设计及性能评估[J].电子测量与仪器学报,2008,22(5)：101-106.
[14]林世俊,苏厉,曾烈光,等.虚通道数和时钟比率对片上网络的影响[J].清华大学学报(自然科学版),2009,49(1)：86-89.
[15]LIN Shijun,SU Li, ZENG Lieguang, et al.Universal GALS Platform and Evaluation Methodology for Networks-on-Chip[J],Journal of Tsinghua University(Science and Technology).2009,4(2):21-25.
[16]韩高飞,杜慧敏,韩俊刚,等.基于FPGA的NOC验证平台的构建[J].电子设计工程,2010,18(3)：90-93.
[17]杨晓强,谭耀东,韩俊刚,等.NOC节点编码及路由算法的研究[J].计算机科学,2009,36(3)：86-89.
[18]方芳,董建波,韩银和,等.支持多播路径传输的片上网络并行测试方法.电子测量与仪器学报[J],2010,24(10)：911-917.
[19]付斌章,韩银和,李华伟,等.面向高可靠片上网络通信的低成本可重构路由算法[C].第六届中国测试学术会议论文集,合肥：中国计算机学会,2010年.
[20]谢佩博,顾华玺,贾林.片上网络路由算法的研究[J].计算机工程与设计,2009,30(13)：3078-3082.
[21]王峥,顾华玺,杨烨,等.片上网络交换机制的研究[J].中国集成电路,2007(12)：22-28.
[22]谢斌,胡威,陈天洲.片上网络系统中动态重构性能评估模型[J].工业控制计算机,2007,23(4)：64-67.
[23]Aline Mello, LeonelTedesco, Ney Calazans, et al.Virtual Channels in Networks on Chip:Implementation and Evaluation on Hermes NOC[C].18th Symposium on Integrated Circuits and Systems Design. IEEE Press,2005.
[24]A.Jantsch, Kumar, A.Postula, et al. Network on chip:An architecture for billion transistor [C].In Proceeding of the NOC Chip Conference. IEEE Press,2000.
[25]Stanley F B, Pratim P P. Networks-on-chip in a three dimensional environment:a performance evaluation [J]. IEEE Transaction on Computer.2009,58(1):32-45.
[26]Matsutani H, Koibuchi M, Amano H. Tightly-coupled multi-layer topologies for 3D NOCs[C]. International Conference on Parallel Processing. Xi'an. IEEE Press,2007.
[27]DUATO J, YALAMANCH IL I S, L IONEL N. Interconnection networks:An engineering approach [M]. San Francisco:Morgan Kaufmann Publishers Inc,2002:28-44.
[28]ADR IAHANTENA INA A, CHARLERY H, GREINER A, et al. SPIN:A scalable, packet switched, on2chip micro2network [C] Proceedings of Design, Automation and Test in Europe Conference and Exhibition. Washington:IEEE Computer Society,2003.
[29]张恒龙,顾华玺,王长山.片上网络拓扑结构的研究[J].中国集成电路设计,2007(11)：42-47
[30]W.J. Dally, B. Towles.Route Packets,Not Wires:On Chip Interconnection Networks[C].Proceeding of Design Automation Conference. IEEE Press,2001.
[31]陈亦欧,胡剑浩,凌翔.三维片上网络拓扑研究[J].研究与开发.2009(4)：39-45.
[32]XinPing Zhu,Wei Qin, Sharad Malik. Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation[C]. International Conference on Hardware/Software Codesign and System Synthesis. IEEE Press,2004.
[33]L.Jain."Nirgam,"in University of Southampton UK, http://www.nirgam.ecs.soton.ac.uk.
[34]G.Varatkar, R.Mareuleseu. Traffic Analysis for On-Chip Networks Design Multimedia Applications[C]. Proceeding of Design Automation Conference. IEEE Press,2002.
[35]H. Hossain, M. Ahmed, A. Al-Nayeem, et al. GPNOCSIM A General Purpose Simulator for Network-on-Chip[C]. International Conference on information and Communication Technology. IEEE Press,2007.
[36]Pablo Abad, Valentin Puente, Jose-Angel Gregorio. MRR:Enabling Fully Adaptive Multicast Routing for CMP Interconnection Networks[C]. IEEE 15th International Symposium on High Performance Computer Architecture. IEEE Press,2009.
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