纳米CMOS集成电路单粒子诱导的脉冲窄化及电荷共享效应研究
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摘要
我国航天科技迅速发展，航天器对先进集成电路抗辐照技术的研究需求十分迫切。随着集成电路工艺的不断进步、芯片上集成的晶体管数目不断增加、时钟频率不断增加、工作电压以及节点电容不断降低，电荷共享已逐渐成为纳米集成电路单粒子失效的主要模式之一。
在纳米工艺下，器件尺寸以及器件间距的缩减使得单个重离子轨迹已经能够同时覆盖多器件，从而导致多个器件同时收集电荷。一方面，电荷共享效应导致的MBU使得目前针对单个节点的加固方法如DICE、TMR等都将面临失效，因此抑制电荷共享效应成为抑制电路发生软错误的重要手段；另一方面，研究表明电荷共享效应可能由于发生脉冲窄化（Pulse Quenching）而导致电路中传播的SET脉冲宽度缩减，因此增强电相关邻近晶体管间的电荷共享效应也成为了单粒子效应加固的一种思路。版图结构、外界粒子、工艺掺杂、电源电压、体偏置等因素都会随着实际应用环境的改变而变化，研究这些因素对电荷共享及脉冲窄化的影响将对抗辐照集成电路设计提供理论依据。此外，由于SRAM存储结构的单粒子效应敏感特性及其加固的重要性，充分考虑此类电路在纳米尺度下的电荷共享效应机理及提出有效的加固策略，对于纳米抗辐照加固集成电路设计具有重要指导意义。本文针对纳米CMOS体硅工艺，对电荷共享效应的物理机理及加固技术进行了深入讨论，主要取得如下几个方面的研究成果：
（1）发现相邻两个器件的间距和它们之间的信号传播延迟最小时，可以最大的抑制传播的SET脉冲宽度，这为纳米工艺下辐射加固集成电路的设计提供了新的思路。研究了影响脉冲窄化效应的各种关键性因素，结果表明传播的SET脉宽与入射粒子的能量并不成正比关系，因此利用多节点电荷收集进行抗辐射加固电路设计时需要注意电路发生SET/SEU的LET阈值界定，即电路在高LET值时满足抗辐照指标却可能在较低LET值时产生软错误，辐照试验应该对产生最坏响应的LET值进行重点评估。
（2）发现改变P+深阱掺杂和衬底掺杂将会影响电荷收集量，从而影响到电路中传播的SET脉冲宽度，从抗辐照加固的角度提出在允许的范围内适当降低P+深阱的掺杂浓度或提高衬底的掺杂浓度，可以最大程度的减小传播的SET脉宽。本文研究了P+深阱掺杂和衬底掺杂对电荷共享效应及脉冲窄化的影响，结果表明P+深阱掺杂和衬底掺杂都主要是影响SET电流中的双极放大成份，改变这些浓度对NMOS器件影响不大，而对PMOS器件的影响十分显著。
（3）发现在电荷共享效应显著的电路中，传播至下一级的SET脉冲宽度随着电源电压的缩减而降低，该结论修正了以往认为超低功耗应用电路对单粒子事件会更加敏感的悲观结论。本文研究了电源电压对电荷收集机理的影响，表明电源电压主要是影响寄生BJT的双极放大增益，源极在SET脉冲的电源电压相关性中起到了重要作用。
（4）发现对于反向体偏置的低功耗设计技术，P-hit的SEE敏感性保持不变；对于正向偏置的高速电路应用，P-hit的SEE敏感性随着体偏电压的增大会降低，同时N-hit的SEE敏感性却几乎与体偏置无关。本文研究了体硅CMOS双阱工艺中体偏置效应对SET、电荷共享及脉冲窄化的影响，对于发生脉冲窄化的电路，随着体偏电压的增大，传播至下一级的SET脉冲宽度会增加，这与单个节点的变化情况恰好相反。
（5）发现SRAM单元中由于电荷共享而导致的单粒子翻转恢复效应的新机理，以此为基础提出了一种新型抗SEU的SRAM版图结构。结论表明电荷共享收集在SEU恢复过程中起关键性的作用，更大角度的轰击可能会引起更强的电荷共享效应，从而增强了存储状态发生单粒子翻转恢复的能力。本文提出的版图结构可以在可靠性和面积开销方面同时获得好处，这对于纳米工艺下降低单粒子翻转的抗辐照加固设计具有重要的借鉴价值。
With the rapid development of China's aerospace science and technology, theresearch work of anti-radiation technology for advanced ICs is very urgent forspacecraft. With the continuous development of ICs technology, the number oftransistors integrated on a chip is increasing, clock frequency is increasing, theoperating voltage and the node capacitance are reducing, thus charge sharing hasbecome one of the main failure mode of nano ICs caused by Single Event.
For nano technology, an ion trajectory has been able to cover more than one devicedue to the reduction of the device feature and the layout spacing, leading to multipledevices simultaneously collect charges. On the one hand, MBU led by the chargesharing effect makes radiation-harden methods such as DICE, TMR, are all facingfailure, thus inhibiting the charge sharing becomes one of the important mean ofinhibiting soft error in circuits. On the other hand, studies have shown that chargesharing may lead to the propagating SET pulsewidths reducing, thus enhancing thecharge sharing effect between the electrically adjacent transistors also becomes aneffective method. Layout structures, particles from the airspace, process doping, supplyvoltage, body bias and other factors will vary with the application environment, andunderstanding the influence of these factors on the charge sharing and Pulse Quenchingcan provide guidance for irradiation ICs design. In addition, due to the sensitivecharacteristics of SRAM cells to SEE, fully considering charge sharing mechanism ofsuch circuit in nanoscale and proposing effective reinforcement strategy are significantfor nano radiation-hardened design. Based on nano CMOS bulk silicon technology, thispaper investigated the physical mechanism of the charge sharing and radiation-hardentechnology in-depth, and mainly achieved the following aspects:
(1) It is found that the SET pulsewidths can be greatly inhibited by minimizing thelayout spacing and signal propagation delay, which sheds new light on theradiation-hardened ICs design. The impact of key factors on Pulse Quenching wasstudied in depth, and the results show that the SET pulsewidths of propagation are not indirect proportion to the LET of incident particles, thus the defining of the LET thresholdshould be noted when SET/SEU occurs for the radiation-hardened design. Thecapability of anti-radiation meets the demand when LET is high but some soft errorsmay occur when LET is low. Therefore, radiation experiments should be focused onevaluating the LET that demonstrates the worst response to the circuit.
(2) We have found that P+deep well doping and substrate doping can affect thecharge collection of the active and passive devices in nano-technology, thus affectingthe propagating SET pulsewidths in circuits. The propagating SET pulsewidths can bequenched by reducing the doping of P+deep well or increasing the substrate doping in the appropriate range. The effect of P+deep well doping and substrate doping on chargesharing and Pulse Quenching are investigated, which shows that the doping of P+deepwell mainly affects the bipolar amplification component of SET current, and thatchanging the P+deep well doping has little effect on NMOS but great effect on PMOS.
(3) We have found that the SET pulse width propagating to subsequent stages in acircuit decreases with reduced power supply voltage, which runs counter to thepessimistic conclusion that ultra-low power applications are much more susceptible todisruption from particle strikes. Supply voltage dependency of SET propagation andmulti-node charge collection phenomena in CMOS ICs were also studied.
(4) It is found that the sensitivity of SEE for P-hit is kept constant for the reversebody bias used in low power consumption technology while it reduces with theincreasing of body bias voltage for the forward body bias used in high speed circuits. Atthe same time, the susceptivity of SEE for N-hit is independent of the body bias. Theeffect of body bias on SET, charge sharing and Pulse Quenching were analyzed, and it isshown that the effect of body biasing on SET pulsewidths propagation is contrary withthe hit node when Pulse Quenching effect is considered.
(5) It is found that the multi-node charge collection plays a key role on recoverymechanism, and it is shown that larger angle can bring about stronger charge sharingeffect, thus strengthening the recovery ability. The recovery mechanism of SEU wasstudied and a novel layout has been proposed to reduce the SEU vulnerability inSRAMs. The layout strategy proposed can gain both reliability and area cost benefitsimultaneously.
在纳米工艺下，器件尺寸以及器件间距的缩减使得单个重离子轨迹已经能够同时覆盖多器件，从而导致多个器件同时收集电荷。一方面，电荷共享效应导致的MBU使得目前针对单个节点的加固方法如DICE、TMR等都将面临失效，因此抑制电荷共享效应成为抑制电路发生软错误的重要手段；另一方面，研究表明电荷共享效应可能由于发生脉冲窄化（Pulse Quenching）而导致电路中传播的SET脉冲宽度缩减，因此增强电相关邻近晶体管间的电荷共享效应也成为了单粒子效应加固的一种思路。版图结构、外界粒子、工艺掺杂、电源电压、体偏置等因素都会随着实际应用环境的改变而变化，研究这些因素对电荷共享及脉冲窄化的影响将对抗辐照集成电路设计提供理论依据。此外，由于SRAM存储结构的单粒子效应敏感特性及其加固的重要性，充分考虑此类电路在纳米尺度下的电荷共享效应机理及提出有效的加固策略，对于纳米抗辐照加固集成电路设计具有重要指导意义。本文针对纳米CMOS体硅工艺，对电荷共享效应的物理机理及加固技术进行了深入讨论，主要取得如下几个方面的研究成果：
（1）发现相邻两个器件的间距和它们之间的信号传播延迟最小时，可以最大的抑制传播的SET脉冲宽度，这为纳米工艺下辐射加固集成电路的设计提供了新的思路。研究了影响脉冲窄化效应的各种关键性因素，结果表明传播的SET脉宽与入射粒子的能量并不成正比关系，因此利用多节点电荷收集进行抗辐射加固电路设计时需要注意电路发生SET/SEU的LET阈值界定，即电路在高LET值时满足抗辐照指标却可能在较低LET值时产生软错误，辐照试验应该对产生最坏响应的LET值进行重点评估。
（2）发现改变P+深阱掺杂和衬底掺杂将会影响电荷收集量，从而影响到电路中传播的SET脉冲宽度，从抗辐照加固的角度提出在允许的范围内适当降低P+深阱的掺杂浓度或提高衬底的掺杂浓度，可以最大程度的减小传播的SET脉宽。本文研究了P+深阱掺杂和衬底掺杂对电荷共享效应及脉冲窄化的影响，结果表明P+深阱掺杂和衬底掺杂都主要是影响SET电流中的双极放大成份，改变这些浓度对NMOS器件影响不大，而对PMOS器件的影响十分显著。
（3）发现在电荷共享效应显著的电路中，传播至下一级的SET脉冲宽度随着电源电压的缩减而降低，该结论修正了以往认为超低功耗应用电路对单粒子事件会更加敏感的悲观结论。本文研究了电源电压对电荷收集机理的影响，表明电源电压主要是影响寄生BJT的双极放大增益，源极在SET脉冲的电源电压相关性中起到了重要作用。
（4）发现对于反向体偏置的低功耗设计技术，P-hit的SEE敏感性保持不变；对于正向偏置的高速电路应用，P-hit的SEE敏感性随着体偏电压的增大会降低，同时N-hit的SEE敏感性却几乎与体偏置无关。本文研究了体硅CMOS双阱工艺中体偏置效应对SET、电荷共享及脉冲窄化的影响，对于发生脉冲窄化的电路，随着体偏电压的增大，传播至下一级的SET脉冲宽度会增加，这与单个节点的变化情况恰好相反。
（5）发现SRAM单元中由于电荷共享而导致的单粒子翻转恢复效应的新机理，以此为基础提出了一种新型抗SEU的SRAM版图结构。结论表明电荷共享收集在SEU恢复过程中起关键性的作用，更大角度的轰击可能会引起更强的电荷共享效应，从而增强了存储状态发生单粒子翻转恢复的能力。本文提出的版图结构可以在可靠性和面积开销方面同时获得好处，这对于纳米工艺下降低单粒子翻转的抗辐照加固设计具有重要的借鉴价值。
With the rapid development of China's aerospace science and technology, theresearch work of anti-radiation technology for advanced ICs is very urgent forspacecraft. With the continuous development of ICs technology, the number oftransistors integrated on a chip is increasing, clock frequency is increasing, theoperating voltage and the node capacitance are reducing, thus charge sharing hasbecome one of the main failure mode of nano ICs caused by Single Event.
For nano technology, an ion trajectory has been able to cover more than one devicedue to the reduction of the device feature and the layout spacing, leading to multipledevices simultaneously collect charges. On the one hand, MBU led by the chargesharing effect makes radiation-harden methods such as DICE, TMR, are all facingfailure, thus inhibiting the charge sharing becomes one of the important mean ofinhibiting soft error in circuits. On the other hand, studies have shown that chargesharing may lead to the propagating SET pulsewidths reducing, thus enhancing thecharge sharing effect between the electrically adjacent transistors also becomes aneffective method. Layout structures, particles from the airspace, process doping, supplyvoltage, body bias and other factors will vary with the application environment, andunderstanding the influence of these factors on the charge sharing and Pulse Quenchingcan provide guidance for irradiation ICs design. In addition, due to the sensitivecharacteristics of SRAM cells to SEE, fully considering charge sharing mechanism ofsuch circuit in nanoscale and proposing effective reinforcement strategy are significantfor nano radiation-hardened design. Based on nano CMOS bulk silicon technology, thispaper investigated the physical mechanism of the charge sharing and radiation-hardentechnology in-depth, and mainly achieved the following aspects:
(1) It is found that the SET pulsewidths can be greatly inhibited by minimizing thelayout spacing and signal propagation delay, which sheds new light on theradiation-hardened ICs design. The impact of key factors on Pulse Quenching wasstudied in depth, and the results show that the SET pulsewidths of propagation are not indirect proportion to the LET of incident particles, thus the defining of the LET thresholdshould be noted when SET/SEU occurs for the radiation-hardened design. Thecapability of anti-radiation meets the demand when LET is high but some soft errorsmay occur when LET is low. Therefore, radiation experiments should be focused onevaluating the LET that demonstrates the worst response to the circuit.
(2) We have found that P+deep well doping and substrate doping can affect thecharge collection of the active and passive devices in nano-technology, thus affectingthe propagating SET pulsewidths in circuits. The propagating SET pulsewidths can bequenched by reducing the doping of P+deep well or increasing the substrate doping in the appropriate range. The effect of P+deep well doping and substrate doping on chargesharing and Pulse Quenching are investigated, which shows that the doping of P+deepwell mainly affects the bipolar amplification component of SET current, and thatchanging the P+deep well doping has little effect on NMOS but great effect on PMOS.
(3) We have found that the SET pulse width propagating to subsequent stages in acircuit decreases with reduced power supply voltage, which runs counter to thepessimistic conclusion that ultra-low power applications are much more susceptible todisruption from particle strikes. Supply voltage dependency of SET propagation andmulti-node charge collection phenomena in CMOS ICs were also studied.
(4) It is found that the sensitivity of SEE for P-hit is kept constant for the reversebody bias used in low power consumption technology while it reduces with theincreasing of body bias voltage for the forward body bias used in high speed circuits. Atthe same time, the susceptivity of SEE for N-hit is independent of the body bias. Theeffect of body bias on SET, charge sharing and Pulse Quenching were analyzed, and it isshown that the effect of body biasing on SET pulsewidths propagation is contrary withthe hit node when Pulse Quenching effect is considered.
(5) It is found that the multi-node charge collection plays a key role on recoverymechanism, and it is shown that larger angle can bring about stronger charge sharingeffect, thus strengthening the recovery ability. The recovery mechanism of SEU wasstudied and a novel layout has been proposed to reduce the SEU vulnerability inSRAMs. The layout strategy proposed can gain both reliability and area cost benefitsimultaneously.
引文
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