片上网络拓扑结构与通信方法研究
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摘要
半导体工艺技术进入深亚微米时代后,基于总线系统芯片SoC(system on chip)的体系结构在物理设计、通信带宽以及功耗等方面无法满足未来多IP体系发展的需求。片上网络NoC(network on chip)是一种新的系统芯片体系结构,其核心思想是将计算机网络技术移植到系统芯片设计中来,从体系结构上彻底解决总线架构带来的问题。在NoC系统中,拓扑结构和通信方法是影响片上系统性能的重要因素。本文对NoC的拓扑结构和通信方法进行了深入研究,提出了一些新的解决NoC关键问题的方法,并通过建模仿真和软硬件验证对提出的新方法进行了验证。论文的主要研究成果如下:
1.对NoC的拓扑结构进行了研究。提出了两种适合二维片上网络的拓扑结构,即广义Petersen图( Generalized Petersen , GP(2m, 1) )和网格环形(Mesh Connected-Cycles,MCC)片上网络互连结构。详细分析两种拓扑结构的性质。分别设计了两种拓扑结构的确定性路由算法,对两种拓扑结构进行了模拟分析,并与典型片上网络的mesh拓扑结构进行了比较。在综合考虑网络直径和节点度之积的情况下,GP(2m, 1)和MCC拓扑结构更适合构建片上互连网络。
2.对NoC的交换机制进行了研究。通过分析总结现有的片上网络交换技术,提出了一种缓冲式快速虫孔交换技术。对该交换机制进行了模拟分析并与典型的虚通道虫孔交换技术进行了比较,表明是一种高性能、低成本的交换技术。
3.总结片上网络路由器的基本结构和设计,设计了一种基于缓冲式虫孔交换技术的通用片上网络路由器结构,并对该路由器结构进行了详细设计、功能仿真和性能评估。结果表明该种结构的路由器是一种低延迟的片上网络路由器。
4.分析总结了系统级评估的性能指标和评估流程,建立了系统级仿真平台。该平台是一个模块化、可扩展的系统级仿真平台。
5.设计了一个网络规模为8×8、基于Mesh的片上网络系统。并用ALTERA FPGA开发板验证了其功能,其中的核心模块片上网络路由器和流量产生/接收器已经SMIC 0.13μm工艺下流片,工作频率300MHz,等效逻辑门为515.5k,在300MHz工作频率下功耗约为308.5 mW。
6.通过分析,提出了基于平台的片上网络设计方法,根据该方法建立了一个片上网络开发验证平台。该平台和系统级仿真平台结合可以形成一个集片上网络系统分析、功能仿真、硬件验证和性能评估的完整的片上网络开发验证环境。
7.针对片上网络的发展趋势,对三维片上网络拓扑结构进行了分析和探索,提出了三种适合三维片上网络的拓扑结构,即三维超立方体双环拓扑结构、三维Torus连接的Petersen图拓扑结构、三维长方形扭花环网格拓扑结构。三种拓扑结构都具有高连接度、短直径、简单的路由策略、常数节点度以及良好的可扩展性,适合构建三维片上网络。
As the microelectronics technology expanding, the traditionally idea of System-on-Chip(SoC) to integrate the whole system on a single chip which with only one CPU is in the bus architecture, unable to meet the need of multi-IP architecture development. So several research groups proposed a whole new idea of integrated circuit architecture, Network-on-Chip(NoC). The core idea of NoC is to transplant the knowledge of network technology of computer into the design of chips to systematically solve the problems of bus architecture. In NoC system, topological structures and communication paradigm are important factors in system performance. After in-depth analysis and research in key problems of NoC, we proposed some new solutions to solve the NoC problems. The solutions had been validated by modeling-simulation, software and hardware verification.
The main research results of this thesis are shown as follows:
1. Research on the topological structures of NoC. Two suitable network-on-chip topologies, that is, Generalized Petersen graph(GP(2m,1)) and the Mesh Connected-Cycles (MCC) interconnect network structures are proposed. We made detailed analysis of the character of the two topologies, designed two deterministic routing algorithms of the new topologies, and make a contrast between the GP(2m,1) and the MCC topologies and the typical mesh topology. The results show that MCC and GP(2m,1) have better performance, especially in local traffics and low loads, and lower cost.
2. Research on NoC switching mechanism. A new Buffered Express Wormhole Switching(BEWS) technology of high performance and low cost is proposed. Also a contrast is made between BEWS and typical Virtual Channel Wormhole Switching(VCWS) technology by simulation analysis,which demonstrate BEWS achieves lower latency than VCWS.
3. After making a summary of structure and design of the NoC routers, a new router structure based on BEWS for network-on-chip is designed. And detailed design, functional simulation, and performance evaluation are done to the new router structure. The results shows BEWS router has lower lantency.
4. Analyzed the NoC system-level modeling simulation, summed up system-level performance evaluating process, and then analyzed and designed system-level-simulation network model and traffic model, finally set up a system-level simulation platform. The platform explores the NoC design space in an expandable way.
5. An NoC system, 64 nodes, is designed and verification with FPGA. And synthesis and layout are carried out by SMIC 0. 13μm standard CMOS process and it s hardware scale and power dissipation is 515.5 k logic gate and 308. 5 mW @ 300 MHz for the router, traffic generator and traffic reciever.
6. The NoC development and verification platform is set up according to a new design method. The platform united with system-level simulation platform comes to an integrated NoC Development & verification environment with system analysis, functional simulation, hardware verification and performance evaluation functions.
7. According to the development trend of NoC, three kinds of topology that suitable for three-dimensional NoC are proposed. They are Hypercube-Connected Double-Loop topology, Torus Connected Petersen Graph topology, Rectangular Twisted Torus Meshes topology. And detailed analysis is made to the three topologies show that the proposed networks is a better interconnection network in the properties of topology and the performance of communication.
1.对NoC的拓扑结构进行了研究。提出了两种适合二维片上网络的拓扑结构,即广义Petersen图( Generalized Petersen , GP(2m, 1) )和网格环形(Mesh Connected-Cycles,MCC)片上网络互连结构。详细分析两种拓扑结构的性质。分别设计了两种拓扑结构的确定性路由算法,对两种拓扑结构进行了模拟分析,并与典型片上网络的mesh拓扑结构进行了比较。在综合考虑网络直径和节点度之积的情况下,GP(2m, 1)和MCC拓扑结构更适合构建片上互连网络。
2.对NoC的交换机制进行了研究。通过分析总结现有的片上网络交换技术,提出了一种缓冲式快速虫孔交换技术。对该交换机制进行了模拟分析并与典型的虚通道虫孔交换技术进行了比较,表明是一种高性能、低成本的交换技术。
3.总结片上网络路由器的基本结构和设计,设计了一种基于缓冲式虫孔交换技术的通用片上网络路由器结构,并对该路由器结构进行了详细设计、功能仿真和性能评估。结果表明该种结构的路由器是一种低延迟的片上网络路由器。
4.分析总结了系统级评估的性能指标和评估流程,建立了系统级仿真平台。该平台是一个模块化、可扩展的系统级仿真平台。
5.设计了一个网络规模为8×8、基于Mesh的片上网络系统。并用ALTERA FPGA开发板验证了其功能,其中的核心模块片上网络路由器和流量产生/接收器已经SMIC 0.13μm工艺下流片,工作频率300MHz,等效逻辑门为515.5k,在300MHz工作频率下功耗约为308.5 mW。
6.通过分析,提出了基于平台的片上网络设计方法,根据该方法建立了一个片上网络开发验证平台。该平台和系统级仿真平台结合可以形成一个集片上网络系统分析、功能仿真、硬件验证和性能评估的完整的片上网络开发验证环境。
7.针对片上网络的发展趋势,对三维片上网络拓扑结构进行了分析和探索,提出了三种适合三维片上网络的拓扑结构,即三维超立方体双环拓扑结构、三维Torus连接的Petersen图拓扑结构、三维长方形扭花环网格拓扑结构。三种拓扑结构都具有高连接度、短直径、简单的路由策略、常数节点度以及良好的可扩展性,适合构建三维片上网络。
As the microelectronics technology expanding, the traditionally idea of System-on-Chip(SoC) to integrate the whole system on a single chip which with only one CPU is in the bus architecture, unable to meet the need of multi-IP architecture development. So several research groups proposed a whole new idea of integrated circuit architecture, Network-on-Chip(NoC). The core idea of NoC is to transplant the knowledge of network technology of computer into the design of chips to systematically solve the problems of bus architecture. In NoC system, topological structures and communication paradigm are important factors in system performance. After in-depth analysis and research in key problems of NoC, we proposed some new solutions to solve the NoC problems. The solutions had been validated by modeling-simulation, software and hardware verification.
The main research results of this thesis are shown as follows:
1. Research on the topological structures of NoC. Two suitable network-on-chip topologies, that is, Generalized Petersen graph(GP(2m,1)) and the Mesh Connected-Cycles (MCC) interconnect network structures are proposed. We made detailed analysis of the character of the two topologies, designed two deterministic routing algorithms of the new topologies, and make a contrast between the GP(2m,1) and the MCC topologies and the typical mesh topology. The results show that MCC and GP(2m,1) have better performance, especially in local traffics and low loads, and lower cost.
2. Research on NoC switching mechanism. A new Buffered Express Wormhole Switching(BEWS) technology of high performance and low cost is proposed. Also a contrast is made between BEWS and typical Virtual Channel Wormhole Switching(VCWS) technology by simulation analysis,which demonstrate BEWS achieves lower latency than VCWS.
3. After making a summary of structure and design of the NoC routers, a new router structure based on BEWS for network-on-chip is designed. And detailed design, functional simulation, and performance evaluation are done to the new router structure. The results shows BEWS router has lower lantency.
4. Analyzed the NoC system-level modeling simulation, summed up system-level performance evaluating process, and then analyzed and designed system-level-simulation network model and traffic model, finally set up a system-level simulation platform. The platform explores the NoC design space in an expandable way.
5. An NoC system, 64 nodes, is designed and verification with FPGA. And synthesis and layout are carried out by SMIC 0. 13μm standard CMOS process and it s hardware scale and power dissipation is 515.5 k logic gate and 308. 5 mW @ 300 MHz for the router, traffic generator and traffic reciever.
6. The NoC development and verification platform is set up according to a new design method. The platform united with system-level simulation platform comes to an integrated NoC Development & verification environment with system analysis, functional simulation, hardware verification and performance evaluation functions.
7. According to the development trend of NoC, three kinds of topology that suitable for three-dimensional NoC are proposed. They are Hypercube-Connected Double-Loop topology, Torus Connected Petersen Graph topology, Rectangular Twisted Torus Meshes topology. And detailed analysis is made to the three topologies show that the proposed networks is a better interconnection network in the properties of topology and the performance of communication.
引文
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