全速电流测试方法研究
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摘要
随着微电子技术的迅猛发展，集成电路规模的急速扩大和集成度的迅速提高，给传统的测试技术和测试方法带来了严峻的挑战。
本文首先分析了稳态电流测试方法和瞬态电流测试方法的原理、特点，并分别指出它们的不足，在此基础上研究了一种新型的测试方法——全速电流测试方法。全速电流测试方法将稳态电流测试方法和瞬态电流测试方法结合起来，利用在一段时间内输入两个交替变换的向量，通过检验其平均电流的情况，对被测电路进行测试。这种方法克服了稳态电流测试方法测试频率低、瞬态电流测试方法对测试仪要求过高等问题，它能以电路的工作频率对电路进行测试，测试结果更准确，可以检测多种类型的故障。
针对这种新型的测试方法，本文结合波形模拟器、贝叶斯优化算法实现了它的测试产生算法，并在ISCAS85’的基准电路上进行了实验。使用测试产生出来的向量通过SPICE仿真，验证了该方法的有效性。
为了进一步提高测试产生的效率，本文基于全速电流测试方法，针对开路故障类型，研究了精简目标故障点的算法。根据电路中跳变数与电路结构的关系，本文提出故障压缩、故障省略等方法，并从理论上证明了其有效性。实验结果表明，这些精简故障的方法较大幅度的精简了需要进行测试产生的目标故障数。
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。实验结果表明，优化之后测试产生算法效率有了较大的提高，并且故障覆盖率损失较小。
With the advance of 1C technology, IC's complexity and performance grow rapidly, which give much challenge to the traditional methods or techniques.
This paper presents a new test method-at-speed current testing based on analyzing the theories, characteristics and shortcomings of quiescent power supply current testing and dynamic current testing.
The method of at-speed current testing combines this two current testing methods, applies two alternative vectors to circuits under test to enable the possibility for using a slow measurement and testing at a high frequency operation. By using it, the test can be done at the operation frequency of circuits under test, therefore results of the test can be more precise and this method can detect different types of faults.
For this new method, this paper implements a test generation algorithm at gate level by means of counting only logical up-transitions based on Boolean process, and employing the Bayesian optimization algorithm, and makes some experiments on the ISCAS'85 benchmark circuit to check its validity. SPICE simulation shows that tests generated by the algorithm can be observed either by ATE or a waveform sensor even if its operation frequency is much lower than that of ICs under test. The experiment results also illustrate the feasibility of the at-speed current testing scheme.
To improve the efficiency of test generation, this paper proposes some techniques for fault collapsing, such as fault compression, fault simulation, and etc, for stuck-open faults, and their application to test generation for at-speed current testing. Experimental results show that by using the techniques, the number of faults to be tested for test generation decreases greatly.
Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm. Experiments of some examples demonstrate that the test generation efficiency is enhanced 200 times, and the fault coverage has little loss.
本文首先分析了稳态电流测试方法和瞬态电流测试方法的原理、特点，并分别指出它们的不足，在此基础上研究了一种新型的测试方法——全速电流测试方法。全速电流测试方法将稳态电流测试方法和瞬态电流测试方法结合起来，利用在一段时间内输入两个交替变换的向量，通过检验其平均电流的情况，对被测电路进行测试。这种方法克服了稳态电流测试方法测试频率低、瞬态电流测试方法对测试仪要求过高等问题，它能以电路的工作频率对电路进行测试，测试结果更准确，可以检测多种类型的故障。
针对这种新型的测试方法，本文结合波形模拟器、贝叶斯优化算法实现了它的测试产生算法，并在ISCAS85’的基准电路上进行了实验。使用测试产生出来的向量通过SPICE仿真，验证了该方法的有效性。
为了进一步提高测试产生的效率，本文基于全速电流测试方法，针对开路故障类型，研究了精简目标故障点的算法。根据电路中跳变数与电路结构的关系，本文提出故障压缩、故障省略等方法，并从理论上证明了其有效性。实验结果表明，这些精简故障的方法较大幅度的精简了需要进行测试产生的目标故障数。
结合故障精简，本文通过编码压缩、变化终止规则等方法进一步优化了全速电流测试方法的测试产生算法。实验结果表明，优化之后测试产生算法效率有了较大的提高，并且故障覆盖率损失较小。
With the advance of 1C technology, IC's complexity and performance grow rapidly, which give much challenge to the traditional methods or techniques.
This paper presents a new test method-at-speed current testing based on analyzing the theories, characteristics and shortcomings of quiescent power supply current testing and dynamic current testing.
The method of at-speed current testing combines this two current testing methods, applies two alternative vectors to circuits under test to enable the possibility for using a slow measurement and testing at a high frequency operation. By using it, the test can be done at the operation frequency of circuits under test, therefore results of the test can be more precise and this method can detect different types of faults.
For this new method, this paper implements a test generation algorithm at gate level by means of counting only logical up-transitions based on Boolean process, and employing the Bayesian optimization algorithm, and makes some experiments on the ISCAS'85 benchmark circuit to check its validity. SPICE simulation shows that tests generated by the algorithm can be observed either by ATE or a waveform sensor even if its operation frequency is much lower than that of ICs under test. The experiment results also illustrate the feasibility of the at-speed current testing scheme.
To improve the efficiency of test generation, this paper proposes some techniques for fault collapsing, such as fault compression, fault simulation, and etc, for stuck-open faults, and their application to test generation for at-speed current testing. Experimental results show that by using the techniques, the number of faults to be tested for test generation decreases greatly.
Besides fault collapsing, this paper also proposes some techniques, such as code collapsing, change of the ending rules to optimizing the test generation algorithm. Experiments of some examples demonstrate that the test generation efficiency is enhanced 200 times, and the fault coverage has little loss.
引文
[1] 杨士元．数字系统的故障诊断与可靠性设计．第二版．北京：清华大学出版社，2000，1-3，6-7，90-92
[2] J.P.Roth. Diagnosis of automata failures: a calculus and a method. IBM Journal of Research and Development, 1966, 10(4):278-291
[3] P.Goel. An implicit enumeration algorithm to generate tests for combinational logic circuits. 1981, IEEE Trans. On Computers, 30(3):215-222
[4] H.Fujiwara, T.Shimono. On the acceleration of test generation algorithms. IEEE Trans. On computers, 1983, 32(12):1137-1144
[5] 魏道政．产生功能级数字电路测试码的一种算法——主路径敏化法．计算机学报，1982，5(2)：125-139
[6] 梁页伟，杨志娟，石茵，魏道政．对数字电路扇出的影响和造成困难的分析．计算机学报，2000，23(3)：311-317
[7] 盛运焕，曾芷德．功能块级大型数字电路测试生成的G-F二值算法．计算机学报，1983，6(1)：32-41
[8] Min Y. Boolean process—An analytial approach to circuit representation. In: Proc IEEE Third Asian Test Symposium, Japan, 1994, 249-254.
[9] 闵应骅，李忠诚，赵著行．boole过程论．中国科学(E辑)，1996，26(6)：541-548
[10] R.C.Aitken. Diagnosis of Leakage Faults with I_(DDQ). Journal of Electronic Testing :Theory and Applications,1992,3(4):367-375
[11] S.Chakravarty, M.Liu. Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. In: Proc. of the 29th Design Automation Conf., Anaheim, USA, 1992,353-356
[12] Keshavarzi Ali, Tschanz James W, Narendra Siva, et al. Leakage and Process Variation Effects in Current .Testing on Future CMOS Circuits. IEEE Design and Test of Computers, 2002,19(5):36-43
[13] 冯建华，孙义和．CMOS电路I_(DDQ)测试方法研究与进展．见：2000年全国测试学术会议论文集，北京：电子测试杂志社，2000，114-118
[14] S.P..Athan, D.L.Landis, S.A.Al-Arian. A Novel Built-In Current Sensor for IDDQ Testing of Deep Submicron CMOS Ics. In: Proc. of the 14th VLSI Test Symp., Princeton, USA, 1996,112-117
[15] Su S.T, Makki R.Z, Nagle T. Transient power supply current monitoring-A new test method for CMOS VLSI circuits. Journal of Electronic Tesing: Theory and Applications, 1995, 6(1): 23-44
[16] Y.Min, Z.Zhao and Z.Li. IDDT Testing. IEEE 6th Asian Test Symposium, Akita, Japan, 1997, 378-383.
[17] Michael L.Bushnell, Vishwani D.Agrawal. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. USA:Kluwer Academic Publishers, 2000:465-485
[18] Yervant Zorian. System-Chip Test Strategies. ln:Proe.of the 35th Design Automation Conference. San Jose, California, USA, 1998,752-757
[19] Michael L.Bushnell, Vishwani D.Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, thelst edition, USA:Kluwer Academic Publidhers, 2000, 60-78
[20] G.R.Case. Analysis of Actual Fault Mechanisms in CMOS Logic Gates. In: Proe. of the 13th Design Automation Conf., 1976, 265-270
[21] P.Nigh,W.Needham, K.Butler, et al. An Experimental Study Comparing the Relative Effectiveness of Functional, Scan,IDDQ, and Delay Fault Testing. In: Proe. of the 15th VLSI Test Symp., Monterey, CA, 1997,459-464
[22] S.Chakravaty, V.p.Dabholkar. Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Applieaion. In: Proc. of IEEE Third Asian Test Symposium(ATS'94), Japan, 1994, 324-329
[23] S.wang, S.K.Gupta. ATPG for.Heat Dissipation Minimization During Test Application. IEEE Trans. On Computers, 1998, 47(2):256-262
[24] R.X.Gu, M.I.Elmasry. Power dissipation analysis and optimization of deep submieron CMOS digital circuits. IEEE Journal on Solid State Circuits, 1996, 31(5):490-496
[25] Khurram Muhammad, Kaushik Roy. Fault Detection and Location Using I_(DD)Waveform Analysis. IEEE Design and Test of Computers, 2001, 18(1):42-49
[26] W.Mao,R.k.Gulatl. Quietest: A methodology for selecting I_(DDQ) test selector. In:Proc.Int. Test.Conf., Baltimore, USA, 1992,770-777
[27] J.M.Soden, C.F,Hawkins, R.K.Gulati et al. I_(DDQ) Testing:A Review. Journal of Electronic Testing :Theory and Applications, 1992, 3(4):5-17
[28] M.J.Riezenman. Wanlass's CMOS Circuit. IEEE Spectrum, 1991, 28(5):44
[29] F.M.Wanlass, C.T.Sah. Nanowatt Logic Using Field-Effect Metal-Oxide Semi-conductor Triodes. In:Proc. of the Solid State Circuits Conf., 1963,32-33
[30] T.W.Williams, R.H.Dennard, B.Kapur, et al. I_(DDQ) Test: Sensitivity Analysis of Scaling. In: Proc. of the International Test Conf., Washington. DC, 1996,786-792
[31] Swarup Bhunia, Kaushik Roy, Segura J. A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization. Design Automation Conference, New Orleans, LA, USA, 2002,361-366
[32] 邝继顺，朱启建，张大方，闵应骅．一种用于动态电流测试的故障模拟算法．见：第九届全国容错计算学术会议论文集．长沙：国舫科技大学出版社，2001，242-246
[33] 朱启建，邝继顺，张大方．一种动态电流测试产生方法的SPICE模拟验证．电子学报，2002，30(8)：1163-1167
[34] Kuang Jishun, You Zhiqiang, Zhu Qijian, et al. I_(DDT): Fundamentals and Test Generation. Journal ofComputer Science and Technology, 2002,18(3):299-307.
[35] 李华伟．基于RTL行为模型的测试产生及时延测试方法：[中科院计算所博士学位论文]．北京：中科院计算所，2001，86-104
[36] Soeleman H, Roy K, Chou Tan-Li. Estimating Circuit Activity in Combinational CMOS Digital Circuit. IEEE Design & Test of computers, 2000,17(3) :112-119.
[37] Li L., Yu Xiaoyang, et al. A Waveform Simulator Based on Boolean Process, In:Proc IEEE 9th Asian Test Symposium, Taipei, Taiwan,2000: 145-150
[38] Lilian Li, Y.Min, Integrity of Waveform Simulation. In:Proc. CAD/Graphics'2001, Kunming, China, 2001, 630-634.
[39] 李立健，闵应骅．基于布尔过程的组合电路波形模拟．计算机辅助设计与图形学学报，2001，13(3)：242-246．
[40] Heckerman D, Geiger D, Chickering D. Learn Bayesian network: The Combination of Knowledge and Statistical Data . Machine learning, 1995, 20(5): 197-243
[41] Pelikan M et al. A Survey of Optimization by Building and Using Probabilistic Models. IlliGAL Report No. 99018, Illinois Genetic Algorithm Laboratory, University of Illinois at Urbana-Champaign.
[42] 刘勇，康立山，陈毓屏．非数值并行算法(第二册)——遗传算法．北京：科学出版社，1995，1-14
[43] Pelikan M, Bayesian Optimization Algorithm with Decision Graphs in C++, version 1.1 http://www-illigal.ge.uiuc.edu/sourcecd.html, 2001-9
[44] 邢文训，谢金星．现代优化计算方法．第一版．北京：清华大学出版社，1999，140-192
[45] 尤志强，牛小燕，闵应骅等，平均瞬态电流测试向量产生方法的研究，第二届中国测试学术会议论文集．上海：同济大学出版社，2001，417-422
[2] J.P.Roth. Diagnosis of automata failures: a calculus and a method. IBM Journal of Research and Development, 1966, 10(4):278-291
[3] P.Goel. An implicit enumeration algorithm to generate tests for combinational logic circuits. 1981, IEEE Trans. On Computers, 30(3):215-222
[4] H.Fujiwara, T.Shimono. On the acceleration of test generation algorithms. IEEE Trans. On computers, 1983, 32(12):1137-1144
[5] 魏道政．产生功能级数字电路测试码的一种算法——主路径敏化法．计算机学报，1982，5(2)：125-139
[6] 梁页伟，杨志娟，石茵，魏道政．对数字电路扇出的影响和造成困难的分析．计算机学报，2000，23(3)：311-317
[7] 盛运焕，曾芷德．功能块级大型数字电路测试生成的G-F二值算法．计算机学报，1983，6(1)：32-41
[8] Min Y. Boolean process—An analytial approach to circuit representation. In: Proc IEEE Third Asian Test Symposium, Japan, 1994, 249-254.
[9] 闵应骅，李忠诚，赵著行．boole过程论．中国科学(E辑)，1996，26(6)：541-548
[10] R.C.Aitken. Diagnosis of Leakage Faults with I_(DDQ). Journal of Electronic Testing :Theory and Applications,1992,3(4):367-375
[11] S.Chakravarty, M.Liu. Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. In: Proc. of the 29th Design Automation Conf., Anaheim, USA, 1992,353-356
[12] Keshavarzi Ali, Tschanz James W, Narendra Siva, et al. Leakage and Process Variation Effects in Current .Testing on Future CMOS Circuits. IEEE Design and Test of Computers, 2002,19(5):36-43
[13] 冯建华，孙义和．CMOS电路I_(DDQ)测试方法研究与进展．见：2000年全国测试学术会议论文集，北京：电子测试杂志社，2000，114-118
[14] S.P..Athan, D.L.Landis, S.A.Al-Arian. A Novel Built-In Current Sensor for IDDQ Testing of Deep Submicron CMOS Ics. In: Proc. of the 14th VLSI Test Symp., Princeton, USA, 1996,112-117
[15] Su S.T, Makki R.Z, Nagle T. Transient power supply current monitoring-A new test method for CMOS VLSI circuits. Journal of Electronic Tesing: Theory and Applications, 1995, 6(1): 23-44
[16] Y.Min, Z.Zhao and Z.Li. IDDT Testing. IEEE 6th Asian Test Symposium, Akita, Japan, 1997, 378-383.
[17] Michael L.Bushnell, Vishwani D.Agrawal. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits. USA:Kluwer Academic Publishers, 2000:465-485
[18] Yervant Zorian. System-Chip Test Strategies. ln:Proe.of the 35th Design Automation Conference. San Jose, California, USA, 1998,752-757
[19] Michael L.Bushnell, Vishwani D.Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, thelst edition, USA:Kluwer Academic Publidhers, 2000, 60-78
[20] G.R.Case. Analysis of Actual Fault Mechanisms in CMOS Logic Gates. In: Proe. of the 13th Design Automation Conf., 1976, 265-270
[21] P.Nigh,W.Needham, K.Butler, et al. An Experimental Study Comparing the Relative Effectiveness of Functional, Scan,IDDQ, and Delay Fault Testing. In: Proe. of the 15th VLSI Test Symp., Monterey, CA, 1997,459-464
[22] S.Chakravaty, V.p.Dabholkar. Two Techniques for Minimizing Power Dissipation in Scan Circuits During Test Applieaion. In: Proc. of IEEE Third Asian Test Symposium(ATS'94), Japan, 1994, 324-329
[23] S.wang, S.K.Gupta. ATPG for.Heat Dissipation Minimization During Test Application. IEEE Trans. On Computers, 1998, 47(2):256-262
[24] R.X.Gu, M.I.Elmasry. Power dissipation analysis and optimization of deep submieron CMOS digital circuits. IEEE Journal on Solid State Circuits, 1996, 31(5):490-496
[25] Khurram Muhammad, Kaushik Roy. Fault Detection and Location Using I_(DD)Waveform Analysis. IEEE Design and Test of Computers, 2001, 18(1):42-49
[26] W.Mao,R.k.Gulatl. Quietest: A methodology for selecting I_(DDQ) test selector. In:Proc.Int. Test.Conf., Baltimore, USA, 1992,770-777
[27] J.M.Soden, C.F,Hawkins, R.K.Gulati et al. I_(DDQ) Testing:A Review. Journal of Electronic Testing :Theory and Applications, 1992, 3(4):5-17
[28] M.J.Riezenman. Wanlass's CMOS Circuit. IEEE Spectrum, 1991, 28(5):44
[29] F.M.Wanlass, C.T.Sah. Nanowatt Logic Using Field-Effect Metal-Oxide Semi-conductor Triodes. In:Proc. of the Solid State Circuits Conf., 1963,32-33
[30] T.W.Williams, R.H.Dennard, B.Kapur, et al. I_(DDQ) Test: Sensitivity Analysis of Scaling. In: Proc. of the International Test Conf., Washington. DC, 1996,786-792
[31] Swarup Bhunia, Kaushik Roy, Segura J. A Novel Wavelet Transform Based Transient Current Analysis for Fault Detection and Localization. Design Automation Conference, New Orleans, LA, USA, 2002,361-366
[32] 邝继顺，朱启建，张大方，闵应骅．一种用于动态电流测试的故障模拟算法．见：第九届全国容错计算学术会议论文集．长沙：国舫科技大学出版社，2001，242-246
[33] 朱启建，邝继顺，张大方．一种动态电流测试产生方法的SPICE模拟验证．电子学报，2002，30(8)：1163-1167
[34] Kuang Jishun, You Zhiqiang, Zhu Qijian, et al. I_(DDT): Fundamentals and Test Generation. Journal ofComputer Science and Technology, 2002,18(3):299-307.
[35] 李华伟．基于RTL行为模型的测试产生及时延测试方法：[中科院计算所博士学位论文]．北京：中科院计算所，2001，86-104
[36] Soeleman H, Roy K, Chou Tan-Li. Estimating Circuit Activity in Combinational CMOS Digital Circuit. IEEE Design & Test of computers, 2000,17(3) :112-119.
[37] Li L., Yu Xiaoyang, et al. A Waveform Simulator Based on Boolean Process, In:Proc IEEE 9th Asian Test Symposium, Taipei, Taiwan,2000: 145-150
[38] Lilian Li, Y.Min, Integrity of Waveform Simulation. In:Proc. CAD/Graphics'2001, Kunming, China, 2001, 630-634.
[39] 李立健，闵应骅．基于布尔过程的组合电路波形模拟．计算机辅助设计与图形学学报，2001，13(3)：242-246．
[40] Heckerman D, Geiger D, Chickering D. Learn Bayesian network: The Combination of Knowledge and Statistical Data . Machine learning, 1995, 20(5): 197-243
[41] Pelikan M et al. A Survey of Optimization by Building and Using Probabilistic Models. IlliGAL Report No. 99018, Illinois Genetic Algorithm Laboratory, University of Illinois at Urbana-Champaign.
[42] 刘勇，康立山，陈毓屏．非数值并行算法(第二册)——遗传算法．北京：科学出版社，1995，1-14
[43] Pelikan M, Bayesian Optimization Algorithm with Decision Graphs in C++, version 1.1 http://www-illigal.ge.uiuc.edu/sourcecd.html, 2001-9
[44] 邢文训，谢金星．现代优化计算方法．第一版．北京：清华大学出版社，1999，140-192
[45] 尤志强，牛小燕，闵应骅等，平均瞬态电流测试向量产生方法的研究，第二届中国测试学术会议论文集．上海：同济大学出版社，2001，417-422