VLSI的高层次综合方法研究
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摘要
芯片设计的高速化和复杂化对VLSI基础理论和设计方法提出了新的挑战。以超深亚微米和纳米工艺及IP核重用为基础的系统芯片是VLSI的发展趋势。传统的设计方法已经难以应付，出现了许多新的设计技术，如有效的高层次综合技术、验证技术及纳米工艺带来的一系列关键技术等。高层次综合是连接系统行为和结构之间的纽带，它能够缩短设计、布局和验证的时间。高层次综合阶段对电路功耗有巨大的优化空间，而物理设计阶段的功耗优化空间则急剧减少。本文就高层次综合中的调度、分配和多电压低功耗设计等问题展开研究，主要工作如下：
1)提出了基于遗传算法与蚂蚁算法相融合的时间约束和资源约束下的高层次调度方法。在充分研究遗传算法和蚂蚁算法独立解决约束条件下的高层次调度问题的基础上，提出了遗传算法的编码方案、交叉算子、变异算子和评估函数及蚂蚁算法的信息素更新规则，并讨论了两个算法之间的动态切换条件。当遗传算法的子代进化率低于事先设定的最小子代进化率或超过最大迭代次数时，结束遗传算法，切换到蚂蚁算法，并由遗传算法得到的优化解产生蚂蚁算法的初始信息素分布。这样避免了蚂蚁算法在初期由于信息素匮乏而做的大量盲目搜索，提高了算法的效率。实验结果表明，与遗传算法和蚂蚁算法相比，本文资源约束的调度方法能明显减少调度长度，本文时间约束的调度方法能明显减少所用资源总数目。
2)在充分研究复杂高层次数据流特性的基础上，提出一种适合高层次复杂数据流分解和设计空间搜索的多项式新模型K~*TDG。首先根据复杂数据流多项式中各参数之间的关系，对TDG中的边权值重新进行定义。然后讨论了K~*TDG模型的两种基本运算：加法和乘法。K~*TDG模型充分利用了TDG模型的思想，克服了TDG模型的缺点。在此基础上，借助于Maple中的Simplify函数和Factor函数，提出复杂数据流分解匹配算法。在此过程中定义关于面积和关键路径时延的代价函数，使上述过程始终向代价函数更优的方向进行。为了进一步降低算法复杂度，还提出了根据复杂元件多项式次数进行分组的策略，使每次搜索时的空间由整个设计空间变成与K~*TDG中分支次数相等的元件组成的局部空间。实验结果表明，在保持面积和延迟近优的前提下，本文方法能明显缩小设计空间。
3)提出了基于网络流的多电压高层次低功耗设计方法。定义了一种新的系统功耗模型，同时考虑了功能单元功耗、互连功耗和电压转换功耗。首先进行单电压高层次综合，然后迭代地对单电压高层次综合结果进行局部多电压调度和分配调整。只有当某个操作与其前驱节点或后继节点有分配到同一电压簇器件的可能时，才执行该调整。提取每次迭代时需要调整的网络流子图，对该子图运行最小费用最大流增量算法。该方法充分利用前面迭代中得到的优化解，避免了对整个网络流的重复计算，节省了大量时间。最后，在讨论电路拓扑结构的基础上提出了一种门控填充值算法，能进一步减少电路设计中的伪开关跳变功耗。实验结果表明，本文方法对电路的互连功耗，电平转换功耗和总功耗均有明显的优化。
The high-speed and complexity of chip design put forward new challenges to thefundamental theories and design methods of VLSI (Very Large Scale Integration).SoC (system on chip), based onthe technology of VDSM (very deep submicron),nanometer and IP (intelligent property) core reuse, is the main development trend ofVLSI. However it is difficult for traditional design methods to handle such problems.Therefore many new design techniques have emerged, such as efficient high levelsynthesis, verification technology and series of key technologies brought about bynanometer technology. Among them, high level synthesis (HLS) bridges systembehaviors and system architectures. HLS can shorten time of design, layout andverification. There is huge optimization space of power dissipation at the stage ofHLS; however the optimization space of power dissipation is smaller at the stage ofphysical design. Scheduling, allocation and multi-voltages low power design of HLSare studied in this paper. The major contributions are as follows:
1) The high level scheduling methods based on the combination of geneticalgorithm and ant algorithm with latency constraints and resource constraints areproposed. After an abundant investigation of the capabilities of genetic algorithm andant algorithm to solve high level scheduling independently, the coding scheme,crosstalk operator, mutation operator, evolution function of genetic algorithm and thepheromone updating rules of ant algorithm are presented. And the dynamic switchingconditions of genetic algorithm and ant algorithm are also explored: when thesub-generation evolution ratio is less than the min sub-generation evolution ratio setbeforehand or the iteration times exceed the given maximum iteration times ofgenetic algorithm, genetic algorithm terminates and switches to ant algorithm. Theinitial pheromone distribution of ant algorithm can be generated by theoptimizational solutions of genetic algorithm, thus many blind searches in the earlystage of ant algorithm for deficiency of pheromone can be avoided, and the algorithmefficiency can also be improved greatly. Experimental results indicate that, the resource constrained scheduling method in this paper can reduce scheduling lengthand the latency constrained scheduling method in this paper can reduce the totalresource numbers, compared with genetic algorithm and ant algorithm.
2) A new polynomial model K*TDG is presented after an intensive study on thecharacteristic of complex high level data flow, which is suitable for complex highlevel data flow decomposition and design space exploration. First, the arc weights ofTDG are redefined according to the relationship between the parameters of complexdata flow polynomial. Then two basic operations of K*TDG are discussed: additionand multiplication. The new model K*TDG makes the best of model TDG fully, andovercomes the disadvantages of TDG as well. On this basis, a complex data flowdecomposition method is proposed by applying the Simplify function and Factorfunction in Maple. A cost function regarding area and critical path delay is defined inthis process in order to move the decomposition to a more optimal direction. In orderto reduce the algorithm complexity further, a grouping strategy based on the degreesof component polynomials is proposed. The search space is transformed from thewhole space into the local one that share the same degree with the K*TDG branch ineach iteration. Experimental results indicate that the method in this paper can reducesearch space greatly on the precondition of keeping area and delaying approximateoptimal.
3) A high level low power multi-voltages design method based on network flow isdeveloped. A new system power dissipation model isdefined, in which function unitpower, interconnection power and voltages converting power are taken intoconsideration. Single voltage high level synthesis methods run first, and thenmulti-voltages local adjustments are done iteratively on the single voltage high levelsynthesis results. Only when one operation node can be allocated to the componentwhich has the same voltage cluster with its previous operation nodes or successoroperation nodes, can the adjustment be executed. In the following, the network flowsub-graph needed to adjust is extracted from the previous network flow graph andthe min-cost max-flow incremental algorithm is run on it. At last, the topologystructure used in this paper is discussed. A gated filler value computation algorithm is proposed at last to further reduce the power dissipation of spurious switchingactivity. Experimental results indicate that, the interconnection power, voltageconverting power and total power can be optimized greatly by using the methods.
1)提出了基于遗传算法与蚂蚁算法相融合的时间约束和资源约束下的高层次调度方法。在充分研究遗传算法和蚂蚁算法独立解决约束条件下的高层次调度问题的基础上，提出了遗传算法的编码方案、交叉算子、变异算子和评估函数及蚂蚁算法的信息素更新规则，并讨论了两个算法之间的动态切换条件。当遗传算法的子代进化率低于事先设定的最小子代进化率或超过最大迭代次数时，结束遗传算法，切换到蚂蚁算法，并由遗传算法得到的优化解产生蚂蚁算法的初始信息素分布。这样避免了蚂蚁算法在初期由于信息素匮乏而做的大量盲目搜索，提高了算法的效率。实验结果表明，与遗传算法和蚂蚁算法相比，本文资源约束的调度方法能明显减少调度长度，本文时间约束的调度方法能明显减少所用资源总数目。
2)在充分研究复杂高层次数据流特性的基础上，提出一种适合高层次复杂数据流分解和设计空间搜索的多项式新模型K~*TDG。首先根据复杂数据流多项式中各参数之间的关系，对TDG中的边权值重新进行定义。然后讨论了K~*TDG模型的两种基本运算：加法和乘法。K~*TDG模型充分利用了TDG模型的思想，克服了TDG模型的缺点。在此基础上，借助于Maple中的Simplify函数和Factor函数，提出复杂数据流分解匹配算法。在此过程中定义关于面积和关键路径时延的代价函数，使上述过程始终向代价函数更优的方向进行。为了进一步降低算法复杂度，还提出了根据复杂元件多项式次数进行分组的策略，使每次搜索时的空间由整个设计空间变成与K~*TDG中分支次数相等的元件组成的局部空间。实验结果表明，在保持面积和延迟近优的前提下，本文方法能明显缩小设计空间。
3)提出了基于网络流的多电压高层次低功耗设计方法。定义了一种新的系统功耗模型，同时考虑了功能单元功耗、互连功耗和电压转换功耗。首先进行单电压高层次综合，然后迭代地对单电压高层次综合结果进行局部多电压调度和分配调整。只有当某个操作与其前驱节点或后继节点有分配到同一电压簇器件的可能时，才执行该调整。提取每次迭代时需要调整的网络流子图，对该子图运行最小费用最大流增量算法。该方法充分利用前面迭代中得到的优化解，避免了对整个网络流的重复计算，节省了大量时间。最后，在讨论电路拓扑结构的基础上提出了一种门控填充值算法，能进一步减少电路设计中的伪开关跳变功耗。实验结果表明，本文方法对电路的互连功耗，电平转换功耗和总功耗均有明显的优化。
The high-speed and complexity of chip design put forward new challenges to thefundamental theories and design methods of VLSI (Very Large Scale Integration).SoC (system on chip), based onthe technology of VDSM (very deep submicron),nanometer and IP (intelligent property) core reuse, is the main development trend ofVLSI. However it is difficult for traditional design methods to handle such problems.Therefore many new design techniques have emerged, such as efficient high levelsynthesis, verification technology and series of key technologies brought about bynanometer technology. Among them, high level synthesis (HLS) bridges systembehaviors and system architectures. HLS can shorten time of design, layout andverification. There is huge optimization space of power dissipation at the stage ofHLS; however the optimization space of power dissipation is smaller at the stage ofphysical design. Scheduling, allocation and multi-voltages low power design of HLSare studied in this paper. The major contributions are as follows:
1) The high level scheduling methods based on the combination of geneticalgorithm and ant algorithm with latency constraints and resource constraints areproposed. After an abundant investigation of the capabilities of genetic algorithm andant algorithm to solve high level scheduling independently, the coding scheme,crosstalk operator, mutation operator, evolution function of genetic algorithm and thepheromone updating rules of ant algorithm are presented. And the dynamic switchingconditions of genetic algorithm and ant algorithm are also explored: when thesub-generation evolution ratio is less than the min sub-generation evolution ratio setbeforehand or the iteration times exceed the given maximum iteration times ofgenetic algorithm, genetic algorithm terminates and switches to ant algorithm. Theinitial pheromone distribution of ant algorithm can be generated by theoptimizational solutions of genetic algorithm, thus many blind searches in the earlystage of ant algorithm for deficiency of pheromone can be avoided, and the algorithmefficiency can also be improved greatly. Experimental results indicate that, the resource constrained scheduling method in this paper can reduce scheduling lengthand the latency constrained scheduling method in this paper can reduce the totalresource numbers, compared with genetic algorithm and ant algorithm.
2) A new polynomial model K*TDG is presented after an intensive study on thecharacteristic of complex high level data flow, which is suitable for complex highlevel data flow decomposition and design space exploration. First, the arc weights ofTDG are redefined according to the relationship between the parameters of complexdata flow polynomial. Then two basic operations of K*TDG are discussed: additionand multiplication. The new model K*TDG makes the best of model TDG fully, andovercomes the disadvantages of TDG as well. On this basis, a complex data flowdecomposition method is proposed by applying the Simplify function and Factorfunction in Maple. A cost function regarding area and critical path delay is defined inthis process in order to move the decomposition to a more optimal direction. In orderto reduce the algorithm complexity further, a grouping strategy based on the degreesof component polynomials is proposed. The search space is transformed from thewhole space into the local one that share the same degree with the K*TDG branch ineach iteration. Experimental results indicate that the method in this paper can reducesearch space greatly on the precondition of keeping area and delaying approximateoptimal.
3) A high level low power multi-voltages design method based on network flow isdeveloped. A new system power dissipation model isdefined, in which function unitpower, interconnection power and voltages converting power are taken intoconsideration. Single voltage high level synthesis methods run first, and thenmulti-voltages local adjustments are done iteratively on the single voltage high levelsynthesis results. Only when one operation node can be allocated to the componentwhich has the same voltage cluster with its previous operation nodes or successoroperation nodes, can the adjustment be executed. In the following, the network flowsub-graph needed to adjust is extracted from the previous network flow graph andthe min-cost max-flow incremental algorithm is run on it. At last, the topologystructure used in this paper is discussed. A gated filler value computation algorithm is proposed at last to further reduce the power dissipation of spurious switchingactivity. Experimental results indicate that, the interconnection power, voltageconverting power and total power can be optimized greatly by using the methods.
引文
[1] Taek K J. CAD for nanometer silicon design challenges and success. IEEE Transactions on Very Large Scale Integration Systems, 2004, 12(11): 1132-1147P
[2] The International Technology Roadmap for Semiconductors. http://public.itrs.net./[2008-03-12]
[3] Wakabayashi K. C-based behavioral synthesis and verification analysis on industrial design examples. Proceedings of the Asia South Pacific Design Automation Conference, Yokohama, Japan, 2004:344-348P
[4] 边计年，薛宏熙，苏明，吴为民．数字系统设计自动化(第二版)．清华大学出版社．2005：265-276页
[5] Micheli G D. Synthesis and optimization of digital circuits. McGrow-Hill, Inc,1994:163-166P
[6] Sllame A M and Drabek V. An efficient list-based scheduling algorithm for high-level synthesis. Proceedings of the Europ Micro Symposium on Digital System Design, Dortmund, Germany, 2002:316-323P
[7] Paulin P G and Knight J P. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989, 8(6): 661-679P
[8] 袁小龙，沈绪榜．一种基于路径的调度算法．计算机研究与发展．1998，135(13)：279-282页
[9] Memik S O, Kastner R, Bozorgzadeh E and Sarrafzadeh M. A scheduling algorithm for optimization and early planning in high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 2005, 10(1):33-57P
[10] 李鑫，胡铭曾，季振洲．基于硬件实现的用于定长匹配的PATRICIA算法．计算机研究与发展．2005，42(6)：951-957页
[11] 许俊娟，程旭．时间约束调度中功能单元的下限估算．计算机辅助设计与图形学学报．2006，118(14)：532-537页
[12] 刘志鹏，边计年，赵震．高层次综合中基于整数线性规划模型的多目标功耗优化算法．计算机辅助设计与图形学学报．2007，19(8)：966-972页
[13] 唐立山等．非数值并行算法(第一册)--模拟退火算法．科学出版社．2000：1-6页
[14] 吴浩扬，常炳国，朱长纯，刘君华．基于模拟退火机制的多种群并行遗传算法．软件学报．2000，11(3)：416-420页
[15] Yim J S and Kyung C M. Datapath layout optimization using genetic algorithm and simulated annealing. Proceedings of Computers and Digital Techniques,1998, 145(2):135-141P
[16] Gandomkar M, Vakilian M, Ehsan M. A combination of genetic algorithm and simulated annealing for optimal allocation in distribution networks. Canadian Conferences on Electrical and Computer Engineering, Saskatchewan, Canada,2005:645-648P
[17] Stammermann A, Helms D, Schulte M, Schulz A and Nebel W. Binding,allocation and floorplanning in low power high-level synthesis. Proceedings of International Conference on Computer Aided Design, San Jose, USA, 2003:544-550P
[18] Kruse L, Schmidt E, Jochens G, Stammermann A, Schulz A, Macii E and Nebel W. Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. IEEE Transactions on Very Large Scale Integration Systems, 2001, 9(1):3-14P
[19] Engebretsen L and Holmerin J. Towards optimal lower bounds for clique and chromatic number. Proceedings of International theoretical computer science,Elsevier, 2003:537-584P
[20] 赵天绪，马佩军，郝跃．划分IC缺陷团的聚类算法．计算机学报．2002，25(6)：661-665页
[21] 林翠琴．图的匹配设计的组合和矩阵方法．清华大学学报(自然科学版)．1999，39(10)：116-120页
[22] 张鲁峰，何连跃，李思昆．基于优化合并准则的团划分算法．电子学报．2001，29(8)：1104-1106页
[23] Lin Y L. Recent developments in high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 1997, 2(1):2-21P
[24] Banerjee N, Raychowdhury A, Bhunia S, Mahmoodi H and Roy K. Novel low-overhead operand isolation techniques for low power datapath synthesis.IEEE Transactions on Very Large Scale Integration Systems, 2006,14(9):1034-1039P
[25] 许庆平，刘明业，宋瀚涛．面向高级综合验证的数据流图提取技术研究．软件学报．1999，10(5)：508-510页
[26] 石峰，刘明业．多级流水线结构高层次VHDL语言行为模型的研究．计算机辅助设计与图形学学报．1999，11(4)：320-323页
[27] 马聪，王作建，刘明业．VHDL高级综合系统中多层次、多目标工艺映射策略及其实现．计算机学报．1999，22(9)：975-980页
[28] 袁小龙，沈绪榜．一种新的操作调度算法．计算机学报．1997，20(3)：193-197页
[29] 袁小龙，沈绪榜．一种新的寄存器分配算法．计算机学报．1998，21(增刊)：68-72页
[30] 王磊，魏少军．一种同时实现算子调度与数据流图划分的高层次综合算法．半导体学报．2004，25(4)：383-387页
[31] 王磊，魏少军．优化寄存器需求的资源约束调度算法．计算机辅助设计与图形学学报．2004，16(19)：1220-1224页
[32] 王云峰，边计年，周强，洪先龙．高层次综合和布图规划相结合的解空间分析．计算机辅助设计与图形学学报．2006，18(10)：1478-1483页
[33] 边计年．底层相关的VLSI高层次设计策略．计算机辅助设计与图形学学报．2000，12(11)：827-829页
[34] Mandal C A, Chakrabarti P P and Ghose S. Allocation and binding in data path synthesis using a genetic algorithm approach. Proceedings of the International Conference on Very Large Scale Integration Design, Bangalore, India,1996:122-125P
[35] Grewal G W and Wilson T C. An enhanced genetic solution for scheduling,module allocation, and binding in VLSI design. Proceedings of the International Conference on Very Large Scale Integration Design, Hyderabad, India, 1997:51-56P
[36] Landwehr B. A genetic algorithm based approach for multi-objective data-flow graph optimization. Proceedings of the Asia and South Pacific Design Automation Conference, Hong Kong, China, 1999:355-358P
[37] Banaiyan A, Esmaeelzadeh H and Safari S. Co-evolutionary scheduling and mapping for high-level test synthesis. Proceedings of the International Conference on Enterprise Information Systems, Islarnabad, Pakistan,2006:269-273
[38] Grewal G, O'Cleirigh M and Wineberg M. An evolutionary approach to behavioral-level synthesis. Proceedings of the Conference on Evolutionary Computation, Canberra, Australia, 2003:264-272P
[39] Torbey E and Knight J. High-level synthesis of digital circuits using genetic algorithms. Proceedings of the Conference on Evolutionary Computation,Piscateway, New Jersy, 1998:224-229P
[40] Vyas K and Srinivas K. A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Transactions on evolutionary computation, 2006, 10(3):213-229P
[41] Torbey E and Knight J. Performing scheduling and storage optimization simultaneously using genetic algorithms. Proceedings of the Midwest Symposium on Circuits Systems, Indiana, USA, 1998:284-287P
[42] Ascia G; Catania V and Palesi M. A GA-based design space exploration framework for parameterized system-on-a-chip platform. IEEE Transactions on evaluationary computation, 2004, 8(4):329-346P
[43] Jackson D. Evolution of processor microcode. IEEE Transactions on Evaluationary Computation, 2005, 9(1): 44-54P
[44] Wang L, Wei S J. Interconnect reuse based resource allocation with GA approach. Proceedings of the International Conference on Application Specific Integrated Circuits, Beijing, China, 2003:290-293P
[45] 王磊，粟雅娟，魏少军．一种使用遗传算法在高层次综合中完成互连优化的方法．半导体学报．2004，25(5)：607-612页
[46] 谢晓锋，李钊，阮骏，姚依，张文俊，杨之廉：应用遗传算法实现MOS器件综合．半导体学报．2002，23(1)：95-101页
[47] Small C. Shrinking devices put the squeeze on system packaging. Electronics Design News, 1994, 39(4):41-46P
[48] Warwick C A and Ourmazd A. Trends and limits in monolithic integration by increasing the die area. IEEE Transactions on Semiconductor Manufacturing,1993, 6(3): 284-289P
[49] Weste N H E and Eshraghian K. Principles of CMOS VLSI design (a systems perspective, 2nd edition). Addison-Wesley, 1993:33-45P
[50] Pollack F. New microarchitecture challenges in the coming generations of CMOS process technologies. Politeonica de Catalunya, Intel Corporation Micro32 Conference Keynote, 1999:19-25P
[51] Khouri K S and Jha N K. Leakage power analysis and reduction during behavioral synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2002, 10(6):876-885P
[52] Kumar A, Bayoumi M and Cherabuddi R. Minimizing switchings of the function traits through binding for low power. Proceedings of the International Symposium on Circuits and Systems, Orlando, USA, 1999:66-69P
[53] Liu Z P, Bian J N and Huang J F. Fast and efficiently binding of functional units for low power design. Proceedings of the Conference on Application Specific Integrated Circuits, Shanghai, China, 2005:10-13P
[54] Srikantam V K, Ranganathan N and Srinivasan S. CREAM: combined register and module assignment with floorplanning for low power datapath synthesis.Proceedings of the International Conference on Very Large Scale Integration Design, Calcutta, India, 2000: 228-233P
[55] Liu Z P, Bian J N and Zhou Q. Interconnect power optimization based on the integration of high-level synthesis and floorplanning. Proceedings of the International Conferences on Communications, Circuits and Systems, Guilin, China, 2006:2286-2290P
[56] Prabhakaran P and Banerjee P. Simultaneous scheduling, binding and floorplanning in high-level synthesis. Proceedings of the International Conference on Very Large Scale Integration Design, San Jose, USA, 1998:428-434P
[57] Mohanty S P, Ranganathan N and Chappidi S K. An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. Proceedings of the International Symposium on Circuits and Systems, Bangkok, Thailand, 2003:313-316P
[58] Mohanty S P, Ranganathan N and Chappidi S K. Simultaneous peak and average power minimization during datapath scheduling. IEEE Transactions on Circuits and Systems, 2005, 52 (6): 1157-1165P
[59] Kim K B and Lin C H. An optimal ILP model for delay time to minimize peak power and area. Proceedings of the International Workshop on System-on-Chip for Real-Time Applications, Banff, Alberta, Canada, 2005:358-362P
[60] Cheng Y K and Kang S M. An efficient method for hot-spot identification in ULSI circuits. Proceedings of the International Conference on Computer-Aided Design, San Jose, USA, 1999:124-127P
[61] Gu Z Y, Yang Y H and Wang J. TAPHS: thermal-aware unified physical-level and high-level synthesis. Proceedings of the Asia and South Pacific Conference on Design Automation Conference, Yokohama, Japan, 2006:879-885P
[62] Zhao Z, Bian J N, Liu Z P. High level synthesis with multiple supply voltages for energy and combined peak power minimization. Proceedings of the Asia Pacific Conference on Circuits and Systems, Singapore, 2006:865-869P
[63] Mukherjee R and Memik S O. An integrated approach to thermal management in high-level synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2006,14 (11):1165-1173P
[64] Kumar A and Bayoumi M. Multiple voltage-based scheduling methodology for low power in the high level synthesis. Proceedings of the IEEE International Symposium on Circuits and Systems, Orlando, Florida, USA, 1999:371-374P
[65] Manzak A and Chakrabarti C. A low power scheduling scheme with resources operating at multiple voltages. IEEE Transactions on Very Large Scale Integration Systems, 2002, 10(1): 6-14P
[66] Bullnheimer B, Hartl R F and Strauss C. A new rank-based version of the ant system: a computational study. Central European Journal for Operations Research and Economics, 1999, 7(1):25-38P
[67] Maniezzo V and Colomi A. The ant system applied to the quadratic assignment problem. IEEE Transactionss on Knowledge and Data Engineering, 1999,11 (5):769-778P
[68] Dorigo M and Gambardella L M. Ant colony system: a cooperative learning approach to the traveling salesman problem. IEEE Transactions on Evolutionary Computation, 1997, 1(1):53-66P
[69] Stutzle T and Hoos H H. MAX-MIN ant system and local search for the traveling salesman problem. Proceedings of the International Conference on Evolutionary Computation, Indianapolis, USA, 1997:309-314P
[70] 丁建立，陈增强，袁著祉．遗传算法与蚂蚁算法的融合．计算机研究与发展．2003，40(9)：1531-1536页
[71] White T, Pagurek B and Oppacher F. ASGA: improving the ant system by integration with genetic algorithms. Proceedings of the Annual Genetic Programming Conference, Morgan Kaufmann, 1998:610-617P
[72] 吴庆洪，张纪会，徐心和．具有变异特性的蚁群算法．计算机研究与发展．1999，36(10)：1240-1245页
[73] Chen M and Lu Q. A Co-evolutionary model based on dynamic combination of genetic algorithm and ant colony algorithm. Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies. Dalian, China, 2005:941-944P
[74] 许可证，赵勇．面向方案组合优化设计的混合遗传蚂蚁算法．计算机辅助设计与图形学学报．2006，18(10)：1587-1593页
[75] Li M, Wang H and Li P. Tasks mapping in multi-core based system: hybrid ACO and GA approach. Proceedings of the International Conference on Application Specific Integrated Circuits, Beijing, China, 2003:335-340P
[76] 李智，许川佩，莫玮，陈光．基于蚂蚁算法和遗传算法的同步时序电路初始化．电子学报．2003，31(8)：1276-1280页
[77] Lee Z J. A hybrid algorithm applied to traveling salesman problem. Proceedings of the International Conference on Networking, Sensing and Control, Taipei,Taiwan, 2004:237-242P
[78] 熊志辉，李思昆，陈吉华．遗传算法与蚂蚁算法动态融合的软硬件划分．软件学报．2005，16(4)：503-512页
[79] Song X Y, Zhu Y L, Yin C W and Li F M. Study on the combination of genetic algorithms and ant Colony algorithms for solving fuzzy job shop scheduling problems. Multiconference on Computational Engineering in Systems Applications, Beijing, China, 2006:1904-1909P
[80] Minato S. Streaming BDD manipulation. IEEE Transactions on Computers,2002, 51 (5):474-485P
[81] Narayan A, Jain J and Fujita M. Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for boolean functions. Proceedings of the International Conference of Computer-Aided Design, San Jose, California,USA, 1996:547-554P
[82] Lain W K C and Brayton R K. Timed boolean functions: a unified formalism for exact timing analysis. Kluwer Academic Publishers, 1994:23-41P
[83] 闵应骅，李忠诚，赵著行．Boole过程论．中国科学(E辑)．1996，26(6)：541-548页
[84] 杜振军，马光胜，冯刚．基于布尔过程论的层次化延时分析方法．计算机研究与发展．2001，38(10)：1269-1275页
[85] 杜振军．布尔过程论及其在复杂高速芯片设计自动化应用中的研究．哈尔滨工程大学博士学位论文．2003：45-93页
[86] 冯刚，马光胜，杜振军．动态串扰优化的开关盒布线．半导体学报．2005，26(2)：399-405页
[87] 冯刚，马光胜，杜振军．信号相关的串扰优化详细布线．计算机辅助设计与图形学学报．2005，17(5)：1074-1078页
[88] 冯刚．基于Boole过程的考虑互连效应的EDA方法研究．哈尔滨工程大学博士学位论文．2005：17-104页
[89] Smith J and Micheli D G Polynomial circuit models for component matching in high-level synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2001, 9(6):783-799P
[90] Smith J. Allocation and interface synthesis algorithms for component-based design. Technical Report, No. CSL-TR-00-793, 2000:58-95P
[91] Smith J and Micheli D G Polynomial methods for component matching and verification. Proceedings of the International Conference on Computer-Aided Design, San Jose, California, USA, 1998:678-685P
[92] Smith J and Micheli D G Polynomial methods for allocating complex components. Proceedings of the Design, Automation and Test in Europ, Munich,Germany, 1999:217-222P
[93] Smith J and Micheli D G A methodology for synthesis with reusable components from an arithmetic specification. Proceedings of the European Conference on Circuit Theory and Design, Stresa, Italy, 1999:1195-1198P
[94] Peymandoust A and Micheli D G. Application of symbolic computer algebra in high-level data-flow synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(9): 1154-1165P
[95] Peymandoust A and Micheli D G. Using symbolic algebra in algorithmic-level DSP synthesis. Proceedings of the Design Automation Conference, Las Vegas,USA, 2001:277-282P
[96] Peymandoust A and Micheli D G. Symbolic algebra and timing driven data-flow synthesis. Proceedings of the International Conference on Computer-Aided Design, San Jose, California, USA, 2001:300-305P
[97] Verma A K and Lenne P. Towards the automatic exploration of arithmetic-Circuit Architectures. Proceedings of the Design Automation Conference, San Francisco, California, 2006:445-450P
[98] Ciesielski M, Kalla P, Zeng Z and Rouzeyre B. Taylor expansion diagrams: a compact canonical representation with application to symbolic verification.Proceedings of the Design, Automation and Test in Europ, Paris, France,2002:285-289P
[99] Ciesielski M, kalla P and Askar S. Taylor expansion diagrams: a canonical representation for verification of data flow designs. IEEE Transactions on Computers, 2006, 55(9): 1188-1201P
[100] Fey G, Drechsler R and Ciesielski M. Algorithms for Taylor expansion diagrams. Proceedings of the International Symposium on Multiple-Valued Logic, Toronto, Canada, 2004:235-240P
[101] Gomez P D, Ren Q, Askar S and Ciesielski M. Variable ordering for Taylor expansion diagrams. Proceedings of the International High Level Design Validation and Test Workshop, California, USA, 2004:55-59P
[102] Guillot J, Boutillon E, Ren Q and Ciesielski M. Efficient factorization of DSP transforms using Taylor expansion diagrams. Proceedings of the Design,Automation and Test in Europ, Munich, Germany, 2006:754-755P
[103] Xing X W and Jong C C. Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis.Proceedings of the International Symposium on Circuits and Systems, Kobe,Japan, 2005:5645-5648P
[104] 董刚，杨银堂，柴长春．多芯片组件互连的功耗分析．计算机辅助设计与图形学学报．2005，17(8)：1809-1812页
[105] 王丽英，杨军，罗岚．SoC设计中的低功耗逻辑综合策略．电子工程师．2005，31(11)：10-12页
[106] 王玲，温东新，杨孝宗，蒋颖涛．一种基于时间限制条件的低功耗高层次设计方案．半导体学报．2005，26(2)：287-293页
[107] Wilken K, Liu J and Heffeman M. Optimal instruction scheduling using integer programming, Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, Vancouver, British Columbia, Canada, 2000:121-133P
[108] Topcuouglu H, Hariri S and Wu M Y. Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE Transactions on Parallel Distribution System, 2002, 13(3): 260-274P
[109] Heijligers M J M, Cluitmans L J M and Jess J A G. High-level synthesis scheduling and allocation using genetic algorithms. Proceedings of the Asia and South Pacific Design Automation Conference, Makuhari, Massa, Chiba,Japan, 1995:61-66P
[110] Wang G, Gong W R, DeRenzi B and Kastner R. Design space exploration using time and resource duality with the ant colony optimization. Proceedings of the Design Automation Conference, San Francisco, CA, USA,2006:451-454P
[111] Tseng C and Siewiorek D P. Automated synthesis of data paths in digital systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986, 5(3):379-395P
[112] 吴庆洪，张纪会，徐心和．具有变异特征的蚁群算法．计算机研究与发展．1999，36(10)：1240-1245页
[113] Dorigo M, Bonabeau E and Theraulaz G. Ant algorithm and stigmergy. Future Generation Computer System, 2000, 16(9): 851-871P
[114] http://express.ece.ucsb.edu/benchmark/[2007-06-15]
[115] Kaltofen E. Polynomial factorization: a success story. Proceedings of the International Symposium on Symbolic and Algebraic, Philadelphia,Pennsylvania, USA, 2003:3-4P
[116] David J and Kuck J W. The structure of computers and computations. ACM SIGARCH Computer Architecture News, 1979, 7(7):27-30P
[117] Kuck D J, Muraoka Y and Chen S C. On the number of operations simultaneously executable in fortran-like programs and their resulting speedup.IEEE Transactions on Computers, 1972, 21 (12): 1293-1310P
[118] Nicolau A and Potasman R. Incremental tree height reduction for high level synthesis. Proceedings of the Design Automation Conference, San Francisco,California, USA, 1991:770-774P
[119] Kolson D, Nicolau A and Dutt N. Integrating program transformations in the memory-based synthesis of image and video algorithms. Proceedings of the International Conference on Computer-Aided Design, San Jose, California,USA, 1994:27-30P
[120] Wang H, Nicolau A and Siu K. The strict time lower bound and optimal schedules for parallel prefix with resource constraints. IEEE Transactions on Computers, 1996, 45(11):1257-1271P
[121] Mathematica. Available: http://www.wri.com[2007-06-15]
[122] Khana F S and Perkowskib M. Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition. Theoretical Computer Science, 2006,367(3): 336-346P
[123] Brayton R, Rudell R, Sangiovanni-Vincentelli A and Wang A. MIS: a multiple-level logic optimization and the rectangular covering problem.Proceedings of the International Conference Computer-Aided Design,Anaheim, California, USA, 1987:1062-1081P
[124] Cox D, Little J and O'Shea D. Ideals, Varieties, and Algorithms. New York:Springer-Verlag, 1997:78-88P
[125] Mehra R, Guerra L M and Rabaey J M. Low-power architectural synthesis and the impact of exploiting locality. Journal of Very Large Scale Integration Signal Processing, 2005, 13(2):239-258P
[126] Chang J M and Pedram M. Energy minimization using multiple supply voltages. IEEE Transactions on Very Large Scale Integration Systems, 1997,5(4): 436-443P
[127] 运筹学教材组．运筹学(第三版)．清华大学出版社．2005：268-273页
[128] 谢政．网络算法与复杂性理论(第二版)．国防科技大学出版社．2003：113-131页
[129] 谢金星，邢文训．网络优化．清华大学出版社．2000：144-184页
[130] Mussoll E and Cortadella J. High-level synthesis techniques for reducing the activity of functional units. Proceedings of the International Symposium on Low-Power Design, California, USA, 1995:99-104P
[131] Munch M, Wurth B, Mehra R, Sproch J and Wehn N. Automating RT-level operand isolation to minimize power consumption in datapaths. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris,France, 2000:624-631P
[2] The International Technology Roadmap for Semiconductors. http://public.itrs.net./[2008-03-12]
[3] Wakabayashi K. C-based behavioral synthesis and verification analysis on industrial design examples. Proceedings of the Asia South Pacific Design Automation Conference, Yokohama, Japan, 2004:344-348P
[4] 边计年，薛宏熙，苏明，吴为民．数字系统设计自动化(第二版)．清华大学出版社．2005：265-276页
[5] Micheli G D. Synthesis and optimization of digital circuits. McGrow-Hill, Inc,1994:163-166P
[6] Sllame A M and Drabek V. An efficient list-based scheduling algorithm for high-level synthesis. Proceedings of the Europ Micro Symposium on Digital System Design, Dortmund, Germany, 2002:316-323P
[7] Paulin P G and Knight J P. Force-directed scheduling for the behavioral synthesis of ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989, 8(6): 661-679P
[8] 袁小龙，沈绪榜．一种基于路径的调度算法．计算机研究与发展．1998，135(13)：279-282页
[9] Memik S O, Kastner R, Bozorgzadeh E and Sarrafzadeh M. A scheduling algorithm for optimization and early planning in high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 2005, 10(1):33-57P
[10] 李鑫，胡铭曾，季振洲．基于硬件实现的用于定长匹配的PATRICIA算法．计算机研究与发展．2005，42(6)：951-957页
[11] 许俊娟，程旭．时间约束调度中功能单元的下限估算．计算机辅助设计与图形学学报．2006，118(14)：532-537页
[12] 刘志鹏，边计年，赵震．高层次综合中基于整数线性规划模型的多目标功耗优化算法．计算机辅助设计与图形学学报．2007，19(8)：966-972页
[13] 唐立山等．非数值并行算法(第一册)--模拟退火算法．科学出版社．2000：1-6页
[14] 吴浩扬，常炳国，朱长纯，刘君华．基于模拟退火机制的多种群并行遗传算法．软件学报．2000，11(3)：416-420页
[15] Yim J S and Kyung C M. Datapath layout optimization using genetic algorithm and simulated annealing. Proceedings of Computers and Digital Techniques,1998, 145(2):135-141P
[16] Gandomkar M, Vakilian M, Ehsan M. A combination of genetic algorithm and simulated annealing for optimal allocation in distribution networks. Canadian Conferences on Electrical and Computer Engineering, Saskatchewan, Canada,2005:645-648P
[17] Stammermann A, Helms D, Schulte M, Schulz A and Nebel W. Binding,allocation and floorplanning in low power high-level synthesis. Proceedings of International Conference on Computer Aided Design, San Jose, USA, 2003:544-550P
[18] Kruse L, Schmidt E, Jochens G, Stammermann A, Schulz A, Macii E and Nebel W. Estimation of lower and upper bounds on the power consumption from scheduled data flow graphs. IEEE Transactions on Very Large Scale Integration Systems, 2001, 9(1):3-14P
[19] Engebretsen L and Holmerin J. Towards optimal lower bounds for clique and chromatic number. Proceedings of International theoretical computer science,Elsevier, 2003:537-584P
[20] 赵天绪，马佩军，郝跃．划分IC缺陷团的聚类算法．计算机学报．2002，25(6)：661-665页
[21] 林翠琴．图的匹配设计的组合和矩阵方法．清华大学学报(自然科学版)．1999，39(10)：116-120页
[22] 张鲁峰，何连跃，李思昆．基于优化合并准则的团划分算法．电子学报．2001，29(8)：1104-1106页
[23] Lin Y L. Recent developments in high-level synthesis. ACM Transactions on Design Automation of Electronic Systems, 1997, 2(1):2-21P
[24] Banerjee N, Raychowdhury A, Bhunia S, Mahmoodi H and Roy K. Novel low-overhead operand isolation techniques for low power datapath synthesis.IEEE Transactions on Very Large Scale Integration Systems, 2006,14(9):1034-1039P
[25] 许庆平，刘明业，宋瀚涛．面向高级综合验证的数据流图提取技术研究．软件学报．1999，10(5)：508-510页
[26] 石峰，刘明业．多级流水线结构高层次VHDL语言行为模型的研究．计算机辅助设计与图形学学报．1999，11(4)：320-323页
[27] 马聪，王作建，刘明业．VHDL高级综合系统中多层次、多目标工艺映射策略及其实现．计算机学报．1999，22(9)：975-980页
[28] 袁小龙，沈绪榜．一种新的操作调度算法．计算机学报．1997，20(3)：193-197页
[29] 袁小龙，沈绪榜．一种新的寄存器分配算法．计算机学报．1998，21(增刊)：68-72页
[30] 王磊，魏少军．一种同时实现算子调度与数据流图划分的高层次综合算法．半导体学报．2004，25(4)：383-387页
[31] 王磊，魏少军．优化寄存器需求的资源约束调度算法．计算机辅助设计与图形学学报．2004，16(19)：1220-1224页
[32] 王云峰，边计年，周强，洪先龙．高层次综合和布图规划相结合的解空间分析．计算机辅助设计与图形学学报．2006，18(10)：1478-1483页
[33] 边计年．底层相关的VLSI高层次设计策略．计算机辅助设计与图形学学报．2000，12(11)：827-829页
[34] Mandal C A, Chakrabarti P P and Ghose S. Allocation and binding in data path synthesis using a genetic algorithm approach. Proceedings of the International Conference on Very Large Scale Integration Design, Bangalore, India,1996:122-125P
[35] Grewal G W and Wilson T C. An enhanced genetic solution for scheduling,module allocation, and binding in VLSI design. Proceedings of the International Conference on Very Large Scale Integration Design, Hyderabad, India, 1997:51-56P
[36] Landwehr B. A genetic algorithm based approach for multi-objective data-flow graph optimization. Proceedings of the Asia and South Pacific Design Automation Conference, Hong Kong, China, 1999:355-358P
[37] Banaiyan A, Esmaeelzadeh H and Safari S. Co-evolutionary scheduling and mapping for high-level test synthesis. Proceedings of the International Conference on Enterprise Information Systems, Islarnabad, Pakistan,2006:269-273
[38] Grewal G, O'Cleirigh M and Wineberg M. An evolutionary approach to behavioral-level synthesis. Proceedings of the Conference on Evolutionary Computation, Canberra, Australia, 2003:264-272P
[39] Torbey E and Knight J. High-level synthesis of digital circuits using genetic algorithms. Proceedings of the Conference on Evolutionary Computation,Piscateway, New Jersy, 1998:224-229P
[40] Vyas K and Srinivas K. A genetic algorithm for the design space exploration of datapaths during high-level synthesis. IEEE Transactions on evolutionary computation, 2006, 10(3):213-229P
[41] Torbey E and Knight J. Performing scheduling and storage optimization simultaneously using genetic algorithms. Proceedings of the Midwest Symposium on Circuits Systems, Indiana, USA, 1998:284-287P
[42] Ascia G; Catania V and Palesi M. A GA-based design space exploration framework for parameterized system-on-a-chip platform. IEEE Transactions on evaluationary computation, 2004, 8(4):329-346P
[43] Jackson D. Evolution of processor microcode. IEEE Transactions on Evaluationary Computation, 2005, 9(1): 44-54P
[44] Wang L, Wei S J. Interconnect reuse based resource allocation with GA approach. Proceedings of the International Conference on Application Specific Integrated Circuits, Beijing, China, 2003:290-293P
[45] 王磊，粟雅娟，魏少军．一种使用遗传算法在高层次综合中完成互连优化的方法．半导体学报．2004，25(5)：607-612页
[46] 谢晓锋，李钊，阮骏，姚依，张文俊，杨之廉：应用遗传算法实现MOS器件综合．半导体学报．2002，23(1)：95-101页
[47] Small C. Shrinking devices put the squeeze on system packaging. Electronics Design News, 1994, 39(4):41-46P
[48] Warwick C A and Ourmazd A. Trends and limits in monolithic integration by increasing the die area. IEEE Transactions on Semiconductor Manufacturing,1993, 6(3): 284-289P
[49] Weste N H E and Eshraghian K. Principles of CMOS VLSI design (a systems perspective, 2nd edition). Addison-Wesley, 1993:33-45P
[50] Pollack F. New microarchitecture challenges in the coming generations of CMOS process technologies. Politeonica de Catalunya, Intel Corporation Micro32 Conference Keynote, 1999:19-25P
[51] Khouri K S and Jha N K. Leakage power analysis and reduction during behavioral synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2002, 10(6):876-885P
[52] Kumar A, Bayoumi M and Cherabuddi R. Minimizing switchings of the function traits through binding for low power. Proceedings of the International Symposium on Circuits and Systems, Orlando, USA, 1999:66-69P
[53] Liu Z P, Bian J N and Huang J F. Fast and efficiently binding of functional units for low power design. Proceedings of the Conference on Application Specific Integrated Circuits, Shanghai, China, 2005:10-13P
[54] Srikantam V K, Ranganathan N and Srinivasan S. CREAM: combined register and module assignment with floorplanning for low power datapath synthesis.Proceedings of the International Conference on Very Large Scale Integration Design, Calcutta, India, 2000: 228-233P
[55] Liu Z P, Bian J N and Zhou Q. Interconnect power optimization based on the integration of high-level synthesis and floorplanning. Proceedings of the International Conferences on Communications, Circuits and Systems, Guilin, China, 2006:2286-2290P
[56] Prabhakaran P and Banerjee P. Simultaneous scheduling, binding and floorplanning in high-level synthesis. Proceedings of the International Conference on Very Large Scale Integration Design, San Jose, USA, 1998:428-434P
[57] Mohanty S P, Ranganathan N and Chappidi S K. An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. Proceedings of the International Symposium on Circuits and Systems, Bangkok, Thailand, 2003:313-316P
[58] Mohanty S P, Ranganathan N and Chappidi S K. Simultaneous peak and average power minimization during datapath scheduling. IEEE Transactions on Circuits and Systems, 2005, 52 (6): 1157-1165P
[59] Kim K B and Lin C H. An optimal ILP model for delay time to minimize peak power and area. Proceedings of the International Workshop on System-on-Chip for Real-Time Applications, Banff, Alberta, Canada, 2005:358-362P
[60] Cheng Y K and Kang S M. An efficient method for hot-spot identification in ULSI circuits. Proceedings of the International Conference on Computer-Aided Design, San Jose, USA, 1999:124-127P
[61] Gu Z Y, Yang Y H and Wang J. TAPHS: thermal-aware unified physical-level and high-level synthesis. Proceedings of the Asia and South Pacific Conference on Design Automation Conference, Yokohama, Japan, 2006:879-885P
[62] Zhao Z, Bian J N, Liu Z P. High level synthesis with multiple supply voltages for energy and combined peak power minimization. Proceedings of the Asia Pacific Conference on Circuits and Systems, Singapore, 2006:865-869P
[63] Mukherjee R and Memik S O. An integrated approach to thermal management in high-level synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2006,14 (11):1165-1173P
[64] Kumar A and Bayoumi M. Multiple voltage-based scheduling methodology for low power in the high level synthesis. Proceedings of the IEEE International Symposium on Circuits and Systems, Orlando, Florida, USA, 1999:371-374P
[65] Manzak A and Chakrabarti C. A low power scheduling scheme with resources operating at multiple voltages. IEEE Transactions on Very Large Scale Integration Systems, 2002, 10(1): 6-14P
[66] Bullnheimer B, Hartl R F and Strauss C. A new rank-based version of the ant system: a computational study. Central European Journal for Operations Research and Economics, 1999, 7(1):25-38P
[67] Maniezzo V and Colomi A. The ant system applied to the quadratic assignment problem. IEEE Transactionss on Knowledge and Data Engineering, 1999,11 (5):769-778P
[68] Dorigo M and Gambardella L M. Ant colony system: a cooperative learning approach to the traveling salesman problem. IEEE Transactions on Evolutionary Computation, 1997, 1(1):53-66P
[69] Stutzle T and Hoos H H. MAX-MIN ant system and local search for the traveling salesman problem. Proceedings of the International Conference on Evolutionary Computation, Indianapolis, USA, 1997:309-314P
[70] 丁建立，陈增强，袁著祉．遗传算法与蚂蚁算法的融合．计算机研究与发展．2003，40(9)：1531-1536页
[71] White T, Pagurek B and Oppacher F. ASGA: improving the ant system by integration with genetic algorithms. Proceedings of the Annual Genetic Programming Conference, Morgan Kaufmann, 1998:610-617P
[72] 吴庆洪，张纪会，徐心和．具有变异特性的蚁群算法．计算机研究与发展．1999，36(10)：1240-1245页
[73] Chen M and Lu Q. A Co-evolutionary model based on dynamic combination of genetic algorithm and ant colony algorithm. Proceedings of the International Conference on Parallel and Distributed Computing, Applications and Technologies. Dalian, China, 2005:941-944P
[74] 许可证，赵勇．面向方案组合优化设计的混合遗传蚂蚁算法．计算机辅助设计与图形学学报．2006，18(10)：1587-1593页
[75] Li M, Wang H and Li P. Tasks mapping in multi-core based system: hybrid ACO and GA approach. Proceedings of the International Conference on Application Specific Integrated Circuits, Beijing, China, 2003:335-340P
[76] 李智，许川佩，莫玮，陈光．基于蚂蚁算法和遗传算法的同步时序电路初始化．电子学报．2003，31(8)：1276-1280页
[77] Lee Z J. A hybrid algorithm applied to traveling salesman problem. Proceedings of the International Conference on Networking, Sensing and Control, Taipei,Taiwan, 2004:237-242P
[78] 熊志辉，李思昆，陈吉华．遗传算法与蚂蚁算法动态融合的软硬件划分．软件学报．2005，16(4)：503-512页
[79] Song X Y, Zhu Y L, Yin C W and Li F M. Study on the combination of genetic algorithms and ant Colony algorithms for solving fuzzy job shop scheduling problems. Multiconference on Computational Engineering in Systems Applications, Beijing, China, 2006:1904-1909P
[80] Minato S. Streaming BDD manipulation. IEEE Transactions on Computers,2002, 51 (5):474-485P
[81] Narayan A, Jain J and Fujita M. Partitioned ROBDDs-a compact, canonical and efficiently manipulable representation for boolean functions. Proceedings of the International Conference of Computer-Aided Design, San Jose, California,USA, 1996:547-554P
[82] Lain W K C and Brayton R K. Timed boolean functions: a unified formalism for exact timing analysis. Kluwer Academic Publishers, 1994:23-41P
[83] 闵应骅，李忠诚，赵著行．Boole过程论．中国科学(E辑)．1996，26(6)：541-548页
[84] 杜振军，马光胜，冯刚．基于布尔过程论的层次化延时分析方法．计算机研究与发展．2001，38(10)：1269-1275页
[85] 杜振军．布尔过程论及其在复杂高速芯片设计自动化应用中的研究．哈尔滨工程大学博士学位论文．2003：45-93页
[86] 冯刚，马光胜，杜振军．动态串扰优化的开关盒布线．半导体学报．2005，26(2)：399-405页
[87] 冯刚，马光胜，杜振军．信号相关的串扰优化详细布线．计算机辅助设计与图形学学报．2005，17(5)：1074-1078页
[88] 冯刚．基于Boole过程的考虑互连效应的EDA方法研究．哈尔滨工程大学博士学位论文．2005：17-104页
[89] Smith J and Micheli D G Polynomial circuit models for component matching in high-level synthesis. IEEE Transactions on Very Large Scale Integration Systems, 2001, 9(6):783-799P
[90] Smith J. Allocation and interface synthesis algorithms for component-based design. Technical Report, No. CSL-TR-00-793, 2000:58-95P
[91] Smith J and Micheli D G Polynomial methods for component matching and verification. Proceedings of the International Conference on Computer-Aided Design, San Jose, California, USA, 1998:678-685P
[92] Smith J and Micheli D G Polynomial methods for allocating complex components. Proceedings of the Design, Automation and Test in Europ, Munich,Germany, 1999:217-222P
[93] Smith J and Micheli D G A methodology for synthesis with reusable components from an arithmetic specification. Proceedings of the European Conference on Circuit Theory and Design, Stresa, Italy, 1999:1195-1198P
[94] Peymandoust A and Micheli D G. Application of symbolic computer algebra in high-level data-flow synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003, 22(9): 1154-1165P
[95] Peymandoust A and Micheli D G. Using symbolic algebra in algorithmic-level DSP synthesis. Proceedings of the Design Automation Conference, Las Vegas,USA, 2001:277-282P
[96] Peymandoust A and Micheli D G. Symbolic algebra and timing driven data-flow synthesis. Proceedings of the International Conference on Computer-Aided Design, San Jose, California, USA, 2001:300-305P
[97] Verma A K and Lenne P. Towards the automatic exploration of arithmetic-Circuit Architectures. Proceedings of the Design Automation Conference, San Francisco, California, 2006:445-450P
[98] Ciesielski M, Kalla P, Zeng Z and Rouzeyre B. Taylor expansion diagrams: a compact canonical representation with application to symbolic verification.Proceedings of the Design, Automation and Test in Europ, Paris, France,2002:285-289P
[99] Ciesielski M, kalla P and Askar S. Taylor expansion diagrams: a canonical representation for verification of data flow designs. IEEE Transactions on Computers, 2006, 55(9): 1188-1201P
[100] Fey G, Drechsler R and Ciesielski M. Algorithms for Taylor expansion diagrams. Proceedings of the International Symposium on Multiple-Valued Logic, Toronto, Canada, 2004:235-240P
[101] Gomez P D, Ren Q, Askar S and Ciesielski M. Variable ordering for Taylor expansion diagrams. Proceedings of the International High Level Design Validation and Test Workshop, California, USA, 2004:55-59P
[102] Guillot J, Boutillon E, Ren Q and Ciesielski M. Efficient factorization of DSP transforms using Taylor expansion diagrams. Proceedings of the Design,Automation and Test in Europ, Munich, Germany, 2006:754-755P
[103] Xing X W and Jong C C. Using symbolic computer algebra for subexpression factorization and subexpression decomposition in high level synthesis.Proceedings of the International Symposium on Circuits and Systems, Kobe,Japan, 2005:5645-5648P
[104] 董刚，杨银堂，柴长春．多芯片组件互连的功耗分析．计算机辅助设计与图形学学报．2005，17(8)：1809-1812页
[105] 王丽英，杨军，罗岚．SoC设计中的低功耗逻辑综合策略．电子工程师．2005，31(11)：10-12页
[106] 王玲，温东新，杨孝宗，蒋颖涛．一种基于时间限制条件的低功耗高层次设计方案．半导体学报．2005，26(2)：287-293页
[107] Wilken K, Liu J and Heffeman M. Optimal instruction scheduling using integer programming, Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, Vancouver, British Columbia, Canada, 2000:121-133P
[108] Topcuouglu H, Hariri S and Wu M Y. Performance-effective and low-complexity task scheduling for heterogeneous computing. IEEE Transactions on Parallel Distribution System, 2002, 13(3): 260-274P
[109] Heijligers M J M, Cluitmans L J M and Jess J A G. High-level synthesis scheduling and allocation using genetic algorithms. Proceedings of the Asia and South Pacific Design Automation Conference, Makuhari, Massa, Chiba,Japan, 1995:61-66P
[110] Wang G, Gong W R, DeRenzi B and Kastner R. Design space exploration using time and resource duality with the ant colony optimization. Proceedings of the Design Automation Conference, San Francisco, CA, USA,2006:451-454P
[111] Tseng C and Siewiorek D P. Automated synthesis of data paths in digital systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986, 5(3):379-395P
[112] 吴庆洪，张纪会，徐心和．具有变异特征的蚁群算法．计算机研究与发展．1999，36(10)：1240-1245页
[113] Dorigo M, Bonabeau E and Theraulaz G. Ant algorithm and stigmergy. Future Generation Computer System, 2000, 16(9): 851-871P
[114] http://express.ece.ucsb.edu/benchmark/[2007-06-15]
[115] Kaltofen E. Polynomial factorization: a success story. Proceedings of the International Symposium on Symbolic and Algebraic, Philadelphia,Pennsylvania, USA, 2003:3-4P
[116] David J and Kuck J W. The structure of computers and computations. ACM SIGARCH Computer Architecture News, 1979, 7(7):27-30P
[117] Kuck D J, Muraoka Y and Chen S C. On the number of operations simultaneously executable in fortran-like programs and their resulting speedup.IEEE Transactions on Computers, 1972, 21 (12): 1293-1310P
[118] Nicolau A and Potasman R. Incremental tree height reduction for high level synthesis. Proceedings of the Design Automation Conference, San Francisco,California, USA, 1991:770-774P
[119] Kolson D, Nicolau A and Dutt N. Integrating program transformations in the memory-based synthesis of image and video algorithms. Proceedings of the International Conference on Computer-Aided Design, San Jose, California,USA, 1994:27-30P
[120] Wang H, Nicolau A and Siu K. The strict time lower bound and optimal schedules for parallel prefix with resource constraints. IEEE Transactions on Computers, 1996, 45(11):1257-1271P
[121] Mathematica. Available: http://www.wri.com[2007-06-15]
[122] Khana F S and Perkowskib M. Synthesis of multi-qudit hybrid and d-valued quantum logic circuits by decomposition. Theoretical Computer Science, 2006,367(3): 336-346P
[123] Brayton R, Rudell R, Sangiovanni-Vincentelli A and Wang A. MIS: a multiple-level logic optimization and the rectangular covering problem.Proceedings of the International Conference Computer-Aided Design,Anaheim, California, USA, 1987:1062-1081P
[124] Cox D, Little J and O'Shea D. Ideals, Varieties, and Algorithms. New York:Springer-Verlag, 1997:78-88P
[125] Mehra R, Guerra L M and Rabaey J M. Low-power architectural synthesis and the impact of exploiting locality. Journal of Very Large Scale Integration Signal Processing, 2005, 13(2):239-258P
[126] Chang J M and Pedram M. Energy minimization using multiple supply voltages. IEEE Transactions on Very Large Scale Integration Systems, 1997,5(4): 436-443P
[127] 运筹学教材组．运筹学(第三版)．清华大学出版社．2005：268-273页
[128] 谢政．网络算法与复杂性理论(第二版)．国防科技大学出版社．2003：113-131页
[129] 谢金星，邢文训．网络优化．清华大学出版社．2000：144-184页
[130] Mussoll E and Cortadella J. High-level synthesis techniques for reducing the activity of functional units. Proceedings of the International Symposium on Low-Power Design, California, USA, 1995:99-104P
[131] Munch M, Wurth B, Mehra R, Sproch J and Wehn N. Automating RT-level operand isolation to minimize power consumption in datapaths. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Paris,France, 2000:624-631P