基于自主嵌入式处理器的半自定制物理设计方法研究
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摘要
随着集成工艺的不断发展,集成电路设计进入了以纳米为代表的SOC(System On Chip)时代。庞大的电路设计规模以及深亚微米条件下各种全新的工艺设计问题,都为集成电路的物理设计提出了新的挑战。如何改进物理设计的方法与流程,对于保证和提升芯片性能,缩短产品的开发周期都有着重要的产业意义和商业价值。
本文基于具有自主知识产权的CK系列嵌入式CPU,提出了一种全新的半定制物理设计方法及流程。该流程将可重构的设计思想贯穿始终,通过引入一种新型的具有版图可重构特性的标准单元结构,将电路晶体管级的优化与调整融入整个芯片的物理设计流程中。方法创新的将一种基于图论的电路拓扑分解算法引入对电路网表的简化过程中,分离出可实施调整的目标电路。并在对目标电路进行晶体管调整的过程中,将连线延时及窜扰延时的变化考虑在内,从而获得连线延时与单元延时之间的平衡优化解决方案。相比传统方法,该方法在实现对电路性能优化的同时,极大的降低了对芯片实施晶体管级调整的难度与复杂度,并保证了设计流程的收敛与迭代次数。
另一方面,本文提出了一种新型的可重构的延时可控网络驱动器结构(DCCB),并提出了基于这一结构对时钟树网络进行调整优化的算法。该算法通过DCCB将有益时钟偏差有效的引入电路,直接针对电路版图进行时钟树调整,实现时钟周期的优化。试验数据表明,此方法对时钟周期的优化相比传统方法高出10%-17%。
最后,本文对CPU中的一类重要的数据存储单元SRAM的自定制设计进行了初步的研究,详细讨论了SRAM单元的建库技术及时序信息库提取的具体方法。
As technology develops, IC design has stepped into the nanometer scale SOC era. The huge circuit scale along with all kinds of novel process technology issues, bring new challenges to the IC physical design methodology. How to improve physical design approaches and flow is greatly significant in industrial and commercial field for decreasing the product development period as well as ensuring and promoting the integration performance of a chip.
A novel semi-custom physical design methodology is proposed based on an embedded system CK series CPU which owns the complete intellectual property rights. This approach merges the transistor level adjustment and optimization into the entire IC physical design flow according to a novel reconfigurable standard cell frame. Utilizing a network graph partition and simplification algorithm, the method extracts the objective circuit available for tuning which is consequently used for implementing a trade-off optimization between cell delay and net delay by taking the net delay variation during the transistor adjustment procedure into account. In comparison with the traditional methodologies, this method realizes the circuit performance optimization in addition to decreasing the complexity and difficulty of transistor tuning on a chip and meanwhile maintains the design convergence and iterations.
Based on the reconfigurable perspective, a novel delay controllable clock buffer (DCCB) is proposed for clock period optimization via a clock tree adjustment algorithm which generates useful clock skew according to DCCB reconfiguration and direct layout modification. Experiments indicated that this approach improved the clock period by approximate 10%-17% higher than the traditional methodologies.
Finally, the dissertation discusses the primary research on SRAM timing library generation and presents the SRAM timing library extraction approaches concretely.
本文基于具有自主知识产权的CK系列嵌入式CPU,提出了一种全新的半定制物理设计方法及流程。该流程将可重构的设计思想贯穿始终,通过引入一种新型的具有版图可重构特性的标准单元结构,将电路晶体管级的优化与调整融入整个芯片的物理设计流程中。方法创新的将一种基于图论的电路拓扑分解算法引入对电路网表的简化过程中,分离出可实施调整的目标电路。并在对目标电路进行晶体管调整的过程中,将连线延时及窜扰延时的变化考虑在内,从而获得连线延时与单元延时之间的平衡优化解决方案。相比传统方法,该方法在实现对电路性能优化的同时,极大的降低了对芯片实施晶体管级调整的难度与复杂度,并保证了设计流程的收敛与迭代次数。
另一方面,本文提出了一种新型的可重构的延时可控网络驱动器结构(DCCB),并提出了基于这一结构对时钟树网络进行调整优化的算法。该算法通过DCCB将有益时钟偏差有效的引入电路,直接针对电路版图进行时钟树调整,实现时钟周期的优化。试验数据表明,此方法对时钟周期的优化相比传统方法高出10%-17%。
最后,本文对CPU中的一类重要的数据存储单元SRAM的自定制设计进行了初步的研究,详细讨论了SRAM单元的建库技术及时序信息库提取的具体方法。
As technology develops, IC design has stepped into the nanometer scale SOC era. The huge circuit scale along with all kinds of novel process technology issues, bring new challenges to the IC physical design methodology. How to improve physical design approaches and flow is greatly significant in industrial and commercial field for decreasing the product development period as well as ensuring and promoting the integration performance of a chip.
A novel semi-custom physical design methodology is proposed based on an embedded system CK series CPU which owns the complete intellectual property rights. This approach merges the transistor level adjustment and optimization into the entire IC physical design flow according to a novel reconfigurable standard cell frame. Utilizing a network graph partition and simplification algorithm, the method extracts the objective circuit available for tuning which is consequently used for implementing a trade-off optimization between cell delay and net delay by taking the net delay variation during the transistor adjustment procedure into account. In comparison with the traditional methodologies, this method realizes the circuit performance optimization in addition to decreasing the complexity and difficulty of transistor tuning on a chip and meanwhile maintains the design convergence and iterations.
Based on the reconfigurable perspective, a novel delay controllable clock buffer (DCCB) is proposed for clock period optimization via a clock tree adjustment algorithm which generates useful clock skew according to DCCB reconfiguration and direct layout modification. Experiments indicated that this approach improved the clock period by approximate 10%-17% higher than the traditional methodologies.
Finally, the dissertation discusses the primary research on SRAM timing library generation and presents the SRAM timing library extraction approaches concretely.
引文
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