H.264视频解码器帧内预测部分的ASIC设计
摘要
随着新世纪的到来,人类进入了一个全新的多媒体信息时代。作为多媒体中最重要、最具表现力和最复杂的数字视频处理,也随着时代的发展取得了长足的进步。新的H.264视频编码标准在相同的视觉感知质量上,编码效率比H.263,MPEG-2和MPEG-4提高了50%左右,并且有更好的网络友好性。
H.264在混合编码器的基本框架下,对关键部件都做了重大调整,如多模式运动估计、帧内预测、基于内容的变长编码等,这使得其实现难度要显著高于以往的视频编码标准。从总体上说,H.264性能的改善是以增加复杂性为代价而获得的。
本文介绍了H.264视频编解码标准以及作者在H.264视频解码器硬件实现方面的研究,主要对H.264标准中的帧内预测部分进行了研究,提出了一种使用并行化操作的ASIC设计,其中帧内预测与变换系数逆扫描、系数逆量化、逆变换等过程都采用了并行结构,这样大大节省了处理时间,提高了解码速率,使得帧内部分处理一个宏块的时间大大缩短,完全可以达到实时解码的要求。作者用Verilog HDL语言实现了这些模块,并成功地在Xilinx的Virtex2 FPGA器件xc2v40上仿真了该方案,获得了很好的实时性能。
H.264/MPEG-AVC is a video encoding & decoding standard which is established by the JVT which is constituted by ITU-T’s VCEG and ISO/IEC’s MPEG. It is not only the H.264 of ITU-T, but also the part 10 of MPEG-4 of ISO/IEC. H.264 is a widely accepted video encoding & decoding standard, it could be used from the service of mobile video to meeting conference, IPTV, HDTV and DVD. It almost covers all the applications of video processing. Its basic system is into the open and needn’t copyrights.
H.264 added new intra predicted encoding of single picture, and made use of the left and up macro block pixels which have been decoded and restructured of the predicted block to predict the current block. It only needed to encode the difference between the current block and the predicted block. The information of block of intra encoding could be expressed by a few of bytes, decreasing the redundancy bytes of correlate information. H.264’s intra-prediction divided the macro block into three types: 16*16 macroblock-predictions modes of processing static and moving slowly pictures, 4*4 macroblock-predictions modes of processing complex and moving intensely pictures, and 8*8 macroblock-predictions of color pictures. Every mode also offered multi-directions’spatial-prediction modes: 9 modes of intra_4*4, 4 modes of intra_16*16 and 4 modes intra_8*8(including U and V the two equal color block, every block had 64 pixels predicted.) , there were 17 intra-modes in the way of prediction. The motion-estimation of intra-prediction of H.264 had improved from the 1/4 pixel-precision to 1/8 pixel-precision, but the complexity of decoding was about 3 times than that of MPEG-2. Owing to decoder was strictly limited by the standard of encoder, the flexible of its algorithm is quite small, but the designer still could assign the structure of the decoder from the beginning and research the multi-layer nesting loop in the referenced software to settle disturbances and abstract codes. The aim is to improve the speed of decoding.
Transplanting the procedure of decoding to hardware is a meaningful breakthrough. The advantage of hardware to the software is evidence: the trait of hardware is quick decoding speed and parallel processing. The project based on hardware has a great outlook. However, the hardware couldn’t deal with a complex control and couldn’t be remedied when the design was over; still others, the price of hardware is very expensive. So, before done it needed software-experiment-flat to give it assistance, which is the common ground of many researchers who deal with the fact of hardware. Separate the hardware and software into two parts: motion- compensation and boundary-filtering. In the part of motion-compensation, hardware is used for decoding the module of macro block. Utilizing the advantage of hardware may achieve more efficiency of decoding and real-time decoding.
Video decoding has two researchable directions: the first is the decoder’s fast decoding algorithm. The part of decoding & encoding adopted two algorithms: context-based adaptive binary arithmetic coding and entropy coding method in the results of current researching. The entropy coding method includes universal variable length coding and context adaptive variable length coding. In the procedure of decoding, inter-prediction is needed to get the data of image which is gained though adding current block’s prediction block in its reference pictures to the dispersion of decoding. If you want to improve the frequency, the key point is looking for a good algorithm. The second is the part of real-time decoding. In this part, there are many difficult, just as FIFO circus which will lead to the sub-stabilization, and many implementation ways like CPU implementation, DSP implementation, ASIC implementation and FPGA implementation. Choosing a way which is economical and efficient is the footstone of this paper.
This paper compared some methods of decoding, and chose the ASIC to accomplish decoding at last. Choose some advanced algorithms as far as possible in design process; particularly carry on the optimization to the decoding process. Only in this way can obtain the quite good result, and make the decoding speed to improve largely。This paper in earlier period mainly used software simulation, as a result of ability limited, when the paper completed did not have hardware's material object which is this paper the biggest regret, but according to the software simulation's result, the author believed that hardware material object could form very quickly in the future. This paper comes from the request of the video decoding development. Today, in our society, the requests of digital television and other video products are unceasingly improving and the request of speed and price of decoder are also unceasingly enhancement. One kind of reasonable price, highly effective and high clear decoding product will quickly seize the market; therefore each scientific research institution will promote the new model decoders when they will pay more attention to the economic benefits. In this aspect, this paper also has a very big improvement space.
H.264在混合编码器的基本框架下,对关键部件都做了重大调整,如多模式运动估计、帧内预测、基于内容的变长编码等,这使得其实现难度要显著高于以往的视频编码标准。从总体上说,H.264性能的改善是以增加复杂性为代价而获得的。
本文介绍了H.264视频编解码标准以及作者在H.264视频解码器硬件实现方面的研究,主要对H.264标准中的帧内预测部分进行了研究,提出了一种使用并行化操作的ASIC设计,其中帧内预测与变换系数逆扫描、系数逆量化、逆变换等过程都采用了并行结构,这样大大节省了处理时间,提高了解码速率,使得帧内部分处理一个宏块的时间大大缩短,完全可以达到实时解码的要求。作者用Verilog HDL语言实现了这些模块,并成功地在Xilinx的Virtex2 FPGA器件xc2v40上仿真了该方案,获得了很好的实时性能。
H.264/MPEG-AVC is a video encoding & decoding standard which is established by the JVT which is constituted by ITU-T’s VCEG and ISO/IEC’s MPEG. It is not only the H.264 of ITU-T, but also the part 10 of MPEG-4 of ISO/IEC. H.264 is a widely accepted video encoding & decoding standard, it could be used from the service of mobile video to meeting conference, IPTV, HDTV and DVD. It almost covers all the applications of video processing. Its basic system is into the open and needn’t copyrights.
H.264 added new intra predicted encoding of single picture, and made use of the left and up macro block pixels which have been decoded and restructured of the predicted block to predict the current block. It only needed to encode the difference between the current block and the predicted block. The information of block of intra encoding could be expressed by a few of bytes, decreasing the redundancy bytes of correlate information. H.264’s intra-prediction divided the macro block into three types: 16*16 macroblock-predictions modes of processing static and moving slowly pictures, 4*4 macroblock-predictions modes of processing complex and moving intensely pictures, and 8*8 macroblock-predictions of color pictures. Every mode also offered multi-directions’spatial-prediction modes: 9 modes of intra_4*4, 4 modes of intra_16*16 and 4 modes intra_8*8(including U and V the two equal color block, every block had 64 pixels predicted.) , there were 17 intra-modes in the way of prediction. The motion-estimation of intra-prediction of H.264 had improved from the 1/4 pixel-precision to 1/8 pixel-precision, but the complexity of decoding was about 3 times than that of MPEG-2. Owing to decoder was strictly limited by the standard of encoder, the flexible of its algorithm is quite small, but the designer still could assign the structure of the decoder from the beginning and research the multi-layer nesting loop in the referenced software to settle disturbances and abstract codes. The aim is to improve the speed of decoding.
Transplanting the procedure of decoding to hardware is a meaningful breakthrough. The advantage of hardware to the software is evidence: the trait of hardware is quick decoding speed and parallel processing. The project based on hardware has a great outlook. However, the hardware couldn’t deal with a complex control and couldn’t be remedied when the design was over; still others, the price of hardware is very expensive. So, before done it needed software-experiment-flat to give it assistance, which is the common ground of many researchers who deal with the fact of hardware. Separate the hardware and software into two parts: motion- compensation and boundary-filtering. In the part of motion-compensation, hardware is used for decoding the module of macro block. Utilizing the advantage of hardware may achieve more efficiency of decoding and real-time decoding.
Video decoding has two researchable directions: the first is the decoder’s fast decoding algorithm. The part of decoding & encoding adopted two algorithms: context-based adaptive binary arithmetic coding and entropy coding method in the results of current researching. The entropy coding method includes universal variable length coding and context adaptive variable length coding. In the procedure of decoding, inter-prediction is needed to get the data of image which is gained though adding current block’s prediction block in its reference pictures to the dispersion of decoding. If you want to improve the frequency, the key point is looking for a good algorithm. The second is the part of real-time decoding. In this part, there are many difficult, just as FIFO circus which will lead to the sub-stabilization, and many implementation ways like CPU implementation, DSP implementation, ASIC implementation and FPGA implementation. Choosing a way which is economical and efficient is the footstone of this paper.
This paper compared some methods of decoding, and chose the ASIC to accomplish decoding at last. Choose some advanced algorithms as far as possible in design process; particularly carry on the optimization to the decoding process. Only in this way can obtain the quite good result, and make the decoding speed to improve largely。This paper in earlier period mainly used software simulation, as a result of ability limited, when the paper completed did not have hardware's material object which is this paper the biggest regret, but according to the software simulation's result, the author believed that hardware material object could form very quickly in the future. This paper comes from the request of the video decoding development. Today, in our society, the requests of digital television and other video products are unceasingly improving and the request of speed and price of decoder are also unceasingly enhancement. One kind of reasonable price, highly effective and high clear decoding product will quickly seize the market; therefore each scientific research institution will promote the new model decoders when they will pay more attention to the economic benefits. In this aspect, this paper also has a very big improvement space.
引文
[1] Republish ITU-T H.264 Series H :Audiovisual and Multimedia Systems Infrastructure of Audiovisual Services-Coding of Moving Video. Telecommunication Standardization Sector of ITU,2005,3.
[2] RongGang Wang,JinTao Li, Chao Huang. Motion Compensation Memory Access Optimization Strategies for H.264/AVC Decoder,2005 IEEE international conference on acoustics, speech, and signal processing,2005,3.
[3] Changsung Kim, Hsuan - Huei Shih, Jay Kuo . Feature-based intra - prediction mode decision for H.264.IEEE Proceedings of International Conference Image Processing, Singapore, 2004.
[4] JVT- G050. Draft ITU- T Recommendation and Final Draft International Standard of Joint Video Specification, 2003.
[5] Roman Kordasiewicz, Shahram Shirani. On Hardware Implementations of DCT and Quantization Blocks for H.264/AVC. Journal of VLSI Signal Processing, 2007, 47:93-102.
[6] Qiang Wang, De-Bin Zhao, Wen Gao.Context-Based 2D-VLC Entropy Coder in AVS Video Coding Standard. J. Comput. Sci.& Technol.,2006, 21(3):315-322.
[7] Bojun Meng, Oscar C. Au. Fast Intra-Prediction Mode Selection for 4x4 Blocks in H.264. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003, 3: 389-392.
[8] 祝敏,刘济林,陈国斌等. H.264/AVC 解码器芯片应用简介. 电视技术. 2006,2:30-33.
[9] 毕厚杰. 新一代视频压缩编码标准——H.264/AVC. 人民邮电出版社. 2005.
[10] 易敏刚. 基于 H.263 的的码率视频压缩编码的软硬件实现. 西安:西北工业大学硕士论文. 2005.
[11] 乔轩. H.26X 系列的算法研究. 浙江:浙江大学硕士论文. 2005.
[12] 陈萍. H.264 视频编码算法研究及解码算法的软件实现. 北京:北京邮电大学硕士论文. 2004.
[13] 夏宇闻. Verilog数字系统设计教程. 北京航空航天大学出版社. 2003.
[14] 魏振宇,史鹍,张旭东. H.264 编解码器在 C6416 DSP 上的实现与优化. 电子产品世界. 2005,5:71-74.
[15] 朱本营,林涛. 基于 FPGA 的 H.264/AVC 视频解码系统验证平台的设计.电子技术应用. 2006,7:109-111.
[16] 荆萍,林争辉. H.264 视频解码器的 ASIC 实验及其中的熵解码. 有线电视技术. 2006,10:39-40.
[17] 梁晓芸,焦孟草,林争辉. H.264 解码器的 ASIC 解决方案及其FPGA 验证平台. 电视技术. 2004,10:50-51.
[18] 张钰,胡亮亮,舒伟. H.264 解码解决方案实例介绍.电子产品世界.2005,10:52-54.
[19] 虞新阳. H.264 解码器的优化及在 ARM 上的实现. 西安:西安电子科技大学硕士论文,2007.
[20] 杨芳芳. H.264 编码器的 DSP 实现与优化.西安:西安电子科技大学硕士论文,2005.
[21] 熊赟,于鸿洋. H.264 实时软件解码器的实现. 中国有线电视. 2005,6:562-565.
[22] 周详平,王嵩. 新标准 H.264 的核心技术和应用前景. 中国有线电视. 2004,15:55-60.
[23] 陈维安,李典,余松煜,钱团结. H.264 软件解码器的优化. 数据采集与处理. 2005,20(4):493-498.
[24] 李彦东,许生旺. H.264/AVC 在 3G 移动通信中的应用. 无线电通信技术. 2006,32(2):51-54.
[25] 干宗良,朱秀昌,王凯. H.264 解码在 ADDSP-BF533 上的实现和优化.中国电子科学研究院学报.2006,4:360-363.
[26] 刘凌志,路奇,戎蒙恬.一种并行结构的 H.264 帧内预测器. 上海交通大学学报.2006,40(1):54-58.
[27] Esra Sahin, Ilker Hamzaoglu. An Efficient Intra Prediciton Hardware Architecture for H.264 Video Decoding.10th Euro micro Conference on Digital System Design Architectures, Methods and Tools, IEEE. 2007.
[28] 纪洪芝,张玉明,黄晁. H.264/AVC 解码中帧内预测的硬件实现. 微电子学与计算机.2007,24(7):173-179.
[29] 王征,刘佩林. AVS 帧内预测算法及其解码器的硬件实现.计算机工程与应用.2006,19:80-83.
[30] 姜弢,周佩海,MIN Bahadur K.C.H.264 及 AVC 双模视频解码器中帧内预测的硬件设计与实现.电子技术应用. 2007,9:41-44.
[2] RongGang Wang,JinTao Li, Chao Huang. Motion Compensation Memory Access Optimization Strategies for H.264/AVC Decoder,2005 IEEE international conference on acoustics, speech, and signal processing,2005,3.
[3] Changsung Kim, Hsuan - Huei Shih, Jay Kuo . Feature-based intra - prediction mode decision for H.264.IEEE Proceedings of International Conference Image Processing, Singapore, 2004.
[4] JVT- G050. Draft ITU- T Recommendation and Final Draft International Standard of Joint Video Specification, 2003.
[5] Roman Kordasiewicz, Shahram Shirani. On Hardware Implementations of DCT and Quantization Blocks for H.264/AVC. Journal of VLSI Signal Processing, 2007, 47:93-102.
[6] Qiang Wang, De-Bin Zhao, Wen Gao.Context-Based 2D-VLC Entropy Coder in AVS Video Coding Standard. J. Comput. Sci.& Technol.,2006, 21(3):315-322.
[7] Bojun Meng, Oscar C. Au. Fast Intra-Prediction Mode Selection for 4x4 Blocks in H.264. IEEE International Conference on Acoustics, Speech, and Signal Processing, 2003, 3: 389-392.
[8] 祝敏,刘济林,陈国斌等. H.264/AVC 解码器芯片应用简介. 电视技术. 2006,2:30-33.
[9] 毕厚杰. 新一代视频压缩编码标准——H.264/AVC. 人民邮电出版社. 2005.
[10] 易敏刚. 基于 H.263 的的码率视频压缩编码的软硬件实现. 西安:西北工业大学硕士论文. 2005.
[11] 乔轩. H.26X 系列的算法研究. 浙江:浙江大学硕士论文. 2005.
[12] 陈萍. H.264 视频编码算法研究及解码算法的软件实现. 北京:北京邮电大学硕士论文. 2004.
[13] 夏宇闻. Verilog数字系统设计教程. 北京航空航天大学出版社. 2003.
[14] 魏振宇,史鹍,张旭东. H.264 编解码器在 C6416 DSP 上的实现与优化. 电子产品世界. 2005,5:71-74.
[15] 朱本营,林涛. 基于 FPGA 的 H.264/AVC 视频解码系统验证平台的设计.电子技术应用. 2006,7:109-111.
[16] 荆萍,林争辉. H.264 视频解码器的 ASIC 实验及其中的熵解码. 有线电视技术. 2006,10:39-40.
[17] 梁晓芸,焦孟草,林争辉. H.264 解码器的 ASIC 解决方案及其FPGA 验证平台. 电视技术. 2004,10:50-51.
[18] 张钰,胡亮亮,舒伟. H.264 解码解决方案实例介绍.电子产品世界.2005,10:52-54.
[19] 虞新阳. H.264 解码器的优化及在 ARM 上的实现. 西安:西安电子科技大学硕士论文,2007.
[20] 杨芳芳. H.264 编码器的 DSP 实现与优化.西安:西安电子科技大学硕士论文,2005.
[21] 熊赟,于鸿洋. H.264 实时软件解码器的实现. 中国有线电视. 2005,6:562-565.
[22] 周详平,王嵩. 新标准 H.264 的核心技术和应用前景. 中国有线电视. 2004,15:55-60.
[23] 陈维安,李典,余松煜,钱团结. H.264 软件解码器的优化. 数据采集与处理. 2005,20(4):493-498.
[24] 李彦东,许生旺. H.264/AVC 在 3G 移动通信中的应用. 无线电通信技术. 2006,32(2):51-54.
[25] 干宗良,朱秀昌,王凯. H.264 解码在 ADDSP-BF533 上的实现和优化.中国电子科学研究院学报.2006,4:360-363.
[26] 刘凌志,路奇,戎蒙恬.一种并行结构的 H.264 帧内预测器. 上海交通大学学报.2006,40(1):54-58.
[27] Esra Sahin, Ilker Hamzaoglu. An Efficient Intra Prediciton Hardware Architecture for H.264 Video Decoding.10th Euro micro Conference on Digital System Design Architectures, Methods and Tools, IEEE. 2007.
[28] 纪洪芝,张玉明,黄晁. H.264/AVC 解码中帧内预测的硬件实现. 微电子学与计算机.2007,24(7):173-179.
[29] 王征,刘佩林. AVS 帧内预测算法及其解码器的硬件实现.计算机工程与应用.2006,19:80-83.
[30] 姜弢,周佩海,MIN Bahadur K.C.H.264 及 AVC 双模视频解码器中帧内预测的硬件设计与实现.电子技术应用. 2007,9:41-44.
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