SOI功率器件的新结构研究
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摘要
绝缘体上的硅（Silicon On Insulator，简称SOI）高压集成电路（High VoltageIntegrated Circuit，简称HVIC）凭借其隔离性能优良、集成度高、响应速度快和抗辐照等优点在智能功率集成电路（Smart Power IC，简称SPIC）中得到广泛的应用。SOI功率器件是整个SOI HVIC的基础，是近年来研究的热点。而耐压与比导通电阻是SOI功率器件两个至关重要的参数，在设计时必须给予很好的兼顾。其中，SOI功率器件的耐压问题主要是由于在器件中引入了介质层，使得耗尽区不能向衬底扩散而造成的纵向耐压限制，引起整个器件耐压值偏低。而SOI功率器件的比导通电阻问题，则是因为在追求小的比导通电阻时，常常会造成器件耐压值降低，因此在设计SOI功率器件时，必须保证在高耐压值的前提下，降低器件的比导通电阻。
针对上述问题，本文做了大量的研究工作，主要可以概括为以下几个方面：
第一，结合介质场增强理论与降低体内电场（Reduced BULk Field，简称REBULF）理论，提出了非耗尽浮空层（Non-depletion Floating Layer，简称NFL）调制电场机理。该机理的主要思想是在传统的SOI功率器件中引入了一层高浓度掺杂的埋层，该埋层在器件耐压时不会被耗尽，形成了一层等势体层，该等势体层电位较高，并且其中电场为零，此时该等势体层可以被看作金属。因此器件在耐压时，该等势体层对SOI层中的电场进行调制，使得SOI层中的电场得以均匀分布。同时，该等势体层向下形成等势体层（金属）—埋氧层—衬底（Metal–Insulator–Semiconductor，简称MIS）结构。在等势体层与埋氧层界面处形成了大量的空穴，埋氧层中的电场因此得到了显著的增强，器件耐压得以提高。基于此机理，提出了一种非耗尽浮空层N型沟道SOI LDMOS结构。并且该结构在耐压时，等势体层被钳制到固定电位，使得埋氧层可以无限减薄，此时只需考虑SiO2的临界电场，避免器件在埋氧层中发生击穿，因为SiO2的临界电场远高于硅，因此可以把埋氧层减得很薄。这种现象可以很好地缓解SOI功率器件中的自热效应。在等势体层与埋氧层界面处形成的大量空穴在器件耐压时有效地屏蔽了背栅压对器件耐压值的影响，使得器件便于集成到电路中。
第二，针对SOI功率器件纵向耐压低的问题，提出一种新的耐压机理，该机理在本文中被称为等效双倍埋氧层厚度机理。该机理的主要思想是把传统SOI功率器件中的埋氧层一分为二，并在埋氧层的下方引入高浓度掺杂的埋层，作为电势连续的载体，使得在不增加埋氧层厚度的情况下，器件的等效埋氧层厚度变为了原来的两倍，因此在理想状况下，器件的纵向耐压几乎可以提高一倍。基于该机理，提出了一种非耗尽电势嵌位层（Non-depletion Potential Clamped Layer，简称NPCL）P型沟道SOI LDMOS结构。该结构的耐压值相比于传统结构提高了55%，并且比导通也大幅度下降。
第三，针对SOI功率器件比导通电阻的问题，提出了电荷补偿的双介质槽与多介质槽N型沟道SOI LDMOS结构。这两种结构原理相同，都是在增强的RESURF效应下，根据电荷补偿原理引入了复合缓冲层（Composite Buffer layer，简称CB层），增加了漂移区中的浓度，该器件在保持高耐压值的同时，得到了很小的比导通电阻。
第四，同样针对SOI功率器件比导通电阻的问题，提出了一种超级高介电常数（高K）SOI超结LDMOS结构。该结构将高K材料与超结结构相结合，在保持器件高耐压值的同时，利用高K材料的电荷积累效应，使得器件的比导通电阻大幅度降低，因此器件在整个电路中占的面积显著减小。
Silicon On Insulator（SOI）High Voltage Integrated Circui（tHVIC）attracts a greatnumber of attention due to the merits of good isolation, high integrated density, fastrespond speed and immunity to radiation. The SOI power device is the key componentin the SOI HVIC. The key parameters of the SOI power device are breakdown voltageand specific on-resistance. The reason about the limit of breakdown voltage of SOIpower device is introducing of the Buried OXide（BOX）into the device, and thedepletion layer can’t spread into the substrate. This phenomenon causes the verticalbreakdown voltage to be very low and furthermore it degrades the breakdown voltage ofthe SOI power device. On the other hand, though some methods can reduce specificon-resistance, it causes the deterioration of the RESURF effect and causes drop ofbreakdown voltage.
According to the problems, this dissertation did a lot of work to resolve themmentioned before. The main work includes these aspects as follows:
First, combining the Enhanced Dielectric Field（ENDIF）and REBULF principle,we proposed a Non-depletion Floating Layer（NFL）N channel SOI LDMOS structure.This structure introduces a high concentration doped layer into the conventional SOIpower device. When the device is under blocking state, NFL can’t be depleted, andbecome an equi-potential layer. This equi-potential layer can modulate the electric fieldin the SOI layer and make the electric field distribution more evenly. Meanwhile, theinterface of SOI layer and BOX generates a large number of holes. According to theGauss law, the electric field in the BOX is hence significantly boosted. Futhermore, thisburied layer is pinned to a certain voltage. When the thickness of the BOX is keepingreduced, the breakdown voltage of the SOI power device maintains the same value. Thisphenomenon can effectively alleviate the Self-Heating effect in SOI power device. Thelarge number of holes at the interface of SOI layer and BOX can shield the back-gatevoltage affecting on the breakdown voltage.
Second, according to the low vertical breakdown voltage, we proposed aNon-depletion Floating Layer（NFL）P channel SOI LDMOS structure. This structure splits the BOX into two sections, with the assistance of a high concentration dopedburied layer, therefore the equivalent thickness of the BOX doubled. This breakdownvoltage of the proposed structure is boosted55%and the specific on-resistance is alsosignificantly reduced.
Third, according to the specific on-resistance of the SOI power device, weproposed the charge compensated two trenches and multiple trenches N channel SOILDMOS. The two structure share the same principle, with the enhanced RESURF effect,the devices can reduce the specific on-resistance with the high breakdown voltage.
Fourth, combining the high K material and the Super Junction structure, weproposed a high K SOI Super Junction LDMOS structure. This structure cansignificantly reduce the specific on-resistance with the high breakdown voltage. Thelayout area of the power device can hence greatly shrink.
针对上述问题，本文做了大量的研究工作，主要可以概括为以下几个方面：
第一，结合介质场增强理论与降低体内电场（Reduced BULk Field，简称REBULF）理论，提出了非耗尽浮空层（Non-depletion Floating Layer，简称NFL）调制电场机理。该机理的主要思想是在传统的SOI功率器件中引入了一层高浓度掺杂的埋层，该埋层在器件耐压时不会被耗尽，形成了一层等势体层，该等势体层电位较高，并且其中电场为零，此时该等势体层可以被看作金属。因此器件在耐压时，该等势体层对SOI层中的电场进行调制，使得SOI层中的电场得以均匀分布。同时，该等势体层向下形成等势体层（金属）—埋氧层—衬底（Metal–Insulator–Semiconductor，简称MIS）结构。在等势体层与埋氧层界面处形成了大量的空穴，埋氧层中的电场因此得到了显著的增强，器件耐压得以提高。基于此机理，提出了一种非耗尽浮空层N型沟道SOI LDMOS结构。并且该结构在耐压时，等势体层被钳制到固定电位，使得埋氧层可以无限减薄，此时只需考虑SiO2的临界电场，避免器件在埋氧层中发生击穿，因为SiO2的临界电场远高于硅，因此可以把埋氧层减得很薄。这种现象可以很好地缓解SOI功率器件中的自热效应。在等势体层与埋氧层界面处形成的大量空穴在器件耐压时有效地屏蔽了背栅压对器件耐压值的影响，使得器件便于集成到电路中。
第二，针对SOI功率器件纵向耐压低的问题，提出一种新的耐压机理，该机理在本文中被称为等效双倍埋氧层厚度机理。该机理的主要思想是把传统SOI功率器件中的埋氧层一分为二，并在埋氧层的下方引入高浓度掺杂的埋层，作为电势连续的载体，使得在不增加埋氧层厚度的情况下，器件的等效埋氧层厚度变为了原来的两倍，因此在理想状况下，器件的纵向耐压几乎可以提高一倍。基于该机理，提出了一种非耗尽电势嵌位层（Non-depletion Potential Clamped Layer，简称NPCL）P型沟道SOI LDMOS结构。该结构的耐压值相比于传统结构提高了55%，并且比导通也大幅度下降。
第三，针对SOI功率器件比导通电阻的问题，提出了电荷补偿的双介质槽与多介质槽N型沟道SOI LDMOS结构。这两种结构原理相同，都是在增强的RESURF效应下，根据电荷补偿原理引入了复合缓冲层（Composite Buffer layer，简称CB层），增加了漂移区中的浓度，该器件在保持高耐压值的同时，得到了很小的比导通电阻。
第四，同样针对SOI功率器件比导通电阻的问题，提出了一种超级高介电常数（高K）SOI超结LDMOS结构。该结构将高K材料与超结结构相结合，在保持器件高耐压值的同时，利用高K材料的电荷积累效应，使得器件的比导通电阻大幅度降低，因此器件在整个电路中占的面积显著减小。
Silicon On Insulator（SOI）High Voltage Integrated Circui（tHVIC）attracts a greatnumber of attention due to the merits of good isolation, high integrated density, fastrespond speed and immunity to radiation. The SOI power device is the key componentin the SOI HVIC. The key parameters of the SOI power device are breakdown voltageand specific on-resistance. The reason about the limit of breakdown voltage of SOIpower device is introducing of the Buried OXide（BOX）into the device, and thedepletion layer can’t spread into the substrate. This phenomenon causes the verticalbreakdown voltage to be very low and furthermore it degrades the breakdown voltage ofthe SOI power device. On the other hand, though some methods can reduce specificon-resistance, it causes the deterioration of the RESURF effect and causes drop ofbreakdown voltage.
According to the problems, this dissertation did a lot of work to resolve themmentioned before. The main work includes these aspects as follows:
First, combining the Enhanced Dielectric Field（ENDIF）and REBULF principle,we proposed a Non-depletion Floating Layer（NFL）N channel SOI LDMOS structure.This structure introduces a high concentration doped layer into the conventional SOIpower device. When the device is under blocking state, NFL can’t be depleted, andbecome an equi-potential layer. This equi-potential layer can modulate the electric fieldin the SOI layer and make the electric field distribution more evenly. Meanwhile, theinterface of SOI layer and BOX generates a large number of holes. According to theGauss law, the electric field in the BOX is hence significantly boosted. Futhermore, thisburied layer is pinned to a certain voltage. When the thickness of the BOX is keepingreduced, the breakdown voltage of the SOI power device maintains the same value. Thisphenomenon can effectively alleviate the Self-Heating effect in SOI power device. Thelarge number of holes at the interface of SOI layer and BOX can shield the back-gatevoltage affecting on the breakdown voltage.
Second, according to the low vertical breakdown voltage, we proposed aNon-depletion Floating Layer（NFL）P channel SOI LDMOS structure. This structure splits the BOX into two sections, with the assistance of a high concentration dopedburied layer, therefore the equivalent thickness of the BOX doubled. This breakdownvoltage of the proposed structure is boosted55%and the specific on-resistance is alsosignificantly reduced.
Third, according to the specific on-resistance of the SOI power device, weproposed the charge compensated two trenches and multiple trenches N channel SOILDMOS. The two structure share the same principle, with the enhanced RESURF effect,the devices can reduce the specific on-resistance with the high breakdown voltage.
Fourth, combining the high K material and the Super Junction structure, weproposed a high K SOI Super Junction LDMOS structure. This structure cansignificantly reduce the specific on-resistance with the high breakdown voltage. Thelayout area of the power device can hence greatly shrink.
引文
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