基于USB2.0+FPGA的密码算法硬件实现平台设计
摘要
硬件加密的诸多优势使得国内外对它的研究开发越来越重视,而密码算法硬件实现的研究更是其中的核心内容。一般来说,密码算法硬件实现研究大多使用通用型FPGA(Field Programmable Gate Array,FPGA)开发平台或者是针对某个项目特别开发的硬件电路。前者缺乏针对性并且体积较大,但是具有高灵活性;后者虽然有很强的针对性,易于控制成本,但是开发周期长,应用范围有限。本文尝试结合两者的优点,采用USB 2.0(Universal Serial Bus 2.0,USB2.0)接口主电路板和FPGA密码算法处理电路板分离的设计(两块电路板使用预定义的插槽连接),并预留足够的标准数据和控制信号接口,设计了基于USB2.0和FPGA技术的密码算法硬件实现平台。该平台不仅可以供开发设计阶段使用,也可以方便地用于演示。论文深入分析研究了USB的体系结构及其设备架构、对比分析了目前广泛使用的几种密码算法硬件实现方式,对整个平台系统架构、各个层面的划分及其解决方案给出了详细的分析与讨论,并采用VHDL(VHSICHardware Description Language,VHDL)语言实现了几个FPGA逻辑模块,对平台设计的有效性和功能进行了验证。所设计的平台具有快速的数据处理和高速的数据交换能力。
Numerous advantages of hardware encryption make people draw more attention to their research and development work at home and abroad. Moreover, hardware implementation of cipher algorithms is the core content of hardware encryption. Generally speaking, either a common FPGA-based (Field Programmable Gate Array, FPGA) development platform or a platform which is designed for a particular project can be used in the hardware implementation of cipher algorithms. The former lacks of specificity and relatively has a bigger size, but it is more flexibile; the latter is highly relevant and easy to control costs, but it has longer development cycle and limited scope of application. This paper attempts to combine the advantages of both by separating USB2.0 (Universal Serial Bus 2.0, USB2.0) main circuit board with FPGA algorithm processing circuit board (these two circuit boards can be connected by pre-defined slots) and setting aside adequate standard data and control signals interface to develop the USB2.0+FPGA-based cipher algorithms hardware implementation platform. This platform not only can be used for development, but also can be easily used for demonstration. In this paper, we studied in-depth the architecture of the USB structure and its equipment, compared and analysised several methods of cipher algorithms hardware implementation which are widely used. We also gave a detailed analysis and discussion of the entire system architecture and the division and solution of different levels. Finally, the functional verification of the entire platform is tested through some simple FPGA modules which are designed by VHDL (VHSIC Hardware Description Language, VHDL). The designed platform has the capacity of rapid data processing and high-speed data exchange.
Numerous advantages of hardware encryption make people draw more attention to their research and development work at home and abroad. Moreover, hardware implementation of cipher algorithms is the core content of hardware encryption. Generally speaking, either a common FPGA-based (Field Programmable Gate Array, FPGA) development platform or a platform which is designed for a particular project can be used in the hardware implementation of cipher algorithms. The former lacks of specificity and relatively has a bigger size, but it is more flexibile; the latter is highly relevant and easy to control costs, but it has longer development cycle and limited scope of application. This paper attempts to combine the advantages of both by separating USB2.0 (Universal Serial Bus 2.0, USB2.0) main circuit board with FPGA algorithm processing circuit board (these two circuit boards can be connected by pre-defined slots) and setting aside adequate standard data and control signals interface to develop the USB2.0+FPGA-based cipher algorithms hardware implementation platform. This platform not only can be used for development, but also can be easily used for demonstration. In this paper, we studied in-depth the architecture of the USB structure and its equipment, compared and analysised several methods of cipher algorithms hardware implementation which are widely used. We also gave a detailed analysis and discussion of the entire system architecture and the division and solution of different levels. Finally, the functional verification of the entire platform is tested through some simple FPGA modules which are designed by VHDL (VHSIC Hardware Description Language, VHDL). The designed platform has the capacity of rapid data processing and high-speed data exchange.
引文
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