功率MOSFET击穿特性研究
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摘要
击穿电压是功率半导体器件的重要参数之一。功率半导体器件在不同的应用场合下,需要不同规格的击穿电压。从100V左右的显示器驱动,几千伏的电气机车,到上万伏特的高压直流传输应用中,都可以发现功率半导体的身影。为了取得较高的击穿电压以满足不同的应用场合,人们自20世纪60年代起就开始了对击穿电压的研究。许多能够有效提高击穿电压的边端技术也陆续地被开发出来。
本文主要的目标是对以场限环技术和场板技术为主的边端结构设计进行研究,并要给出一种设计方法。本文采用由简到难的研究路线。
首先,本文详细研究了前人所提出的耐压机理、分析方法和解析方法,进行了仿真验证。仿真结果表明,无限大平面结与柱状结两类结的理论计算值与仿真结果十分接近。采用理论方法,可以精确地预测其电场分布情况以及电势分布情况。
在对各种结的研究与分析基础之上,本文又进一步研究了场限环与场板两种技术,并将其融合在一起,进行了仿真研究。仿真结果表明,场限环间距和场限环结深对击穿电压有明显的影响：击穿电压对场板长度和场氧化层厚度的变化十分敏感。场限环的结深越深,击穿电压越高；击穿电压随着场限环间距的增加会有先升高再降低的现象。场板有效降低了主结的表面电场,因此,场板越长,击穿电压越高；适当调整场板下氧化层的厚度可以使击穿电压取得较优的结果。同时,根据各种现象,可以推断出,场限环较场板有更强的击穿电压扩展能力,而场板有更强的降低表面场强的能力。
将场限环和场板融合在一起的边端结构的仿真结果表明,该场限环0场板联合边端结构可以更有效地降低表面电场强度,调节表面电场的分布,提高击穿电压。
最后,为取得较好的击穿电压结果,本文从边端结构入手,分析了击穿时的电场分布情况和电势分布情况,最终得到了场限环等电场峰值设计方法和场限环等电压分布设计方法。本文采用场限环等电压设计方法。在仿真软件中,首先设计了一个500V多场限环边端结构。为优化该结构,场板技术被引入其中,在保证击穿电压特性不退化的条件下,优化了电场分布,降低了表面电荷给器件带来的不稳定性。仿真表明,该设计方法可以方便有效地实现高压功率器件的边端设计。最终,本文在105um的有效宽度上取得了一个500V多场限环边端结构。同时,通过引入场板结构,在105um的有效宽度上也取得了优化的边端。该优化结构在使各个场限环较均衡地分担了击穿电压的同时,也利用场板的降低表面电场强度效果,尽可能地保证了击穿不发生在各个场限环的表面位置。
Breakdown voltage is one of the key properties for power semiconductor device. In the different areas, the level of breakdown voltage for power semiconductor device varies. Power semiconductor is widely used in display driver, electric train, High Voltage Direct Current transmission and so on, in which, the breakdown voltage varies from100V to10000V. In order to acquire the breakdown voltages for different areas, breakdown has been studied since1960s. And the termination techniques were developed to improve the breakdown voltage.
In this thesis, the study on floating field ring and field plate is carried on and a design methodology for termination is given. The easier topics are firstly studied and then harder ones.
At first, the research on breakdown theory, the analyzing method and analytical solution are carried on. And some simulations are also made to verify the theory. The simulation results demonstrate that the analytical solutions for planar junction and cylindrical junction are very close to simulation results. The analytical solutions can be used in predicting the electric field distribution and potential distribution.
Based on the research of basic junctions, floating field ring and field plate are studied, as well as the combination structure of floating field ring and field plate. Some simulation results are made, which can give some useful conclusions. The space between floating field rings, as well as the junction depth, has strong impact on breakdown voltage. The breakdown voltage for filed plate is sensitive to the length and the oxide thickness. The deeper the junction depth of field ring, the higher the breakdown voltage goes. With the enlargement of the field ring space, the breakdown voltage will increase and then decrease. The level of surface electric field is lowered by the field plate technique. Long field plate contributes to a higher breakdown voltage. And the optimization can also be carried on by adjusting the the thickness of the oxide underneath the field plate metal. The simulation demonstrates that field ring takes the advantage of improving the breakdown voltage and filed plate can effectively decrease the surface breakdown voltage.
The combination of the filed ring and field plate has both the advantages of reducing the surface electric field and improving the breakdown voltage.
Finally, in order to achieve the optimum breakdown voltage, the structure of the termination, the surface electric field distribution and the potential distribution are studied. The methods for the termination design are given. One is named after "equal peak electric field method" and the other one "equal potential method"
The "equal potential method" is taken to design a500V multiple floating field ring termination. And the termination is optimized by introducing the field plate. The electric field distribution is optimized and the impact of the surface charge on the device reliability is improved. The simulation results show that the "equal potential method" are available for high voltage power semiconductor device termination design.
A500V multi field rings termination is designed whose width is105um. And an optimization has been taken to make each field rings sustain the same voltage. Because of the reduction of the surface electric field, the breakdown point will be not located at the surface of each field rings.
本文主要的目标是对以场限环技术和场板技术为主的边端结构设计进行研究,并要给出一种设计方法。本文采用由简到难的研究路线。
首先,本文详细研究了前人所提出的耐压机理、分析方法和解析方法,进行了仿真验证。仿真结果表明,无限大平面结与柱状结两类结的理论计算值与仿真结果十分接近。采用理论方法,可以精确地预测其电场分布情况以及电势分布情况。
在对各种结的研究与分析基础之上,本文又进一步研究了场限环与场板两种技术,并将其融合在一起,进行了仿真研究。仿真结果表明,场限环间距和场限环结深对击穿电压有明显的影响：击穿电压对场板长度和场氧化层厚度的变化十分敏感。场限环的结深越深,击穿电压越高；击穿电压随着场限环间距的增加会有先升高再降低的现象。场板有效降低了主结的表面电场,因此,场板越长,击穿电压越高；适当调整场板下氧化层的厚度可以使击穿电压取得较优的结果。同时,根据各种现象,可以推断出,场限环较场板有更强的击穿电压扩展能力,而场板有更强的降低表面场强的能力。
将场限环和场板融合在一起的边端结构的仿真结果表明,该场限环0场板联合边端结构可以更有效地降低表面电场强度,调节表面电场的分布,提高击穿电压。
最后,为取得较好的击穿电压结果,本文从边端结构入手,分析了击穿时的电场分布情况和电势分布情况,最终得到了场限环等电场峰值设计方法和场限环等电压分布设计方法。本文采用场限环等电压设计方法。在仿真软件中,首先设计了一个500V多场限环边端结构。为优化该结构,场板技术被引入其中,在保证击穿电压特性不退化的条件下,优化了电场分布,降低了表面电荷给器件带来的不稳定性。仿真表明,该设计方法可以方便有效地实现高压功率器件的边端设计。最终,本文在105um的有效宽度上取得了一个500V多场限环边端结构。同时,通过引入场板结构,在105um的有效宽度上也取得了优化的边端。该优化结构在使各个场限环较均衡地分担了击穿电压的同时,也利用场板的降低表面电场强度效果,尽可能地保证了击穿不发生在各个场限环的表面位置。
Breakdown voltage is one of the key properties for power semiconductor device. In the different areas, the level of breakdown voltage for power semiconductor device varies. Power semiconductor is widely used in display driver, electric train, High Voltage Direct Current transmission and so on, in which, the breakdown voltage varies from100V to10000V. In order to acquire the breakdown voltages for different areas, breakdown has been studied since1960s. And the termination techniques were developed to improve the breakdown voltage.
In this thesis, the study on floating field ring and field plate is carried on and a design methodology for termination is given. The easier topics are firstly studied and then harder ones.
At first, the research on breakdown theory, the analyzing method and analytical solution are carried on. And some simulations are also made to verify the theory. The simulation results demonstrate that the analytical solutions for planar junction and cylindrical junction are very close to simulation results. The analytical solutions can be used in predicting the electric field distribution and potential distribution.
Based on the research of basic junctions, floating field ring and field plate are studied, as well as the combination structure of floating field ring and field plate. Some simulation results are made, which can give some useful conclusions. The space between floating field rings, as well as the junction depth, has strong impact on breakdown voltage. The breakdown voltage for filed plate is sensitive to the length and the oxide thickness. The deeper the junction depth of field ring, the higher the breakdown voltage goes. With the enlargement of the field ring space, the breakdown voltage will increase and then decrease. The level of surface electric field is lowered by the field plate technique. Long field plate contributes to a higher breakdown voltage. And the optimization can also be carried on by adjusting the the thickness of the oxide underneath the field plate metal. The simulation demonstrates that field ring takes the advantage of improving the breakdown voltage and filed plate can effectively decrease the surface breakdown voltage.
The combination of the filed ring and field plate has both the advantages of reducing the surface electric field and improving the breakdown voltage.
Finally, in order to achieve the optimum breakdown voltage, the structure of the termination, the surface electric field distribution and the potential distribution are studied. The methods for the termination design are given. One is named after "equal peak electric field method" and the other one "equal potential method"
The "equal potential method" is taken to design a500V multiple floating field ring termination. And the termination is optimized by introducing the field plate. The electric field distribution is optimized and the impact of the surface charge on the device reliability is improved. The simulation results show that the "equal potential method" are available for high voltage power semiconductor device termination design.
A500V multi field rings termination is designed whose width is105um. And an optimization has been taken to make each field rings sustain the same voltage. Because of the reduction of the surface electric field, the breakdown point will be not located at the surface of each field rings.
引文
[1]B.Jayant.Baliga. Fundamentals of Power Semiconductor Devices. Springer, 2008
[2]B. Jayant Baliga. Advanced Power MOSFET Concepts. Springer, 2010
[3]Krishna Shenai. A 55-V, 0.2-mO · cm2 Vertical Trench Power MOSFET. Electron Device Letters. 1991,12(3):108-110
[4]Tsengyou Syau, Prasad Venkatraman, and B.Jayant.Baliga. Comparison of Ultralow Specific On-Resistance UMOSFET Structures:The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's. Transactions on Electron Devices.1994, 41(5):800-808
[5]Ying Wang, Hai-Fan Hu, Wen-Li Jiao, and Chao Cheng. Gate Enhanced Power UMOSFET With Ultralow On-Resistance. Electron Device Letters.2010,31(4): 338-340
[6]M. Darwish, C. Yue, K.H. Lui, F. Giles, B. Chan, K.-I. Chen, D. Pattanayak, Q. Chen, K. Terrill and K. Owyang. W-gated trench power MOSFET (WFET). Circuits Devices and Systems.2004,151(3):238-242
[7]Qimeng Jiang, Minzhi Wang, and Xingbi Chen. A High-Speed Deep-Trench MOSFET With a Self-Biased Split Gate. Transactions on electron devices.2010, 57(8):1972-1977
[8]B. Jayant Baliga, B. Tech. High-voltage Device Termination Techniques:A comparative review. Solid-State and Electron Devices.1982,129(5):173-179
[9]Dejan Krizaj, Slavko Amon, Corinne Mingues, and Georges Charitat. Spiral Junction Termination. Transactions on electron devices.1997,44(11):2002-2010
[10]Andrew S. Grove, Otto Leistiko, JR. and William W. Hooper. Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p-n Junctions. Transactions on Electron Devices.1967,14(3):157-162
[11]F. CONTI and M. CONTI. Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate. Solid-State Electronics.1972,15:93-105
[12]B. Jayant Baliga. Analytical Solutions For the Breakdown Voltage of Abrupt Cylindrical and Spherical Junctions. Solid-State Electronics.1976,19(9):739-744
[13]Adler, M.S, Temple V.A.K., Ferro A.P., Rustay R.C. Theory and Breakdown Voltage for Planar Devices with A Single Field Limiting Ring. Transactions on Electron Devices.1977,24(2):107-113
[14]Antoine A. Tamer, Ken Rauch and John L. Moll. Numerical Comparison of DMOS, VMOS, and UMOS Power Transistors. Transactions on Electron Devices.1983, 30(1):73-76
[15]Tomowki Tanaka, Yasuhiro Mochizuki and Masahiro Okamura. Analysis of a Junction Termination Structure for Ideal Breakdown Voltage in p-n Junction Devices. Transactions on Electron Devices.1980,27(1):261-265
[16]Mohamed N. Darwish and Kenneth Board. Optimization of Breakdown Voltage and On-Resistance of VDMOS Transistors. Transactions on Electron Devices.1984, 31(12):1769-1773
[17]D. Jaume, G. Charitat, J. M. Reynes, and P. Rossel. High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers. Transactions on Electron Devices.1991, 38(7):1681-1684
[18]Krishna Shenai. Optimized Trench MOSFET Technologies for Power Devices. Transactions on Electron Devices.1992,39(6):1435-1443
[19]C. Basavana Goud, and K. N. Bhat. Two-Dimensional Analysis and Design Considerations of High-Voltage Planar Junctions Equipped with Field Plate and Guard Ring. Transactions on Electron Devices.1991,38(6):1497-1504
[20]B. Jayant Baliga, Tsengyou Syau, and Prasad Venkatraman. The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET. Electron Devcie Letters.1992,13(8):427-429
[21]Satoshi Matsumoto, Terukazu Ohno, Hiromu Ishii, and Hideo Yoshino. A High-Performance Self-Aligned UMOSFET With a Vertical Trench Contact Structure. Transactions on Electron Devices.1994,41(5):814-818
[22]Florin Udrea and Gehan A. J. and Amaratunga. Theoretical and Numerical Comparison Between DMOS and Trench Technologies for Insulated Gate Bipolar Transistors. Transactions on Electron Devices.1995,42(7):1356-1366
[23]B. Jayant Baliga. Trends in Power Semiconductor Devices. Transactions on Electron Devices.1996,43(10):1717-1731
[24]B. Jayant Baliga. The Future of Power Semiconductor Device Technology. Proceedings of IEEE.2001,89(6):822-832
[25]Maurizio Boscardin, Luciano Bosisio, Andrea Candelori, Gian Franco Dalla Betta, Selenia Dittongo,Paolo Gregori, Claudio Piemonte, Irina Rachevskaia, Sabina Ronchin, and Nicola Zorzi. An Improved Termination Structure for Silicon Radiation Detectors With All-P-Type Multi-guard and Cut-Line Implants. Transactions on Nuclear Science. 2003,50(4):1001-1007
[26]Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, and Amitava Bose. A Floating RESURF (FRESURF) LD-MOSFET Device Concept. Electron Device Letters.2003, 24(10):664-666
[27]F.-T. Chien, C.-N. Liao, C.-L. Wang, H.-C. Chiu and Y.-T. Tsai. Low on-resistance trench power MOSFETs design. Electronic Letters.2008,44(3):232-234
[28]Qinsong Qian, Weifeng Sun, Member, IEEE,JingZhu,andSiyangLiu. A Novel Charge-Imbalance Termination for Trench Superjunction VDMOS. Electron Device Letters.2010,31(12):1434-1436
[29]Yoshiya Kawashima, Hisao Inomata, Koichi Murakawa, and Yoshinao Miura. Narrow-Pitch N-Channel Superjunction UMOSFET for 40-60 V Automotive Application.22nd ISPSD, Hiroshima, 2010. IEEE:329-332
[30]F. Udrea, T. Trajkovic, J. Thomsonb, L. Coulbeckb, P.R. Waindb, G.A.J. Amaratunga and P. Taylorb. Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept-experimental demonstration at 6.5 kV. ISPSD 2001, Osaka. IEEE:129-132
[31]L. Theolier, H. Mahfoz-Kotb, K. Isoird, F. Morancho. A new junction termination technique:the Deep Trench Termination (DT2). ISPSD 2009, Barcelona. IEEE: 176-179
[32]Shigeto Honda, Ryoich Fujii, Tsuyoshi Kawakami, Seiji Fujioka, Atsushi Narazaki, Kaoru Motonami. A concept of a novel edge termination technique:Junction Termination(RJT). 22nd ISPSD, Hiroshima, 2010. IEEE:111-114
[33]Appels J.A. and Vaes, H.M.J. High voltage Thin Layer Devices(RESURF devices). Electron Devices Meeting, 1979. IEEE: 238-241
[34]Michael Amato and Vladimir Rumennik. Comparison of Lateral and Vertical DMOS Specific On-Resistance. IEDM, 1985. IEEE: 736-739
[35]Dejan Kritaj, Sass Sokolic and Slavko Amon. A New Approach to Field-Plate Junction Termination Modeling. 6th Electrotechnical Conference, 1991. IEEE: 91-94
[36]B. Jayant Baliga. MOS Devices For Power Electronic Applications. Solid-State Device Research Conference, 1998. IEEE: 81-87
[37]Subhas chandra Bose J.V, M. M. De Souza, E.M. Sankara Narayanan, 0. Spulber and M. Sweet. Influence of A Shallow P+ Offset Region on A Novel Edge Termination Technique Using Lightly Doped P-Rings. Semiconductor Conference, 1999. IEEE: 63-66
[38]Adriaan W. Ludikhuize. A Review of RESURF Technology. ISPSD, Toulouse, France, 2000. IEEE: 11-18
[39]S. Hidalgo, D. Flores, I. Obieta, I. Mazarredo, J.Millan. Study of A Positive Bevel Angle Edge Termination For High Voltage Power Structures. Semiconductor Conference, 2002. IEEE:261-264
[40]Chanho Park, Jinmyung Kim, Taehoon Kim, and Deok J. Kim. Deep Trench Terminations Using ICP RIE for Ideal Breakdown Voltages. ISPSD, Cambridge, UK, 2003. IEEE: 199-202
[41]T. Kurosaki, H. Shishido, M. Kitada, K. Oshima, S. Kunori and A. Sugai. 200V Multi RESURF Trench MOSFET(MR-TMOS). ISPSD, Cambridge, UK, 2003. IEEE: 211-214
[42]Victor A. Emelyanov, Valentine V. Baranov, Ivan I. Rubtsevich and Dmitry L Anufriev.Simulation and Optimization of Power DMOS Transistors Parameters. Electronics System integration Technology Conference, Dresden, Germany,2006. IEEE: 666-670
[43]Kamibaba R., Takahama K., Omura I. Design of trench termination for high voltage devices. ISPSD, Hiroshima, 2010. IEEE: 107-110
[44]Chien-Nan Liao, Ping-hung Lai, Tien-Chun Li, Feng-Tso Chien, and Yao-Tsung Tsai. Comparison of Termination Structure Design by Device Simulator. International Symposium on Power Electronics for Distributed Generation Systems, Hefei, China, 2010. IEEE: 530-533
[45]Siemieniec, R.; Hirler, F.; Geissler, C; Space-saving edge-termination structures for vertical charge compensation devices. EPE, Barcelona, Spain, 2009. IEEE: 1-10
[46]Fairchild Korea Semiconductor. MOSFET Basics. Fairchild Semiconductor. 1999.
[47]陈星弼.功率MOSFET与高压集成电路.东南大学出版社,1990
[48]施敏.半导体器件物理与工艺.赵鹤鸣,钱敏,黄秋萍.第二版.苏州大学出版社,2002
[49]曾云.微电子器件基础.湖南大学出版社,2005
[50]Gray S.May,施敏.半导体制造基础.代永平.人民邮电出版社,2007
[51]张一工,肖湘宁.现代电力电子技术原理与应用.科学出版社,1999
[52]胡佳贤,韩雁,张世峰,张斌,韩成功.高压VDMOS结终端技术研究.半导体技术.2010.35：52-54
[53]宋文斌,蔡小五.一种新型高压功率器件终端技术.微电子学.2011,41(4)：567-569
[54]孙华芳,荆吉利,孙伟锋.六角形超结VDMOS器件的终端结构设计.电子器件.2011,33(4)：403-406
[55]殷丽,王传敏.高压功率FRED结终端保护技术及其组合优化设计.电力电子.2010.2：51-55
[56]高东岳.一种600V VDMOS终端保护环结构的设计.中国集成电路.2009,123：58-61
[57]孙伟锋,王佳宁,易扬波.单个浮置场限环终端结构击穿电压模型.微电子学.2009,39(6)：848-851
[58]张彦飞,吴郁,游雪兰,亢宝位.硅材料功率半导体器件结终端技术的新发展.电子器件.2009,32(3)：538-546
[59]石广源,李永亮,李严,高嵩.新型结终端技术.辽宁大学学报自然科学版.2006,33(2)：172-174
[60]张雯,张俊松.功率VDMOSFET结终端技术研究.辽宁大学学报自然科学版.2006,33(2)：180-183
[61]吴正元,张硕,董晓敏,于军.高压VDMOS场板终端技术的研究.华中理工大学学报.1999,27(4)：43-45
[62]王彩琳,于凯.沟槽负斜角终端结构的耐压机理与击穿特性分析.固体电子学研究与进展.2011,31(4)：345-349
[63]荆吉利,孙伟锋.超结MOSFET功率器件的终端技术分析.固体电子学研究与进展.2009,29(4)：542-546
[64]陈利,李开航,郭东辉.高压功率MOSFET结终端保护技术及其组合优化设计现代电子技术.2006,11：71-74
[65]何进,张兴,黄如,王阳元.平面结场板结构表面场分布的二维解析.半导体学报.2001,22(7)：915-918
[66]梁苏军,罗晋生.高压终端结构场分析边界元数值方法.半导体学报.1993,14(7)：416-422
[67]秦祖新,刘三清.MOS型硅功率器件平面终端结构. 微电子学.1992,22(2)：37-44
[68]刘三清,秦祖新,应建华500V VDMOS功率器件终端结构设计.微电子学.1991,21(5)：40-44
[69]苏延芬,刘英坤Trench MOSFET的研究与进展.半导体技术.2007,2(4)：277-280
[70]陈龙,沈克强VDMOS场效应晶体管的研究与进展.电子器件.2006,29(1)：290-295
[71]冯玉春.功率半导体器件的发展和市场.半导体技术.2000,25(6)：12-15
[72]何进,陈星弼,王新VDMOS均匀掺杂外延区优化设计的简单理论.电子器件.1999,22(3)：143-148
[73]尹光,周涛,石广源.晶体管二次击穿特性研究.辽宁大学学报自然科学版.2009.36(1)：30-34
[2]B. Jayant Baliga. Advanced Power MOSFET Concepts. Springer, 2010
[3]Krishna Shenai. A 55-V, 0.2-mO · cm2 Vertical Trench Power MOSFET. Electron Device Letters. 1991,12(3):108-110
[4]Tsengyou Syau, Prasad Venkatraman, and B.Jayant.Baliga. Comparison of Ultralow Specific On-Resistance UMOSFET Structures:The ACCUFET, EXTFET, INVFET, and Conventional UMOSFET's. Transactions on Electron Devices.1994, 41(5):800-808
[5]Ying Wang, Hai-Fan Hu, Wen-Li Jiao, and Chao Cheng. Gate Enhanced Power UMOSFET With Ultralow On-Resistance. Electron Device Letters.2010,31(4): 338-340
[6]M. Darwish, C. Yue, K.H. Lui, F. Giles, B. Chan, K.-I. Chen, D. Pattanayak, Q. Chen, K. Terrill and K. Owyang. W-gated trench power MOSFET (WFET). Circuits Devices and Systems.2004,151(3):238-242
[7]Qimeng Jiang, Minzhi Wang, and Xingbi Chen. A High-Speed Deep-Trench MOSFET With a Self-Biased Split Gate. Transactions on electron devices.2010, 57(8):1972-1977
[8]B. Jayant Baliga, B. Tech. High-voltage Device Termination Techniques:A comparative review. Solid-State and Electron Devices.1982,129(5):173-179
[9]Dejan Krizaj, Slavko Amon, Corinne Mingues, and Georges Charitat. Spiral Junction Termination. Transactions on electron devices.1997,44(11):2002-2010
[10]Andrew S. Grove, Otto Leistiko, JR. and William W. Hooper. Effect of Surface Fields on the Breakdown Voltage of Planar Silicon p-n Junctions. Transactions on Electron Devices.1967,14(3):157-162
[11]F. CONTI and M. CONTI. Surface Breakdown in Silicon Planar Diodes Equipped with Field Plate. Solid-State Electronics.1972,15:93-105
[12]B. Jayant Baliga. Analytical Solutions For the Breakdown Voltage of Abrupt Cylindrical and Spherical Junctions. Solid-State Electronics.1976,19(9):739-744
[13]Adler, M.S, Temple V.A.K., Ferro A.P., Rustay R.C. Theory and Breakdown Voltage for Planar Devices with A Single Field Limiting Ring. Transactions on Electron Devices.1977,24(2):107-113
[14]Antoine A. Tamer, Ken Rauch and John L. Moll. Numerical Comparison of DMOS, VMOS, and UMOS Power Transistors. Transactions on Electron Devices.1983, 30(1):73-76
[15]Tomowki Tanaka, Yasuhiro Mochizuki and Masahiro Okamura. Analysis of a Junction Termination Structure for Ideal Breakdown Voltage in p-n Junction Devices. Transactions on Electron Devices.1980,27(1):261-265
[16]Mohamed N. Darwish and Kenneth Board. Optimization of Breakdown Voltage and On-Resistance of VDMOS Transistors. Transactions on Electron Devices.1984, 31(12):1769-1773
[17]D. Jaume, G. Charitat, J. M. Reynes, and P. Rossel. High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers. Transactions on Electron Devices.1991, 38(7):1681-1684
[18]Krishna Shenai. Optimized Trench MOSFET Technologies for Power Devices. Transactions on Electron Devices.1992,39(6):1435-1443
[19]C. Basavana Goud, and K. N. Bhat. Two-Dimensional Analysis and Design Considerations of High-Voltage Planar Junctions Equipped with Field Plate and Guard Ring. Transactions on Electron Devices.1991,38(6):1497-1504
[20]B. Jayant Baliga, Tsengyou Syau, and Prasad Venkatraman. The Accumulation-Mode Field-Effect Transistor: A New Ultralow On-Resistance MOSFET. Electron Devcie Letters.1992,13(8):427-429
[21]Satoshi Matsumoto, Terukazu Ohno, Hiromu Ishii, and Hideo Yoshino. A High-Performance Self-Aligned UMOSFET With a Vertical Trench Contact Structure. Transactions on Electron Devices.1994,41(5):814-818
[22]Florin Udrea and Gehan A. J. and Amaratunga. Theoretical and Numerical Comparison Between DMOS and Trench Technologies for Insulated Gate Bipolar Transistors. Transactions on Electron Devices.1995,42(7):1356-1366
[23]B. Jayant Baliga. Trends in Power Semiconductor Devices. Transactions on Electron Devices.1996,43(10):1717-1731
[24]B. Jayant Baliga. The Future of Power Semiconductor Device Technology. Proceedings of IEEE.2001,89(6):822-832
[25]Maurizio Boscardin, Luciano Bosisio, Andrea Candelori, Gian Franco Dalla Betta, Selenia Dittongo,Paolo Gregori, Claudio Piemonte, Irina Rachevskaia, Sabina Ronchin, and Nicola Zorzi. An Improved Termination Structure for Silicon Radiation Detectors With All-P-Type Multi-guard and Cut-Line Implants. Transactions on Nuclear Science. 2003,50(4):1001-1007
[26]Vishnu Khemka, Vijay Parthasarathy, Ronghua Zhu, and Amitava Bose. A Floating RESURF (FRESURF) LD-MOSFET Device Concept. Electron Device Letters.2003, 24(10):664-666
[27]F.-T. Chien, C.-N. Liao, C.-L. Wang, H.-C. Chiu and Y.-T. Tsai. Low on-resistance trench power MOSFETs design. Electronic Letters.2008,44(3):232-234
[28]Qinsong Qian, Weifeng Sun, Member, IEEE,JingZhu,andSiyangLiu. A Novel Charge-Imbalance Termination for Trench Superjunction VDMOS. Electron Device Letters.2010,31(12):1434-1436
[29]Yoshiya Kawashima, Hisao Inomata, Koichi Murakawa, and Yoshinao Miura. Narrow-Pitch N-Channel Superjunction UMOSFET for 40-60 V Automotive Application.22nd ISPSD, Hiroshima, 2010. IEEE:329-332
[30]F. Udrea, T. Trajkovic, J. Thomsonb, L. Coulbeckb, P.R. Waindb, G.A.J. Amaratunga and P. Taylorb. Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept-experimental demonstration at 6.5 kV. ISPSD 2001, Osaka. IEEE:129-132
[31]L. Theolier, H. Mahfoz-Kotb, K. Isoird, F. Morancho. A new junction termination technique:the Deep Trench Termination (DT2). ISPSD 2009, Barcelona. IEEE: 176-179
[32]Shigeto Honda, Ryoich Fujii, Tsuyoshi Kawakami, Seiji Fujioka, Atsushi Narazaki, Kaoru Motonami. A concept of a novel edge termination technique:Junction Termination(RJT). 22nd ISPSD, Hiroshima, 2010. IEEE:111-114
[33]Appels J.A. and Vaes, H.M.J. High voltage Thin Layer Devices(RESURF devices). Electron Devices Meeting, 1979. IEEE: 238-241
[34]Michael Amato and Vladimir Rumennik. Comparison of Lateral and Vertical DMOS Specific On-Resistance. IEDM, 1985. IEEE: 736-739
[35]Dejan Kritaj, Sass Sokolic and Slavko Amon. A New Approach to Field-Plate Junction Termination Modeling. 6th Electrotechnical Conference, 1991. IEEE: 91-94
[36]B. Jayant Baliga. MOS Devices For Power Electronic Applications. Solid-State Device Research Conference, 1998. IEEE: 81-87
[37]Subhas chandra Bose J.V, M. M. De Souza, E.M. Sankara Narayanan, 0. Spulber and M. Sweet. Influence of A Shallow P+ Offset Region on A Novel Edge Termination Technique Using Lightly Doped P-Rings. Semiconductor Conference, 1999. IEEE: 63-66
[38]Adriaan W. Ludikhuize. A Review of RESURF Technology. ISPSD, Toulouse, France, 2000. IEEE: 11-18
[39]S. Hidalgo, D. Flores, I. Obieta, I. Mazarredo, J.Millan. Study of A Positive Bevel Angle Edge Termination For High Voltage Power Structures. Semiconductor Conference, 2002. IEEE:261-264
[40]Chanho Park, Jinmyung Kim, Taehoon Kim, and Deok J. Kim. Deep Trench Terminations Using ICP RIE for Ideal Breakdown Voltages. ISPSD, Cambridge, UK, 2003. IEEE: 199-202
[41]T. Kurosaki, H. Shishido, M. Kitada, K. Oshima, S. Kunori and A. Sugai. 200V Multi RESURF Trench MOSFET(MR-TMOS). ISPSD, Cambridge, UK, 2003. IEEE: 211-214
[42]Victor A. Emelyanov, Valentine V. Baranov, Ivan I. Rubtsevich and Dmitry L Anufriev.Simulation and Optimization of Power DMOS Transistors Parameters. Electronics System integration Technology Conference, Dresden, Germany,2006. IEEE: 666-670
[43]Kamibaba R., Takahama K., Omura I. Design of trench termination for high voltage devices. ISPSD, Hiroshima, 2010. IEEE: 107-110
[44]Chien-Nan Liao, Ping-hung Lai, Tien-Chun Li, Feng-Tso Chien, and Yao-Tsung Tsai. Comparison of Termination Structure Design by Device Simulator. International Symposium on Power Electronics for Distributed Generation Systems, Hefei, China, 2010. IEEE: 530-533
[45]Siemieniec, R.; Hirler, F.; Geissler, C; Space-saving edge-termination structures for vertical charge compensation devices. EPE, Barcelona, Spain, 2009. IEEE: 1-10
[46]Fairchild Korea Semiconductor. MOSFET Basics. Fairchild Semiconductor. 1999.
[47]陈星弼.功率MOSFET与高压集成电路.东南大学出版社,1990
[48]施敏.半导体器件物理与工艺.赵鹤鸣,钱敏,黄秋萍.第二版.苏州大学出版社,2002
[49]曾云.微电子器件基础.湖南大学出版社,2005
[50]Gray S.May,施敏.半导体制造基础.代永平.人民邮电出版社,2007
[51]张一工,肖湘宁.现代电力电子技术原理与应用.科学出版社,1999
[52]胡佳贤,韩雁,张世峰,张斌,韩成功.高压VDMOS结终端技术研究.半导体技术.2010.35：52-54
[53]宋文斌,蔡小五.一种新型高压功率器件终端技术.微电子学.2011,41(4)：567-569
[54]孙华芳,荆吉利,孙伟锋.六角形超结VDMOS器件的终端结构设计.电子器件.2011,33(4)：403-406
[55]殷丽,王传敏.高压功率FRED结终端保护技术及其组合优化设计.电力电子.2010.2：51-55
[56]高东岳.一种600V VDMOS终端保护环结构的设计.中国集成电路.2009,123：58-61
[57]孙伟锋,王佳宁,易扬波.单个浮置场限环终端结构击穿电压模型.微电子学.2009,39(6)：848-851
[58]张彦飞,吴郁,游雪兰,亢宝位.硅材料功率半导体器件结终端技术的新发展.电子器件.2009,32(3)：538-546
[59]石广源,李永亮,李严,高嵩.新型结终端技术.辽宁大学学报自然科学版.2006,33(2)：172-174
[60]张雯,张俊松.功率VDMOSFET结终端技术研究.辽宁大学学报自然科学版.2006,33(2)：180-183
[61]吴正元,张硕,董晓敏,于军.高压VDMOS场板终端技术的研究.华中理工大学学报.1999,27(4)：43-45
[62]王彩琳,于凯.沟槽负斜角终端结构的耐压机理与击穿特性分析.固体电子学研究与进展.2011,31(4)：345-349
[63]荆吉利,孙伟锋.超结MOSFET功率器件的终端技术分析.固体电子学研究与进展.2009,29(4)：542-546
[64]陈利,李开航,郭东辉.高压功率MOSFET结终端保护技术及其组合优化设计现代电子技术.2006,11：71-74
[65]何进,张兴,黄如,王阳元.平面结场板结构表面场分布的二维解析.半导体学报.2001,22(7)：915-918
[66]梁苏军,罗晋生.高压终端结构场分析边界元数值方法.半导体学报.1993,14(7)：416-422
[67]秦祖新,刘三清.MOS型硅功率器件平面终端结构. 微电子学.1992,22(2)：37-44
[68]刘三清,秦祖新,应建华500V VDMOS功率器件终端结构设计.微电子学.1991,21(5)：40-44
[69]苏延芬,刘英坤Trench MOSFET的研究与进展.半导体技术.2007,2(4)：277-280
[70]陈龙,沈克强VDMOS场效应晶体管的研究与进展.电子器件.2006,29(1)：290-295
[71]冯玉春.功率半导体器件的发展和市场.半导体技术.2000,25(6)：12-15
[72]何进,陈星弼,王新VDMOS均匀掺杂外延区优化设计的简单理论.电子器件.1999,22(3)：143-148
[73]尹光,周涛,石广源.晶体管二次击穿特性研究.辽宁大学学报自然科学版.2009.36(1)：30-34