高压功率MOSFET终端结构击穿特性的研究
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摘要
耐压能力是功率MOSFET的最重要性能,通常在器件的应用选型中,击穿电压是作为首要的考虑指标。对于击穿电压小于100V的VDMOS器件,达到规格要求的击穿电压难度不大,对于这类器件的耐压设计主要是考虑其与导通电阻之间的折衷与优化；而对于高压VDMOS器件而言,提高击穿电压是芯片设计的最难点,因为在高逆向偏压下,在最外圈的元胞区如果没有保护措施则会导致芯片的提前击穿。终端结构的作用就是,利用特别设计的横向结构将漏源之间的高电势差,从元胞平缓过渡到芯片边缘。一般而言,在高压VDMOS的设计中,只要终端结构的击穿电压达到了设计规格,则芯片的整体耐压就能得到保证。
本论文研究的是高压VDMOS的终端结构。作为高压器件的典型规格,耐压为600V的VDMOS终端结构是本论文的优化与设计目标。
首先研究雪崩击穿的机制及其发生条件,代入平行平面结与圆柱结两种模型得到击穿电压的解析方程。平行平面结模型适用于外延片掺杂浓度与厚度的参数选取,通过计算得到的外延片参数与仿真值误差在0.3%,并且得到的是导通电阻与击穿电压折衷的最优解。圆柱结模型应用于主结边缘的击穿电压计算,获得结曲率半径与击穿电压之间呈正比的强烈关系。该结论是多种基本的终端技术原理的根基,特别是场限环技术及其他结终端技术,就是通过增大耗尽层曲率半径的方式获得高击穿电压。
接着对多场限环场板复合的终端结构进行设计与优化,分别对单场限环和单场板的模型进行仿真,探究其形状与位置的改变导致终端电性能特性的变化,包括表面电场分布,碰撞电离率分布,耗尽层曲线形状以及击穿电压的变化趋势等。这将指导复合结构终端的调整与优化。通过TCAD仿真软件ISE优化得到的6场限环场板复合终端耐压为690.2V,终端宽度为150μm。
本论文还基于表面变形的原理设计了浅沟槽负斜坡终端结构。优化后得到宽度为126.7μm,击穿电压为724.8V的终端结构,达到了同外延材料同制程条件下元胞区击穿电压的90%。
具有应用意义的终端结构还需考虑到其面积大小,因为终端结构的唯一功能就是使芯片的击穿电压尽量接近于元胞区耐压。在芯片正常工作时,终端并不提供电流通路,所以终端面积过大会造成同成本下芯片的导通电阻增加,同时增加的还有漏电流。本论文设计的两种终端结构中,浅沟槽负斜坡的终端宽度比多场限环场板结构的小得多,但是对工艺技术的要求有所增加。
Blocking capacity is the key parameter of Power MOSFET. Usually in the device selection, the breakdown voltage is considered as a primary indicator. For breakdown voltage less than100V VDMOS devices, it is not difficult to design to meet the target breakdown voltage, which mainly focus on the trade-off between on resistance and breakdown voltage. But for high voltage VDMOS devices, to improve the breakdown voltage is the most difficult work of the chip design. Under high reverse bias, if no protective measures in the outer ring of the cell area will lead to chip breakdown ahead. The role of the termination is the use of the special design of a lateral structure for gentle transition of the high electric potential difference between the drain and the source. Generally, as long as the termination breakdown voltage reaches the target specifications, then the overall blocking capacity of the chip can be guaranteed.
This thesis is the research of the high voltage VDMOS termination. Typical specifications as a high voltage device,600V VDMOS termination had been optimized design in this work.
First of all, the mechanism of avalanche breakdown occuring conditions was been studied, substituted into the electric field equation of each model of the plane junction and the cylindrical junction, then the breakdown voltage analytical solution had been got. Infinite plane junction model is suitable for the selection of epitaxial wafers doping concentration and thickness, and what we get is the optimal solution between on-resistance and breakdown voltage trade-off.
Cylindrical junction model is applied to calculate the breakdown voltage of the edge of the main junction, the junction curvature radius and the breakdown voltage were calculated to be direct proportion. This theory is the foundation of a variety of basic principles of termination technology, especially the field limiting ring technique and other junction termination technique, that is, by increasing the curvature radius of the depletion layer to get a high breakdown voltage.
Then design and optimize the structure of Multi-FLR-FP termination. Single field limiting ring and a single field plate model had been simulated to explore the shape and location led to changes in the characteristics of the termination electrical properties, including the surface electric field distribution, the impact ionization rate distribution, the depletion boundary shape, and breakdown voltage of the trend. This will guide the adjustment and optimization of the composite structure of the termination. After works of simulation with TCAD software ISE, optimized Multi-FLR-FP structure termination had been designed, which breakdown voltage is690.2V, and the width is150μm.
In this paper, a shallow trench negative slope termination structure had also been designed, which was based on the principle of surface deformation. Get a width of126.7μm, and the breakdown voltage of724.8V termination structure.
本论文研究的是高压VDMOS的终端结构。作为高压器件的典型规格,耐压为600V的VDMOS终端结构是本论文的优化与设计目标。
首先研究雪崩击穿的机制及其发生条件,代入平行平面结与圆柱结两种模型得到击穿电压的解析方程。平行平面结模型适用于外延片掺杂浓度与厚度的参数选取,通过计算得到的外延片参数与仿真值误差在0.3%,并且得到的是导通电阻与击穿电压折衷的最优解。圆柱结模型应用于主结边缘的击穿电压计算,获得结曲率半径与击穿电压之间呈正比的强烈关系。该结论是多种基本的终端技术原理的根基,特别是场限环技术及其他结终端技术,就是通过增大耗尽层曲率半径的方式获得高击穿电压。
接着对多场限环场板复合的终端结构进行设计与优化,分别对单场限环和单场板的模型进行仿真,探究其形状与位置的改变导致终端电性能特性的变化,包括表面电场分布,碰撞电离率分布,耗尽层曲线形状以及击穿电压的变化趋势等。这将指导复合结构终端的调整与优化。通过TCAD仿真软件ISE优化得到的6场限环场板复合终端耐压为690.2V,终端宽度为150μm。
本论文还基于表面变形的原理设计了浅沟槽负斜坡终端结构。优化后得到宽度为126.7μm,击穿电压为724.8V的终端结构,达到了同外延材料同制程条件下元胞区击穿电压的90%。
具有应用意义的终端结构还需考虑到其面积大小,因为终端结构的唯一功能就是使芯片的击穿电压尽量接近于元胞区耐压。在芯片正常工作时,终端并不提供电流通路,所以终端面积过大会造成同成本下芯片的导通电阻增加,同时增加的还有漏电流。本论文设计的两种终端结构中,浅沟槽负斜坡的终端宽度比多场限环场板结构的小得多,但是对工艺技术的要求有所增加。
Blocking capacity is the key parameter of Power MOSFET. Usually in the device selection, the breakdown voltage is considered as a primary indicator. For breakdown voltage less than100V VDMOS devices, it is not difficult to design to meet the target breakdown voltage, which mainly focus on the trade-off between on resistance and breakdown voltage. But for high voltage VDMOS devices, to improve the breakdown voltage is the most difficult work of the chip design. Under high reverse bias, if no protective measures in the outer ring of the cell area will lead to chip breakdown ahead. The role of the termination is the use of the special design of a lateral structure for gentle transition of the high electric potential difference between the drain and the source. Generally, as long as the termination breakdown voltage reaches the target specifications, then the overall blocking capacity of the chip can be guaranteed.
This thesis is the research of the high voltage VDMOS termination. Typical specifications as a high voltage device,600V VDMOS termination had been optimized design in this work.
First of all, the mechanism of avalanche breakdown occuring conditions was been studied, substituted into the electric field equation of each model of the plane junction and the cylindrical junction, then the breakdown voltage analytical solution had been got. Infinite plane junction model is suitable for the selection of epitaxial wafers doping concentration and thickness, and what we get is the optimal solution between on-resistance and breakdown voltage trade-off.
Cylindrical junction model is applied to calculate the breakdown voltage of the edge of the main junction, the junction curvature radius and the breakdown voltage were calculated to be direct proportion. This theory is the foundation of a variety of basic principles of termination technology, especially the field limiting ring technique and other junction termination technique, that is, by increasing the curvature radius of the depletion layer to get a high breakdown voltage.
Then design and optimize the structure of Multi-FLR-FP termination. Single field limiting ring and a single field plate model had been simulated to explore the shape and location led to changes in the characteristics of the termination electrical properties, including the surface electric field distribution, the impact ionization rate distribution, the depletion boundary shape, and breakdown voltage of the trend. This will guide the adjustment and optimization of the composite structure of the termination. After works of simulation with TCAD software ISE, optimized Multi-FLR-FP structure termination had been designed, which breakdown voltage is690.2V, and the width is150μm.
In this paper, a shallow trench negative slope termination structure had also been designed, which was based on the principle of surface deformation. Get a width of126.7μm, and the breakdown voltage of724.8V termination structure.
引文
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[2]B. Jayant Baliga. Advanced Power MOSFET Concepts. Springer,2010
[3]B. Jayant Baliga. The Future of Power Semiconductor Device Technology. Proceedings of IEEE.2001,89 (6):822-832
[4]B. Jayant Baliga. MOS Devices For Power Electronic Applications. Solid-State Device Research Conference,1998. IEEE:81-87
[5]M. Darwish, C. Yue, K.H. Lui, F. Giles, B. Chan, K.-I. Chen, D. Pattanayak, Q. Chen, K. Terrill and K. Owyang. W-gated trench power MOSFET (WFET). Circuits Devices and Systems.2004,151(3):238-242
[6]B. Jayant Baliga, B. Tech. High-voltage Device Termination Techniques:A comparative review. Solid-State and Electron Devices.1982,129(5):173-179
[7]S. M. Sze, Physics of Semiconductor Devices 2nd. Edition, Ch.1, John Wiley and Sons, New York. Chichester. Brisbane. Toronto.Singapore,1981.
[8]B. Jayant Baliga. Analytical Solutions For the Breakdown Voltage of Abrupt Cylindrical and Spherical Junctions. Solid-State Electronics.1976,19(9):739-744
[9]Krishna Shenai. A 55-V,0.2-mΩ·cm2 Vertical Trench Power MOSFET. Electron Device Letters.1991,12(3):108-110
[10]Tarui Y, Hayasui Y, Sekigawa T. Diffusion self-aligned enhance-depletion MOS-IC. Proceedings of the 2nd Conference Solid State Devices, Tokyo, Japan.1970:157-162.
[11]Qinsong Qian, Weifeng Sun, Member, IEEE, JingZhu,andSiyangLiu. A Novel Charge-Imbalance Termination for Trench Super Junction VDMOS. Electron Device Letters.2010,31 (12):1434-1436.
[12]Yoshiya Kawashima, Hisao Inomata, Koichi Murakawa, and Yoshinao Miura. Narrow-Pitch N-Channel Super Junction UMOSFET for 40-60 V Automotive Application.22nd ISPSD, Hiroshima,2010. IEEE:329-332.
[13]F. Udrea, T. Trajkovic, J. Thomsonb, L. Coulbeckb, P.R. Waindb, G.A.J. Amaratunga and P. Taylorb. Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept-experimental demonstration at 6.5 kV. ISPSD 2001, Osaka. IEEE:129-132.
[14]Chen X B. Optimum design parameters for different pattern of CB-structure. Chinese Journal of Electronics,2000,9 (1):6-11.
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