一种新型低功耗智能漏电保护器芯片的设计
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摘要
在国家的扶助下，我国在漏电保护器上已是世界产量最大的国家，但是技术含量不高，质量欠佳。由于国内集成电路产业的严重滞后，目前，国内市场上这方面没有任何一块集成电路是中国人自己设计的，被国外处于垄断地位。漏电保护器因为竞争激烈，只能是薄利多销。在无竞争的状况下，使用国外的芯片直接挤占了保护器产品的利润空间。同时由于脱离中国的市场，国外的芯片也不能针对国内市场进行有效的优化，导致技术不能得到升级，或是成本不能下降。因此，我国是漏电保护器的产量大国，不是强国，急待提高质量。
本论文设计了一种新型漏电开关保护芯片，在功能上可以取代目前占市场主导地位的日本三菱公司的M54133FP/GP。和采用双极工艺的纯模拟电路芯片M54133FP/GP不同，本芯片采用的是数模混合的CMOS工艺，可以充分利用数字电路所带来的极大的灵活性和强大的功能，比起M54133FP/GP来本芯片具有一些显著的优点。
1，因为采用数字电路实现延时，这个芯片在控制原理上采用了定时延，从而使在电力网三级保护下的级间匹配的精确性大大提高，减少了误触发。
2，实现了多功能的集成。利用数字电路的灵活性，除了漏电保护这一主功能外，还将电源过压保护，电源过负载保护等功能也都集成了进来，实现了部分电源管理的功能。
3，本芯片在进行功能划分时，将尽可能多的功能都利用CMOS数字电路来实现。由于CMOS数字电路本身低功耗的特点，相对于用双极模拟工艺的实现方案大大节省了功耗。
4，本芯片外置了两个编程管脚，以便决定是应用在三级保护的哪一级上，具有极大的灵活性和可靠性。
5，在数字电路中特别增加了对输入有效信号的判别功能，大大减少了干扰信号造成的漏电保护器误动作。
本芯片是一个数模混合信号的芯片，参加了由上海集成电路中心(ICC)组织的MPW计划在无锡上华半导体有限公司流片，采用0.6微米双铝、双多晶硅、准双阱CMOS工艺。芯片面积约为2.1平方毫米，管脚为19个(含测试管脚)。
Our country now has the biggest share in the market of residual current device. But we are the biggest, not the best one. We can not find any chip for the residual current device that designed and made in china or for china. This is a heavy burden for these Chinese factories who have to buy these chips from a few foreign companies, since they can not earn too much money from the heavily competitive market.
This paper implements a new type residual current device which can be the substitute of M54133FP/GP. Unlike M54133FP/GP, this chip is achieved in the process of mixed-signal CMOS, but not purely analog bipolar process, which means it can take the full advantage of logic design: the flexibility in logic function and low power in dissipation. Some features of this chip are listed below:
The first, the response time is preset by the logic circuit so that the delay between different stages can be more accurate.
The second, the function of overload protection and overvoltage protection for the power supply are all integrated in this chip beside the residual current protection, so this chip acts like some of power management.
The third, the power dissipation is reduced through the usage of CMOS gates as the substitute of bipolar circuits.
The fourth, two pins are reserved for the selection of different stages. This achieves more flexibility in application.
The fifth, the judgement block is implemented in digital circuits for the validity of the input signal which will reduce the miscarriage of justice greatly.
The chip is a mixed-signal chip. This chip joined the MPW plan laughed by ICC, it was taped out in Shanghua Semiconductor corp., Wuxi. It is implemented in 0.6um double metal, double polysilicon, twin well CMOS process.
本论文设计了一种新型漏电开关保护芯片，在功能上可以取代目前占市场主导地位的日本三菱公司的M54133FP/GP。和采用双极工艺的纯模拟电路芯片M54133FP/GP不同，本芯片采用的是数模混合的CMOS工艺，可以充分利用数字电路所带来的极大的灵活性和强大的功能，比起M54133FP/GP来本芯片具有一些显著的优点。
1，因为采用数字电路实现延时，这个芯片在控制原理上采用了定时延，从而使在电力网三级保护下的级间匹配的精确性大大提高，减少了误触发。
2，实现了多功能的集成。利用数字电路的灵活性，除了漏电保护这一主功能外，还将电源过压保护，电源过负载保护等功能也都集成了进来，实现了部分电源管理的功能。
3，本芯片在进行功能划分时，将尽可能多的功能都利用CMOS数字电路来实现。由于CMOS数字电路本身低功耗的特点，相对于用双极模拟工艺的实现方案大大节省了功耗。
4，本芯片外置了两个编程管脚，以便决定是应用在三级保护的哪一级上，具有极大的灵活性和可靠性。
5，在数字电路中特别增加了对输入有效信号的判别功能，大大减少了干扰信号造成的漏电保护器误动作。
本芯片是一个数模混合信号的芯片，参加了由上海集成电路中心(ICC)组织的MPW计划在无锡上华半导体有限公司流片，采用0.6微米双铝、双多晶硅、准双阱CMOS工艺。芯片面积约为2.1平方毫米，管脚为19个(含测试管脚)。
Our country now has the biggest share in the market of residual current device. But we are the biggest, not the best one. We can not find any chip for the residual current device that designed and made in china or for china. This is a heavy burden for these Chinese factories who have to buy these chips from a few foreign companies, since they can not earn too much money from the heavily competitive market.
This paper implements a new type residual current device which can be the substitute of M54133FP/GP. Unlike M54133FP/GP, this chip is achieved in the process of mixed-signal CMOS, but not purely analog bipolar process, which means it can take the full advantage of logic design: the flexibility in logic function and low power in dissipation. Some features of this chip are listed below:
The first, the response time is preset by the logic circuit so that the delay between different stages can be more accurate.
The second, the function of overload protection and overvoltage protection for the power supply are all integrated in this chip beside the residual current protection, so this chip acts like some of power management.
The third, the power dissipation is reduced through the usage of CMOS gates as the substitute of bipolar circuits.
The fourth, two pins are reserved for the selection of different stages. This achieves more flexibility in application.
The fifth, the judgement block is implemented in digital circuits for the validity of the input signal which will reduce the miscarriage of justice greatly.
The chip is a mixed-signal chip. This chip joined the MPW plan laughed by ICC, it was taped out in Shanghua Semiconductor corp., Wuxi. It is implemented in 0.6um double metal, double polysilicon, twin well CMOS process.
引文
[1] 高福林等，漏电保护器的选用，《低温建筑技术》，2000年第1期
[2] P.V. Brennan, Residual current device with high immunity to nuisance tripping, IEE PROCEEDINGS-G, Vol. 140, No. 2, APRIL 1993
[3] M54133FP/GP datasheet
[4] 0.6um TECHNOLOGY TOPOLOGICAL DESIGN RULE, 无锡华晶上华半导体有限公司
[5] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Publishing House of Electronics Industry, 2002.6
[6] Paul R. Gray, Robert G. Meyer, Aanlysis and Design of Analog Integrated Circuits, Hamilton Printing Company, 1993
[7] Shyh-Jye Jou and Tsu-Lin Chen, On-Chip Voltage Down Converter for Low-Power Digital System, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅱ: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL 45, NO.5 MAY 1998
[8] Shyh-Jye Jou and Tsu-Lin Chen, On-Chip Voltage Down Converter for LP/LV Digital System, 1997 IEEE International Symposium on citcuits and System, June 9-12, 1997, Hong Kong
[9] Tsukasa Ooishi etc. , A Mixed Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 31, NO.4, APRIL 1996
[10] R. Hogervorst, J. P. Tero. R. G. H. Esschauzier, And J. H. Huijsing, A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries, IEEE Journal of Solid State Circuits, Vol. 29, pp1505-1513, December 1994
[11] Jan M. Rabaey，数字集成电路设计透视，清华大学出版社，1998．12
[12] 张明，Verilog HDL实用教程，电子科技大学出版社，1999．11
[13] 杨之廉，申明，超大规模集成电路设计方法学导论(第二版)，清华大学出版社，1999．3
[14] 韩雁，专用集成电路设计技术基础，电子科技大学出版社，2000．3
[15] 吴明远，电子算盘式计算器及其芯片的设计，浙江大学硕士研究生毕业论文，2002
[2] P.V. Brennan, Residual current device with high immunity to nuisance tripping, IEE PROCEEDINGS-G, Vol. 140, No. 2, APRIL 1993
[3] M54133FP/GP datasheet
[4] 0.6um TECHNOLOGY TOPOLOGICAL DESIGN RULE, 无锡华晶上华半导体有限公司
[5] Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, Publishing House of Electronics Industry, 2002.6
[6] Paul R. Gray, Robert G. Meyer, Aanlysis and Design of Analog Integrated Circuits, Hamilton Printing Company, 1993
[7] Shyh-Jye Jou and Tsu-Lin Chen, On-Chip Voltage Down Converter for Low-Power Digital System, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-Ⅱ: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL 45, NO.5 MAY 1998
[8] Shyh-Jye Jou and Tsu-Lin Chen, On-Chip Voltage Down Converter for LP/LV Digital System, 1997 IEEE International Symposium on citcuits and System, June 9-12, 1997, Hong Kong
[9] Tsukasa Ooishi etc. , A Mixed Mode Voltage Down Converter with Impedance Adjustment Circuitry for Low-Voltage High-Frequency Memories, IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 31, NO.4, APRIL 1996
[10] R. Hogervorst, J. P. Tero. R. G. H. Esschauzier, And J. H. Huijsing, A Compact Power-Efficient 3 V CMOS Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries, IEEE Journal of Solid State Circuits, Vol. 29, pp1505-1513, December 1994
[11] Jan M. Rabaey，数字集成电路设计透视，清华大学出版社，1998．12
[12] 张明，Verilog HDL实用教程，电子科技大学出版社，1999．11
[13] 杨之廉，申明，超大规模集成电路设计方法学导论(第二版)，清华大学出版社，1999．3
[14] 韩雁，专用集成电路设计技术基础，电子科技大学出版社，2000．3
[15] 吴明远，电子算盘式计算器及其芯片的设计，浙江大学硕士研究生毕业论文，2002