12位流水线型A/D转换器设计
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摘要
本文设计了一种应用广泛的流水线型A／D转换器，分辨精度12位，采样速率50MHz，输入范围1V，工作电压3.3V。
首先介绍了几种应用较为广泛的A／D转换器的结构和工作原理，并对其优缺点进行了分析。然后结合设计指标确定了本文流水线型A／D转换器的主体结构，经过权衡考虑计划采用8级流水线型结构实现，结合冗余位数字校正技术，第一级采用4位／级结构，后面6级为1.5位／级结构，最后一级为2位／级结构。
电路的设计从系统级开始，首先分析其功能然后由功能得出算法，再由算法设计出具体的电路。采样保持电路(SHA)采用翻转式结构，提高了采样速度和减小了因电容失配引起的采样误差；除过最后一级每级流水线都包含一个闪烁型(flash)ADC和余量增益电路(MDAC)，第一级流水线包含一个4位子ADC和4位MDAC，后面6级流水线包含一个1.5位子ADC和1.5位MDAC，最后一级流水线仅包括一个2位子ADC；译码电路和数字校正电路由逻辑电路构成。
最后使用Hspice软件和TSMC 0.35um CMOS工艺库对电路逐级仿真，仿真结果显示各级电路能够实现基本功能，转换出的12位数字信号在最后4位出现了误差，对于误差的减小还需要进一步研究。
In this thesis, a 12bit, 50MSPS, 1V input range, single 3.3V supply, pipelined ADC is presented.
First the architecture and the theory of several popular ADC is presented, the advantage and the disadvantage is analyzed. Then the basic architecture is designed, the architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4bit first stage followed by six 1.5bit stages and a final 2bit flash.
The design is begin at the system architecture, the function is analyzed firstly, then educe the arithmetic, the circuit is based on arithmetic. The SHA used overturn architecture. Each stage of the pipeline, excepting the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and inter stage residue amplifier (MDAC). The encoder and the correction logic consists of logic circuit.
The simulation results with Hspice and TSMC 0.35um CMOS process proves it can carry out the basic function, the last 4bit of the digital outputs is imprecise.
首先介绍了几种应用较为广泛的A／D转换器的结构和工作原理，并对其优缺点进行了分析。然后结合设计指标确定了本文流水线型A／D转换器的主体结构，经过权衡考虑计划采用8级流水线型结构实现，结合冗余位数字校正技术，第一级采用4位／级结构，后面6级为1.5位／级结构，最后一级为2位／级结构。
电路的设计从系统级开始，首先分析其功能然后由功能得出算法，再由算法设计出具体的电路。采样保持电路(SHA)采用翻转式结构，提高了采样速度和减小了因电容失配引起的采样误差；除过最后一级每级流水线都包含一个闪烁型(flash)ADC和余量增益电路(MDAC)，第一级流水线包含一个4位子ADC和4位MDAC，后面6级流水线包含一个1.5位子ADC和1.5位MDAC，最后一级流水线仅包括一个2位子ADC；译码电路和数字校正电路由逻辑电路构成。
最后使用Hspice软件和TSMC 0.35um CMOS工艺库对电路逐级仿真，仿真结果显示各级电路能够实现基本功能，转换出的12位数字信号在最后4位出现了误差，对于误差的减小还需要进一步研究。
In this thesis, a 12bit, 50MSPS, 1V input range, single 3.3V supply, pipelined ADC is presented.
First the architecture and the theory of several popular ADC is presented, the advantage and the disadvantage is analyzed. Then the basic architecture is designed, the architecture consists of a front end SHA followed by a pipelined switched capacitor ADC. The pipelined ADC is divided into three sections, consisting of a 4bit first stage followed by six 1.5bit stages and a final 2bit flash.
The design is begin at the system architecture, the function is analyzed firstly, then educe the arithmetic, the circuit is based on arithmetic. The SHA used overturn architecture. Each stage of the pipeline, excepting the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and inter stage residue amplifier (MDAC). The encoder and the correction logic consists of logic circuit.
The simulation results with Hspice and TSMC 0.35um CMOS process proves it can carry out the basic function, the last 4bit of the digital outputs is imprecise.
引文
[1] 洪志良．模拟集成电路分析与设[M]．北京：科学出版社，2005：194-289
[2] R．J．贝克．CMOS：混合信号电路设计[M]．北京：科学出版社，2005：221-460
[3] 秦世才，高清运．现代模拟集成电子学[M]．北京：科学出版社，2003：255-259
[4] www.analog.com
[5] www.atmel.com
[6] www.linear.com.cn
[7] 吴大正．信号与线性系统分析[M]．北京：高等教育出版社，2000：186-192
[8] 薛亮．10位高速流水线模数转换器的研究[D]．北京：清华大学，2004：23-67
[9] Mikko Waltari. 1-V 9-Bit Pipelined Switched-Opamp ADC[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36(1): 129-134
[10] 毕查德·拉扎维．模拟CMOS集成电路设计(陈贵灿等译)[M]．西安：西安交通大学出版社．2004：9-360
[11] Yang. W. A 3V 340mW 14bit 75Msample/s CMOS ADC with 85dB SFDR at Nyquist input[J]. Solid-State Circuits, 2001, 36(1): 10
[12] Terje N. Andersen. A 97mW 110MS/s 12b Pipeline AOCImplemented in 0.18um Digital CMOS[J]. Solid-State Circuits, 2004, 40(4): 247-250
[13] H. A. ASLANZADEH. A LOW POWER 25MS/S 12-BIT PIPELINED ANALOG TO DIGITAL CONVERTER FOR WIRELIESS APPLICATIONS[J]. SSMSD 2003, 2003, 8(3): 38-42
[14] M. Yaser. Azizi. Thermal noise analysis of multi-bit SC gain-stages for low-voltage high-resolution pipeline ADC design[J]. Circuits and Systems, 2003, 32(2): 581-584
[15] J. Goes. ACMOS 4-bit MDACwith Self-Calibrated 14-bit Linearity for High-Resolution Pipclined A/D Converters[J]. IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, 6(6): 105-108
[16] Vivek Sharma. A Generic Multilevel Multiplying O/A Converter for Pipelined ADCs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40(2): 6182-6185
[17] D. W. Cline, P. R. Gray. A power optimized 13-b5Msamples/s pipelined analog-to-digital converter in 1.2um CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 35(3): 294-303
[18] S. H. Lewis. Optimizing the stage resolution in pipelincd, multistagc, analog-to-digital converters for video-rate applications[J]. IEEE Trans. Circuits and Systems2, 1992, 39(8): 516-523
[19] S. H. Lewis. A 10-b 20-Msample/s Analog-to-Digital Converter[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27(3): 351-358
[20] Gil-Cho Ahn. A 12-b, 10-Mltz, 250-mW CMOS A/D Converter[J]. IEEE JOURNAl. OF SOLID-STATE CIRCUITS, 1996, 31(12): 2030-2035
[21] M. Anderson, K. Norling, A Reconfigurable Pipelined ADC in 0.18μm CMOS[J]. 2005 Symposium on VLSI Circuits Digest of Technical Papers, 2005, 21(2): 326-329
[22] 吴建辉．CMOS模拟集成电路分析与设计[M]．北京：电子工业出版社，2004：210-321
[23] J. Yuan. A 50MS/s 12-bit CMOS Pipeline A/D Converter with Nonlinear Background Calibration[J]. IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, 10(6): 399-402
[24] 朱臻，王涛．30兆赫采样频率的采样-保持电路和减法-增益电路的误差分析及设计[J]．固体电子学研究与进展，2002，22(1)：57-63
[25] 胡小波．12位40兆采样频率流水线结构模数转换器[D]．武汉：华中科技大学，2004：43-44
[26] Lewis S. A 10-b 20Msample/s analog-to-digital converter[J]. Solid-State Circuits, 1992, 27(1): 351-358
[27] Khayrollah Hadidi. Error Analysis in pipeline A/D Converters and its Applications[J]. IEEE Transactions on Circuits and Systems, 1992, 39(8): 506-515
[28] Alma Deli'c-Ibuki'c. CONTINUOUS DIGITAL CALIBRATION OF PIPELINED A/D CONVERTERS[D]. US: The University of Maine, 2004: 5-17
[29] 李宏斌．10bits100MSPSPipelinedADC的采保和时钟电路研究与设计[D]．成都：电子科技大学，2005：28
[30] KLAAS BULT. A Fast-Setting CMOS Op Amp for SC Circuits with 90-dB DC Gain[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25(6): 1379-1384
[31] 王晋．全差分增益提高运算放大器的分析与设计[J]．电子器件，2005，28(2)：342-345
[32] Ojas Choksi and L. Richard Carley. Analysis of Switched-Capacitor Common-Mode Feedback Circuit[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ, 2003, 50(12): 906-917
[33] 朱正涌．半导体集成电路[M]．北京：清华大学出版社，2001：140-146
[34] P．E．艾伦．CMOS模拟电路设计[M]．北京：科学出版社，1995：439-494
[35] 高文焕．模拟电路的计算机分析与设计PSpice程序应用[M]．北京：清华大学出版社，1999：14-50
[36] 杨之廉．超大规模集成电路设计方法学导论[M]．北京：清华大学出版社，2002：123-156
[37] Avant!. Star-Hspice Manual[M]. US: Avant!, 1999: 13-188
[2] R．J．贝克．CMOS：混合信号电路设计[M]．北京：科学出版社，2005：221-460
[3] 秦世才，高清运．现代模拟集成电子学[M]．北京：科学出版社，2003：255-259
[4] www.analog.com
[5] www.atmel.com
[6] www.linear.com.cn
[7] 吴大正．信号与线性系统分析[M]．北京：高等教育出版社，2000：186-192
[8] 薛亮．10位高速流水线模数转换器的研究[D]．北京：清华大学，2004：23-67
[9] Mikko Waltari. 1-V 9-Bit Pipelined Switched-Opamp ADC[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36(1): 129-134
[10] 毕查德·拉扎维．模拟CMOS集成电路设计(陈贵灿等译)[M]．西安：西安交通大学出版社．2004：9-360
[11] Yang. W. A 3V 340mW 14bit 75Msample/s CMOS ADC with 85dB SFDR at Nyquist input[J]. Solid-State Circuits, 2001, 36(1): 10
[12] Terje N. Andersen. A 97mW 110MS/s 12b Pipeline AOCImplemented in 0.18um Digital CMOS[J]. Solid-State Circuits, 2004, 40(4): 247-250
[13] H. A. ASLANZADEH. A LOW POWER 25MS/S 12-BIT PIPELINED ANALOG TO DIGITAL CONVERTER FOR WIRELIESS APPLICATIONS[J]. SSMSD 2003, 2003, 8(3): 38-42
[14] M. Yaser. Azizi. Thermal noise analysis of multi-bit SC gain-stages for low-voltage high-resolution pipeline ADC design[J]. Circuits and Systems, 2003, 32(2): 581-584
[15] J. Goes. ACMOS 4-bit MDACwith Self-Calibrated 14-bit Linearity for High-Resolution Pipclined A/D Converters[J]. IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 1996, 6(6): 105-108
[16] Vivek Sharma. A Generic Multilevel Multiplying O/A Converter for Pipelined ADCs[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40(2): 6182-6185
[17] D. W. Cline, P. R. Gray. A power optimized 13-b5Msamples/s pipelined analog-to-digital converter in 1.2um CMOS[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996, 35(3): 294-303
[18] S. H. Lewis. Optimizing the stage resolution in pipelincd, multistagc, analog-to-digital converters for video-rate applications[J]. IEEE Trans. Circuits and Systems2, 1992, 39(8): 516-523
[19] S. H. Lewis. A 10-b 20-Msample/s Analog-to-Digital Converter[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27(3): 351-358
[20] Gil-Cho Ahn. A 12-b, 10-Mltz, 250-mW CMOS A/D Converter[J]. IEEE JOURNAl. OF SOLID-STATE CIRCUITS, 1996, 31(12): 2030-2035
[21] M. Anderson, K. Norling, A Reconfigurable Pipelined ADC in 0.18μm CMOS[J]. 2005 Symposium on VLSI Circuits Digest of Technical Papers, 2005, 21(2): 326-329
[22] 吴建辉．CMOS模拟集成电路分析与设计[M]．北京：电子工业出版社，2004：210-321
[23] J. Yuan. A 50MS/s 12-bit CMOS Pipeline A/D Converter with Nonlinear Background Calibration[J]. IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2005, 10(6): 399-402
[24] 朱臻，王涛．30兆赫采样频率的采样-保持电路和减法-增益电路的误差分析及设计[J]．固体电子学研究与进展，2002，22(1)：57-63
[25] 胡小波．12位40兆采样频率流水线结构模数转换器[D]．武汉：华中科技大学，2004：43-44
[26] Lewis S. A 10-b 20Msample/s analog-to-digital converter[J]. Solid-State Circuits, 1992, 27(1): 351-358
[27] Khayrollah Hadidi. Error Analysis in pipeline A/D Converters and its Applications[J]. IEEE Transactions on Circuits and Systems, 1992, 39(8): 506-515
[28] Alma Deli'c-Ibuki'c. CONTINUOUS DIGITAL CALIBRATION OF PIPELINED A/D CONVERTERS[D]. US: The University of Maine, 2004: 5-17
[29] 李宏斌．10bits100MSPSPipelinedADC的采保和时钟电路研究与设计[D]．成都：电子科技大学，2005：28
[30] KLAAS BULT. A Fast-Setting CMOS Op Amp for SC Circuits with 90-dB DC Gain[J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1990, 25(6): 1379-1384
[31] 王晋．全差分增益提高运算放大器的分析与设计[J]．电子器件，2005，28(2)：342-345
[32] Ojas Choksi and L. Richard Carley. Analysis of Switched-Capacitor Common-Mode Feedback Circuit[J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—Ⅱ, 2003, 50(12): 906-917
[33] 朱正涌．半导体集成电路[M]．北京：清华大学出版社，2001：140-146
[34] P．E．艾伦．CMOS模拟电路设计[M]．北京：科学出版社，1995：439-494
[35] 高文焕．模拟电路的计算机分析与设计PSpice程序应用[M]．北京：清华大学出版社，1999：14-50
[36] 杨之廉．超大规模集成电路设计方法学导论[M]．北京：清华大学出版社，2002：123-156
[37] Avant!. Star-Hspice Manual[M]. US: Avant!, 1999: 13-188