多业务PDH单片FPGA解决方案
摘要
随着通信网的发展和用户需求的提高，光纤通信中的PDH体系逐渐被SDH体系所取代。SDH光纤通信系统以其通信容量大、传输性能好、接口标准、组网灵活方便、管理功能强大等优点获得越来越广泛的应用。但是在某些对传输容量需求不大的场合，SDH的巨大潜力和优越性无法发挥出来，反而还会造成带宽浪费。相反，PDH因其容量适中，配置灵活，成本低廉和功能齐全，可针对客户不同需要设计不同的方案，在某些特定的接入场合具有一定的优势。
本课题根据现实的需要，提出并设计了一种基于PDH技术的多业务单片FPGA传输系统。系统可以同时提供12路E1的透明传输和一个线速为100M以太网通道，主要由一块FPGA芯片实现大部分功能，该解决方案在集成度、功耗、成本以及灵活性等方面都具有明显的优势。
本文首先介绍数字通信以及数字复接原理和以太网的相关知识，然后详细阐述了本系统的方案设计，对所使用的芯片和控制芯片FPGA做了必要的介绍，最后具体介绍了系统硬件和FPGA编码设计，以及后期的软硬件调试。
归纳起来，本文主要具体工作如下：
1．实现4路E1信号到1路二次群信号的复分接，主要包括全数字锁相环、HDB3-NRZ编解码、正码速调整、帧头检测和复分接等。
2．将以太网MII接口来的25M的MII信号通过码速变换到25.344M，进行映射。
3．将三路二次群信号和变换过的以太网MII信号进行5b6b编解码，以利于在光纤上传输。
4．高速时提取时钟采用XILINX的CDR方案。并对接收到的信号经过5b6b解码后，分接出各路信号。
With the development of communication network and the improvement of user's requirement, PDH is gradually replaced by SDH in optical fiber communication. SDH optical fiber communication system is being used widely by its advantages: huge volume of communication, high performance of transmission, facile configuring and powerful management. But in some case when huge volume of communication is not needed, the potential and advantages of SDH can't be exerted and most of volume is wasted. On the contrary, in some special case PDH have advantages for its moderate volume, facile configuring, low cost, high reliability and plentiful function.In this thesis, we design and realize a single chip FPGA transmitting system based on PDH technology for the requirement of practice. The system which is mainly designed on single FPGA chip could transmit 12 El signals and 1 100M Ethernet tunnel, and this solution have obvious advantages in integration, power, cost and flexibility.Firstly, we introduce digital communication and the principle of multiplexer as well as ethernet. Then we describe the solution of our transmitting system in detail, also we introduce the chip used in this system including the main FPGA chip. Finally, the circuit board is designed and the RTL coding is writed, then both hardware and verilog code debug is performed. The author's main tasks includes:1.Implement the multiplexer of 4 El signals, the main circuit includes all digital phase-locked loop(DPLL), HDB3 encode and decode, positive justification, the start of frame detect circuit, multiplex and demultiplex circuit.2.Map the Mil signals which come from 100M ethernet from 25M bit/s to 25.344M bit/s.3.Encode the El multiplexer signals and Mil signals with 5b6b encode-decode scheme, then transmit the 152.074M signal by optical fiber.4.Use the clock and data recovery solution of XILINX to recover the high-speed clock. And decode the signal with 5b6b, then demultiplex the El and ethernet signals.
本课题根据现实的需要，提出并设计了一种基于PDH技术的多业务单片FPGA传输系统。系统可以同时提供12路E1的透明传输和一个线速为100M以太网通道，主要由一块FPGA芯片实现大部分功能，该解决方案在集成度、功耗、成本以及灵活性等方面都具有明显的优势。
本文首先介绍数字通信以及数字复接原理和以太网的相关知识，然后详细阐述了本系统的方案设计，对所使用的芯片和控制芯片FPGA做了必要的介绍，最后具体介绍了系统硬件和FPGA编码设计，以及后期的软硬件调试。
归纳起来，本文主要具体工作如下：
1．实现4路E1信号到1路二次群信号的复分接，主要包括全数字锁相环、HDB3-NRZ编解码、正码速调整、帧头检测和复分接等。
2．将以太网MII接口来的25M的MII信号通过码速变换到25.344M，进行映射。
3．将三路二次群信号和变换过的以太网MII信号进行5b6b编解码，以利于在光纤上传输。
4．高速时提取时钟采用XILINX的CDR方案。并对接收到的信号经过5b6b解码后，分接出各路信号。
With the development of communication network and the improvement of user's requirement, PDH is gradually replaced by SDH in optical fiber communication. SDH optical fiber communication system is being used widely by its advantages: huge volume of communication, high performance of transmission, facile configuring and powerful management. But in some case when huge volume of communication is not needed, the potential and advantages of SDH can't be exerted and most of volume is wasted. On the contrary, in some special case PDH have advantages for its moderate volume, facile configuring, low cost, high reliability and plentiful function.In this thesis, we design and realize a single chip FPGA transmitting system based on PDH technology for the requirement of practice. The system which is mainly designed on single FPGA chip could transmit 12 El signals and 1 100M Ethernet tunnel, and this solution have obvious advantages in integration, power, cost and flexibility.Firstly, we introduce digital communication and the principle of multiplexer as well as ethernet. Then we describe the solution of our transmitting system in detail, also we introduce the chip used in this system including the main FPGA chip. Finally, the circuit board is designed and the RTL coding is writed, then both hardware and verilog code debug is performed. The author's main tasks includes:1.Implement the multiplexer of 4 El signals, the main circuit includes all digital phase-locked loop(DPLL), HDB3 encode and decode, positive justification, the start of frame detect circuit, multiplex and demultiplex circuit.2.Map the Mil signals which come from 100M ethernet from 25M bit/s to 25.344M bit/s.3.Encode the El multiplexer signals and Mil signals with 5b6b encode-decode scheme, then transmit the 152.074M signal by optical fiber.4.Use the clock and data recovery solution of XILINX to recover the high-speed clock. And decode the signal with 5b6b, then demultiplex the El and ethernet signals.
引文
[1] ITU—T G. 742.
[2] 牛立新，杨钧．用FPGA实现PDH到SDH的高阶映射．光通信研究．1997，2
[3] Xilinx公司．用Spartan-Ⅱ实现Reed—Solomon编码／译码方案．电子产品世界．2006，6
[4] 张璇，王福昌．帧同步器的EPLD设计与实现．电气电子教学学报．Dec，2001
[5] 徐钊，杨锐．基于FPGA的16El光纤复接系统．中国矿业人学学报．2003，3
[6] 郑新，徐东明，宋焕生．基于FPGA的多路El反向复用接口电路设计与实现．无线电工程．2003，10
[7] 习建华，龚建荣．用FPGA实现二次群复接器．数字通信．1999，3
[8] J．Bhasker著，徐振林等译．Verilog HDL硬件描述语言．机械工业出版社．2000，7
[9] 孙玉．数字复接技术．人民邮电出版社．1991
[10] 李文海，张方菖．数字通信原理．人民邮电出版社。1986
[11] 王钦笙，毛京丽，朱彤．数字通信原理．北京邮电人学出版社．1995
[12] 郭世满，叶奕和，钱德馨．数字通信—原理、技术及其应用．人民邮电出版社．1994
[13] 桑林，郝建军，刘丹谱．数字通信．北京邮电大学出版社．2002
[14] 李文海，毛京丽，石方文．数字通信原理．人民邮电出版社．2001
[15] 段吉海，黄智伟．基于CPLD／FPGA的数字通信系统建模与设计．电子工业出版社．2004
[16] 黄海生，刘宇．一种从El信号中提取时钟的全数字锁相环设计与实现．现代电子技术．2000．12
[17] 单长虹，孟宪元．基于FPGA的全数字锁相环路的设计．通讯与电视．2001，9
[18] 谢程宏．全数字锁相环的设计．通信与计算机．2003，4
[19] 龚建荣，李晓飞．利用FPGA实现数字锁相及频率转换．南京邮电学院学报．1998，8
[20] Harry A. Nienhaus, Vijay K. Jain. A Digital Phase Lock Loop For VLSI Telecommunication Applications. IEEE. 1989
[21] 胡华春．数字锁相环路原理与应用．上海科技出版社．1990
[22] Digital Phase Locked Loop Design Using SN54/74LS297. Texas Instruments. March, 1997
[23] 王利众，费元春．基于Q3236的S波段频率源的设计．电卢技术．2002，10
[24] 李莉，吴重庆等．用于SDH／SONET的时钟提取芯片$3026．公安大学学报．1999，4
[25] 魏建将．用集总LC元件的VCO构成155.520MHz锁相时钟频率源．电子技术应用．2002，3
[26] Spartan-IIE 1.8V FPGA Family: Complete Data Sheet. Xilinx. 2003, 7
[27] Clock and Data Recovery With Coded Data Streams. Xilinx XAPP250. Sep, 2003
[28] 45MHz to 650MHz, Integrated IF VCOs with Differential Output. MAXIM.
[29] MAX2605-Max2609 Evaluation Kits. MAXIM.
[30] 王瀚晟，曾烈光．全数字化PDH复接系统的设计．电信科学．1998，4
[31] 陈立胜．多路El以太网的传输．通讯世界．2002，9
[32] 王晓林．新型数字二次复接器．无线电通信技术．1995，8
[33] 袁天夫．NRZ码与HDB3码相互转换的实现．集成电路应用．1997，3
[34] 唐智灵．VHDL语言在数字光端机专用芯片中的一个应用．光通信技术．1999，3
[35] 杨静．采用在系统可编程逻辑器件实现HDB3编解码．北京联合大学学报．1998，3
[36] 高悦广，闫华．在SONET／SDH架构上实现以太网透明传输的方案．电子质量．2002，1
[37] IEEE Std 802.3. 2000 Edition
[38] RTL8201 Single port 10/100Mbps Fast Ethernet Phyceiver. REALTEK Semiconductor Corp.
[39] 范亚希，葛宁．以太网到多路El适配电路设计及FPGA实现．电子技术应用．2002，11
[40] Ethernet Ip Core Specification. www. opencores, org.
[41] 王鸣．基于RC7010的以太网光端机．当代通信．2002，11
[42] 一种用VHDL语言实现的帧同步算法．慧聪电子元器件商务网
[43] 吴玉成，许太火，王黎明．帧同步电路的设计．现代电子技术．2003，4
[44] 吕志斌．数字通信网中帧同步的实现方式．微波与卫星通信．1997，3
[45] 曾烈光，冯重熙．一种减少正码速调整等候抖动的新方法．通信学报．1992，1
[46] 全劲松．34Mbit／s数字电视传输系统研制．现代电信技术．1996，4
[47] 谢润华，黄佩伟．多速率码流同步复接方案设计与实现．通信技术．2001，5
[48] G. Pierobon, R. P. Valussi. "Jitter analysis of a double modulated threshold pulse stuffing synchronizer". IEEE Transactions on Communication, Vol. 39, Issue: 4, PP. 594-602, April 1991
[49] Hansheng Wang, Xiaoyi Qin, Lieguang Zeng, Fuqin Xiong. "Coding, decoding, and recovery of clock synchronization in digital multiplexing system," IEEE Transactions on Communications, Vol. 51, lssue: 5, PE825-831, May 2003
[50] 沙燕萍，皇甫伟，曾烈光．异步FIFO的VHDL设计．电子技术应用．2001，6
[51] Vijay A. Nebhrajani. ASYNCHRONOUS FIFO ARCHITECTURE.
[52] 吴自信，张嗣忠．异步FIFO结构及FPGA设计．半导体与嵌入式系统应用．2003，8
[53] 孙娇燕．586B码编解码方案的分析与改进．光通信技术．1994，18(4)
[54] 郑庆荣，潘道仪．M序列在数字通信中的应川及电路设计．数字通信．1991，2
[55] 范秋华，季鸿雁．基于VHDL的m序列．现代电子技术．2003，7
[2] 牛立新，杨钧．用FPGA实现PDH到SDH的高阶映射．光通信研究．1997，2
[3] Xilinx公司．用Spartan-Ⅱ实现Reed—Solomon编码／译码方案．电子产品世界．2006，6
[4] 张璇，王福昌．帧同步器的EPLD设计与实现．电气电子教学学报．Dec，2001
[5] 徐钊，杨锐．基于FPGA的16El光纤复接系统．中国矿业人学学报．2003，3
[6] 郑新，徐东明，宋焕生．基于FPGA的多路El反向复用接口电路设计与实现．无线电工程．2003，10
[7] 习建华，龚建荣．用FPGA实现二次群复接器．数字通信．1999，3
[8] J．Bhasker著，徐振林等译．Verilog HDL硬件描述语言．机械工业出版社．2000，7
[9] 孙玉．数字复接技术．人民邮电出版社．1991
[10] 李文海，张方菖．数字通信原理．人民邮电出版社。1986
[11] 王钦笙，毛京丽，朱彤．数字通信原理．北京邮电人学出版社．1995
[12] 郭世满，叶奕和，钱德馨．数字通信—原理、技术及其应用．人民邮电出版社．1994
[13] 桑林，郝建军，刘丹谱．数字通信．北京邮电大学出版社．2002
[14] 李文海，毛京丽，石方文．数字通信原理．人民邮电出版社．2001
[15] 段吉海，黄智伟．基于CPLD／FPGA的数字通信系统建模与设计．电子工业出版社．2004
[16] 黄海生，刘宇．一种从El信号中提取时钟的全数字锁相环设计与实现．现代电子技术．2000．12
[17] 单长虹，孟宪元．基于FPGA的全数字锁相环路的设计．通讯与电视．2001，9
[18] 谢程宏．全数字锁相环的设计．通信与计算机．2003，4
[19] 龚建荣，李晓飞．利用FPGA实现数字锁相及频率转换．南京邮电学院学报．1998，8
[20] Harry A. Nienhaus, Vijay K. Jain. A Digital Phase Lock Loop For VLSI Telecommunication Applications. IEEE. 1989
[21] 胡华春．数字锁相环路原理与应用．上海科技出版社．1990
[22] Digital Phase Locked Loop Design Using SN54/74LS297. Texas Instruments. March, 1997
[23] 王利众，费元春．基于Q3236的S波段频率源的设计．电卢技术．2002，10
[24] 李莉，吴重庆等．用于SDH／SONET的时钟提取芯片$3026．公安大学学报．1999，4
[25] 魏建将．用集总LC元件的VCO构成155.520MHz锁相时钟频率源．电子技术应用．2002，3
[26] Spartan-IIE 1.8V FPGA Family: Complete Data Sheet. Xilinx. 2003, 7
[27] Clock and Data Recovery With Coded Data Streams. Xilinx XAPP250. Sep, 2003
[28] 45MHz to 650MHz, Integrated IF VCOs with Differential Output. MAXIM.
[29] MAX2605-Max2609 Evaluation Kits. MAXIM.
[30] 王瀚晟，曾烈光．全数字化PDH复接系统的设计．电信科学．1998，4
[31] 陈立胜．多路El以太网的传输．通讯世界．2002，9
[32] 王晓林．新型数字二次复接器．无线电通信技术．1995，8
[33] 袁天夫．NRZ码与HDB3码相互转换的实现．集成电路应用．1997，3
[34] 唐智灵．VHDL语言在数字光端机专用芯片中的一个应用．光通信技术．1999，3
[35] 杨静．采用在系统可编程逻辑器件实现HDB3编解码．北京联合大学学报．1998，3
[36] 高悦广，闫华．在SONET／SDH架构上实现以太网透明传输的方案．电子质量．2002，1
[37] IEEE Std 802.3. 2000 Edition
[38] RTL8201 Single port 10/100Mbps Fast Ethernet Phyceiver. REALTEK Semiconductor Corp.
[39] 范亚希，葛宁．以太网到多路El适配电路设计及FPGA实现．电子技术应用．2002，11
[40] Ethernet Ip Core Specification. www. opencores, org.
[41] 王鸣．基于RC7010的以太网光端机．当代通信．2002，11
[42] 一种用VHDL语言实现的帧同步算法．慧聪电子元器件商务网
[43] 吴玉成，许太火，王黎明．帧同步电路的设计．现代电子技术．2003，4
[44] 吕志斌．数字通信网中帧同步的实现方式．微波与卫星通信．1997，3
[45] 曾烈光，冯重熙．一种减少正码速调整等候抖动的新方法．通信学报．1992，1
[46] 全劲松．34Mbit／s数字电视传输系统研制．现代电信技术．1996，4
[47] 谢润华，黄佩伟．多速率码流同步复接方案设计与实现．通信技术．2001，5
[48] G. Pierobon, R. P. Valussi. "Jitter analysis of a double modulated threshold pulse stuffing synchronizer". IEEE Transactions on Communication, Vol. 39, Issue: 4, PP. 594-602, April 1991
[49] Hansheng Wang, Xiaoyi Qin, Lieguang Zeng, Fuqin Xiong. "Coding, decoding, and recovery of clock synchronization in digital multiplexing system," IEEE Transactions on Communications, Vol. 51, lssue: 5, PE825-831, May 2003
[50] 沙燕萍，皇甫伟，曾烈光．异步FIFO的VHDL设计．电子技术应用．2001，6
[51] Vijay A. Nebhrajani. ASYNCHRONOUS FIFO ARCHITECTURE.
[52] 吴自信，张嗣忠．异步FIFO结构及FPGA设计．半导体与嵌入式系统应用．2003，8
[53] 孙娇燕．586B码编解码方案的分析与改进．光通信技术．1994，18(4)
[54] 郑庆荣，潘道仪．M序列在数字通信中的应川及电路设计．数字通信．1991，2
[55] 范秋华，季鸿雁．基于VHDL的m序列．现代电子技术．2003，7