基于FPGA的同步数字复接系统的设计
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摘要
数字复接技术是数字通信网的一项重要技术,能够将若干路低速信号合并为一路高速信号,进而提高传输效率。应用可编程逻辑门阵列(FPGA)芯片实现复接系统便于修改电路结构,增强设计的灵活性,并且节约了系统资源。
本文基于FPGA的同步数字复接系统的设计与建模,首先介绍了EDA技术及其发展,然后对数字复接技术的基木原理进行说明,采用自顶向下的数字系统建模思路,提出了基于FPGA的同步数字复接系统的设计方法,详细介绍了同步数字复接器和同步数字分接器各组成模块的设计过程及具体功能,并阐述其设计思想,重点分析了数字分接模块中帧同步电路和锁相环提取位同步电路的实现方法,给出了在Quartus II环境下的仿真结果,并对仿真波形进行分析说明。本文设计的数字复接系统的主要功能是在复接端将四个支路的25Mbps数据通过正码速调整技术,将其合路成一路100 Mbps的高速数据流,在分接端又将此高速数据流恢复成原来的四路25Mbps的数据。整个系统的功能在EDA技术开发平台上均调试通过,具有较高的实用性和可靠性。
Digital multiplexing and demultiplexing, an important technique in the network of communication, can improve the transmission efficiency in the way of multiplexing several low speed data flows into a high speed one. In addition to better design flexibility and save system resource, digital MULDEX system based on the FPGA also make the problem of modifying structure of circuit easier.
This paper deals with the implementation and modeling of synchronous digital MULDEX system based on the FPGA. Firstly it presents EDA technology and its development, then describes the theory of synchronous digital MULDEX system. By using top-down design method, a way for designing MULDEX system based on the FPGA is introduced. Not only the design step and idiographic function of synchronous digital multiplexer and synchronous digital demultiplexer is presented, but design idea is also put forward. This paper analyzes the implementation of frame synchronization circuit and DPLL circuit in the bit synchronization ,along with their simulation result in Quartus II which has been explained in detail. The function of the designed MULDEX system can be accomplished that multiplexes four branches of 25Mb/s into one data flow of 100Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. This system features have high reliability and good flexibility.
本文基于FPGA的同步数字复接系统的设计与建模,首先介绍了EDA技术及其发展,然后对数字复接技术的基木原理进行说明,采用自顶向下的数字系统建模思路,提出了基于FPGA的同步数字复接系统的设计方法,详细介绍了同步数字复接器和同步数字分接器各组成模块的设计过程及具体功能,并阐述其设计思想,重点分析了数字分接模块中帧同步电路和锁相环提取位同步电路的实现方法,给出了在Quartus II环境下的仿真结果,并对仿真波形进行分析说明。本文设计的数字复接系统的主要功能是在复接端将四个支路的25Mbps数据通过正码速调整技术,将其合路成一路100 Mbps的高速数据流,在分接端又将此高速数据流恢复成原来的四路25Mbps的数据。整个系统的功能在EDA技术开发平台上均调试通过,具有较高的实用性和可靠性。
Digital multiplexing and demultiplexing, an important technique in the network of communication, can improve the transmission efficiency in the way of multiplexing several low speed data flows into a high speed one. In addition to better design flexibility and save system resource, digital MULDEX system based on the FPGA also make the problem of modifying structure of circuit easier.
This paper deals with the implementation and modeling of synchronous digital MULDEX system based on the FPGA. Firstly it presents EDA technology and its development, then describes the theory of synchronous digital MULDEX system. By using top-down design method, a way for designing MULDEX system based on the FPGA is introduced. Not only the design step and idiographic function of synchronous digital multiplexer and synchronous digital demultiplexer is presented, but design idea is also put forward. This paper analyzes the implementation of frame synchronization circuit and DPLL circuit in the bit synchronization ,along with their simulation result in Quartus II which has been explained in detail. The function of the designed MULDEX system can be accomplished that multiplexes four branches of 25Mb/s into one data flow of 100Mb/s and then demultiplexes the data flow into four branches, positive justification used during the course of multiplex. This system features have high reliability and good flexibility.
引文
[1]孙玉,数字复接技术,北京:人民邮电出版社,1983,15~53
[2]孙萍萍,顾美康,基于FPGA的数字复接器的设计,中小企业科技,2007(7): 177~178
[3]黄智伟,FPGA系统设计与实践,北京:电子工业出版社,2005,294~299
[4]潘松,黄继业,EDA技术实用教程,北京:科学出版社,2005,1~30
[5]刘昌华,数字逻辑EDA设计与实践:MAX+plusⅡ与QuartusⅡ双剑合璧,北京:国防工业出版社,2006,206~276
[6]刘皖,何道君,谭明,FPGA设计与应用,北京:清华大学出版社,2006,1~13
[7]胡振华,VHDL与FPGA设计,北京:中国铁道出版社,2003,232~244
[8]Haytham Azmia, Hamed Elsimary, M. Ibrahim Youssef etal, FPGA based multistandard configurable FSK demodulator, Integration, 2003, 36(3):145~154
[9]张兴旺,基于FPGA的同步数字分接设计,广西轻工业,2007(10):42~48
[10]辛春艳,VHDL硬件描述语言,北京:国防工业出版社,2002,15~48
[11]侯伯亨,顾新,VHDL硬件描述语言与数字逻辑电路设计,西安:西安电子科技大学出版社,1997,11~318
[12]徐慧,徐锋,2FSK信号产生器的FPGA设计,现代电子技术,2005(22):60~61
[13]王志,周剑扬,陈辉煌,同步数字复接的设计及其FPGA实现,电子技术应用,2005(4):24~26
[14]曾繁泰,陈美金,VHDL程序设计,.北京:清华大学出版社,2001,30~78
[15]李洪伟,袁斯华,基于QuartusⅡ的FPGA/CPLD设计,北京:电子工业出版社,2006,19~68
[16]Wayne Wolf, FPGA-based system design,北京:机械工业出版社,2006,204~ 210
[17]张明,Verilog HDL实用教程,成都:电子科技大学出版社,1999,1~213
[18]段吉海,黄智伟,基于CPLD/FPGA的数字通信系统建模与设计,北京:电子工业出版社,2004,109~137
[19]樊昌信,徐炳祥,吴成柯等,通信原理,北京:国防工业出版社,2001,78~107
[20]Bernard Sklar, Digital communications: Fundamentals and Application(徐平平,宋铁成,叶芝慧),北京:电子工业出版社,2002,458~489
[21]潘长勇,王劲涛,杨知行,现代通信原理实验,北京:清华大学出版社,2005,66~77
[22]桑林,郝建军,刘丹谱,数字通信,北京:北京邮电大学出版社,2002,33~49
[23]狄京,张申,庄乾启等,基于CPLD的锁相位同步信号提取技术,工矿自动化,2004(5):12~14
[24]李学桂,王晓明,向国菊,数字通信系统位同步电路设计,青岛大学学报(工程技术版),2000,15(01):13~16
[25]褚振勇,翁木云,FPGA设计与应用,西安:西安电子科技大学出版社,1997, 11~318
[26]林建中,王缨,郭世满,数字传输技术基础,北京:北京邮电大学出版社, 2003,72~92
[27]杜慧敏,李宥谋,赵全良,基于Verilog的FPGA设计基础,西安:西安电子科技大学出版社,2006,18~23
[28]张应中,张德民,温瞽荣,数字通信工程.北京:人民邮电出版社,1996, 33~68
[29]Uwe Meyer Baese, Digital signal processing with field programmable gate arrays,北京:清华大学出版社,2001,45~56
[30]刘宇,陈文艺,SDH中E1接1:2数字分接复用器VHDL设计及FPGA实现,电子技术应用,2006(5):44~47
[31]曹志刚,钱亚生,现代通信原理,北京:清华大学出版社,1992,206~223
[32]樊昌信,张甫翊,徐炳祥,通信原理(第五版),北京:国防工业出版社,2001,236~278
[33]田智生,基于锁相环的精确自动增益控制电路,现代电子技术,2005,28(3): 16~17
[34]梅灿华,张潜,基于FPGA的键控移频调制解调器的设计与实现,安徽大学学报(自然科学版),2003,27(2):22~27
[35]吴玉成,许太火,王黎明,帧同步电路的设计,现代电子技术,2003,38(4): 28~36
[36]F.Baronti,P.C Adell,W.T. Holman, R.D Schrimpf,DC/DC Switching Power Conv erter with Radiation Hardened Digital Control Based on SRAM FPGAs, FPGA/CPLD, 2005, 15(10):51~58
[37]Benjamin J. Patella, Aleksandar Prodic, Art Zirger and Dragan, Maksimovic High-frequency Digital PWM Controller IC for DC/DC Converters, IEEE Tractions vol 18, January 2003,PP:438~446
[38]张厥盛,郑继禹,锁相技术,西安:西安电子科技大学出版社,1994,29~60
[39]夏宇闻,Verilog数字系统设计教程,北京:北京航空航天大学出版社,2003,1~74
[40]陈萍,韩玉芬,现代通信实验系统的计算机仿真,北京:国防工业出版社, 2003,214~218
[41]黄仁欣,EDA技术实用教程,北京:清华大学出版社,2006,72~80
[2]孙萍萍,顾美康,基于FPGA的数字复接器的设计,中小企业科技,2007(7): 177~178
[3]黄智伟,FPGA系统设计与实践,北京:电子工业出版社,2005,294~299
[4]潘松,黄继业,EDA技术实用教程,北京:科学出版社,2005,1~30
[5]刘昌华,数字逻辑EDA设计与实践:MAX+plusⅡ与QuartusⅡ双剑合璧,北京:国防工业出版社,2006,206~276
[6]刘皖,何道君,谭明,FPGA设计与应用,北京:清华大学出版社,2006,1~13
[7]胡振华,VHDL与FPGA设计,北京:中国铁道出版社,2003,232~244
[8]Haytham Azmia, Hamed Elsimary, M. Ibrahim Youssef etal, FPGA based multistandard configurable FSK demodulator, Integration, 2003, 36(3):145~154
[9]张兴旺,基于FPGA的同步数字分接设计,广西轻工业,2007(10):42~48
[10]辛春艳,VHDL硬件描述语言,北京:国防工业出版社,2002,15~48
[11]侯伯亨,顾新,VHDL硬件描述语言与数字逻辑电路设计,西安:西安电子科技大学出版社,1997,11~318
[12]徐慧,徐锋,2FSK信号产生器的FPGA设计,现代电子技术,2005(22):60~61
[13]王志,周剑扬,陈辉煌,同步数字复接的设计及其FPGA实现,电子技术应用,2005(4):24~26
[14]曾繁泰,陈美金,VHDL程序设计,.北京:清华大学出版社,2001,30~78
[15]李洪伟,袁斯华,基于QuartusⅡ的FPGA/CPLD设计,北京:电子工业出版社,2006,19~68
[16]Wayne Wolf, FPGA-based system design,北京:机械工业出版社,2006,204~ 210
[17]张明,Verilog HDL实用教程,成都:电子科技大学出版社,1999,1~213
[18]段吉海,黄智伟,基于CPLD/FPGA的数字通信系统建模与设计,北京:电子工业出版社,2004,109~137
[19]樊昌信,徐炳祥,吴成柯等,通信原理,北京:国防工业出版社,2001,78~107
[20]Bernard Sklar, Digital communications: Fundamentals and Application(徐平平,宋铁成,叶芝慧),北京:电子工业出版社,2002,458~489
[21]潘长勇,王劲涛,杨知行,现代通信原理实验,北京:清华大学出版社,2005,66~77
[22]桑林,郝建军,刘丹谱,数字通信,北京:北京邮电大学出版社,2002,33~49
[23]狄京,张申,庄乾启等,基于CPLD的锁相位同步信号提取技术,工矿自动化,2004(5):12~14
[24]李学桂,王晓明,向国菊,数字通信系统位同步电路设计,青岛大学学报(工程技术版),2000,15(01):13~16
[25]褚振勇,翁木云,FPGA设计与应用,西安:西安电子科技大学出版社,1997, 11~318
[26]林建中,王缨,郭世满,数字传输技术基础,北京:北京邮电大学出版社, 2003,72~92
[27]杜慧敏,李宥谋,赵全良,基于Verilog的FPGA设计基础,西安:西安电子科技大学出版社,2006,18~23
[28]张应中,张德民,温瞽荣,数字通信工程.北京:人民邮电出版社,1996, 33~68
[29]Uwe Meyer Baese, Digital signal processing with field programmable gate arrays,北京:清华大学出版社,2001,45~56
[30]刘宇,陈文艺,SDH中E1接1:2数字分接复用器VHDL设计及FPGA实现,电子技术应用,2006(5):44~47
[31]曹志刚,钱亚生,现代通信原理,北京:清华大学出版社,1992,206~223
[32]樊昌信,张甫翊,徐炳祥,通信原理(第五版),北京:国防工业出版社,2001,236~278
[33]田智生,基于锁相环的精确自动增益控制电路,现代电子技术,2005,28(3): 16~17
[34]梅灿华,张潜,基于FPGA的键控移频调制解调器的设计与实现,安徽大学学报(自然科学版),2003,27(2):22~27
[35]吴玉成,许太火,王黎明,帧同步电路的设计,现代电子技术,2003,38(4): 28~36
[36]F.Baronti,P.C Adell,W.T. Holman, R.D Schrimpf,DC/DC Switching Power Conv erter with Radiation Hardened Digital Control Based on SRAM FPGAs, FPGA/CPLD, 2005, 15(10):51~58
[37]Benjamin J. Patella, Aleksandar Prodic, Art Zirger and Dragan, Maksimovic High-frequency Digital PWM Controller IC for DC/DC Converters, IEEE Tractions vol 18, January 2003,PP:438~446
[38]张厥盛,郑继禹,锁相技术,西安:西安电子科技大学出版社,1994,29~60
[39]夏宇闻,Verilog数字系统设计教程,北京:北京航空航天大学出版社,2003,1~74
[40]陈萍,韩玉芬,现代通信实验系统的计算机仿真,北京:国防工业出版社, 2003,214~218
[41]黄仁欣,EDA技术实用教程,北京:清华大学出版社,2006,72~80