余数系统模加法器与模乘法器设计
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摘要
由于普通二进制系统的有权性,不可避免的存在着随位宽增加而增加的进位延迟。因此,乘加运算模块的进位链往往制约了数字处理系统的速度;而在余数系统(Residue Number System)中,普通二进制系统中的计算表现为位宽大大减小的模运算,各个模运算分支之间具有天然的独立、并行特性,因此,余数系统中的乘加运算延迟大大减小,这在通信和信息处理系统中有着巨大的应用潜力。在余数系统中,模加法器与模乘法器属于最基本也是最重要的算术运算单元,因此提高余数系统中模加法器与模乘法器的性能具有重要意义。
本文研究的内容主要有:系统的总结了余数系统的背景及其相关理论;讨论了传统二进制数值表征系统的加法器与乘法器的设计,以及在此基础上的余数系统模加法器与模乘法器的设计方法;并根据本文提出的进位修正算法,实现了余数基为2 n ? (2 n?2+ 1)和2 n ? (2 n?1? 1)的高效模加法器设计方法;同时,结合了余数系统的2P缩放理论,提出了能避免溢出的有符号数在余数系统中具有2P缩放能力的高精度模乘法器的算法及实现。
Accroding to the positional property in the binary system, the carry chain in the addtion and multiplication increase with the word length, therefore become the bottleneck of the speed; While in the Residue Number System (RNS), integer in the binary number system is decomposed into several small ones with short word length excuting modular arithmetic, and the computation can be performed independently and simultaneously, so RNS has a great petential in communication and information system applications. In RNS, the critical path is greatly decided by multiplication and addition, thus, it is very important to enhance the performance of the modular addition and modular multiplication for RNS.
In this paper, We focus on the structures of fundmentel modular adders and multipliers. We propose high performance modular 2 n ? (2 n?2+ 1) and 2 n ? (2 n?1? 1) adders based on the carry modification algorithm proposed in this paper. Accoding to the 2P scaling theory, We also propose the high efficiency auto scaling modular multiplier for signed numbers in RNS which could avoid the overflow problem.
本文研究的内容主要有:系统的总结了余数系统的背景及其相关理论;讨论了传统二进制数值表征系统的加法器与乘法器的设计,以及在此基础上的余数系统模加法器与模乘法器的设计方法;并根据本文提出的进位修正算法,实现了余数基为2 n ? (2 n?2+ 1)和2 n ? (2 n?1? 1)的高效模加法器设计方法;同时,结合了余数系统的2P缩放理论,提出了能避免溢出的有符号数在余数系统中具有2P缩放能力的高精度模乘法器的算法及实现。
Accroding to the positional property in the binary system, the carry chain in the addtion and multiplication increase with the word length, therefore become the bottleneck of the speed; While in the Residue Number System (RNS), integer in the binary number system is decomposed into several small ones with short word length excuting modular arithmetic, and the computation can be performed independently and simultaneously, so RNS has a great petential in communication and information system applications. In RNS, the critical path is greatly decided by multiplication and addition, thus, it is very important to enhance the performance of the modular addition and modular multiplication for RNS.
In this paper, We focus on the structures of fundmentel modular adders and multipliers. We propose high performance modular 2 n ? (2 n?2+ 1) and 2 n ? (2 n?1? 1) adders based on the carry modification algorithm proposed in this paper. Accoding to the 2P scaling theory, We also propose the high efficiency auto scaling modular multiplier for signed numbers in RNS which could avoid the overflow problem.
引文
[1] Liu Y and Lai E M-K. Design and implementation of an RNS-based 2-D DWT processor. IEEE Trans on Consumer Electronics, Vol. 50, No. 1, February 2004: 376~385
[2] Keshab K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley & Sons Inc., 1999.
[3] The International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, San Jose, CA, 2001).
[4] www.intel.com
[5] Jose A. B. Fortes, Future Challenges in VLSI System Desgin, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI’03..
[6] Ananth Grama et al., Introduction to Parallel Computing, the Benjamin Cummings Publishing company, 2003.
[7] E.赫克,王元.代数数理论讲义.北京:科学出版社,2005。
[8]胡剑浩,“基于余数系统的VLSI设计技术及其在电子科技大学的研究进展”大会特邀报告,第五届中国通信集成电路技术与应用研讨会,西安,2007。
[9] Wei Wang and M.O. Ahmad, RNS Application for Digital Image Processing, Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’04)
[10] A.S. Madhukumar and Francois Chin, Enhanced Architecture for Residue Number System-Based CDMA for High-Rate Data Transmission, IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 3, NO. 5, SEPTEMBER 2004.
[11] 11 Conway R. and Nelson J., Improved RNS FIR filter architectures, IEEE Trans. on circuit and systems II, Volume 51, Issue 1, Jan 2004.
[12] Lie-Liang Yang,, and Lajos Hanzo, A Residue Number System Based Parallel Communication Scheme Using Orthogonal Signaling: Part I—System Outline, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 51, NO. 6, NOVEMBER 2002, pp.1534-1546
[13] Lie-Liang Yang, and Lajos Hanzo, A Residue Number System Based Parallel Communication Scheme Using Orthogonal Signaling: Part II—Multipath Fading Channels, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 51, NO. 6, NOVEMBER 2002, pp.1547-1559
[14] Ming-Hwa Sheu, Su-Hon Lin, Chichyang Chen, and Shyue-Wen Yang, An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli (2n-3, 2n+1, 2n-1, 2n+3), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 3, MARCH 2004
[15] Ahmad A. Hiasat, VLSI Implementation of New Arithmetic Residue to Binary Decoders, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 1, JANUARY 2005.
[16] Leonel Sousa, Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli, 18th IEEE Symposium on Computer Arithmetic(ARITH'07).
[17] Tadeusz Tomczak, Fast Sign Detection for RNS(2n-1,2n,2n+1), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008, pp.1502-1511
[18] Ma Shang, Hu Jianhao, Zhang Lin, Ling Xiang An efficient RNS parity checker for moduli set {2 n ? 1, 2 n + 1, 22 n + 1} and its applications, Science in China Series F: Information Sciences, vol. 51, no. 8, Aug. 2008, pp.1-9.
[19] Shang Ma, Jianhao Hu, Lin Zhang, Xiang Lin, An Efficient 2n RNS Scaler and Its VLSI Implementation, ICCCAS’08
[20] Wei Wang, M.N.S. Swamy, M.O. Ahmad. Moduli Selection in RNS for Efficient VLSI Implementation. IEEE 2003,3:7803-7761
[21] Ricardo Chaves, Leonel Sousa. {2n + 1, 2n+k, 2n ? 1}: A New RNS Moduli Set Extension Proceedings of the EUROMICRO Systems on Digital System Design. IEEE 2004,3:7695-2203
[22] Henkelmaizii, W. Anlzeiev. IMPLEMENTATION OF SIGN DETECTION IN RNS USING MIXED RADIX REPRESENTATION. IEEE, 1999,99:7803-5682
[23] Wei Wang, M. N. S. Swamy, M. O. Ahmad, and Yuke Wang. A High-Speed Residue-to-Binary onverter for Three-Moduli {2k, 2k-1, 2k-1-1} RNS and a Scheme for Its VLSI Implementation . IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, 2000,VOL. 47:1564-1571
[24] Wei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang. A Study of the Residue-to-Binary Converters for the Three-Moduli Sets. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS. 2003,VOL.50, NO. 2
[25] Yuke Wang, Xiaoyu Song, Mostapha Aboulhamid, Hong Shen. Adder Based Residue to Binary Number Converters for {2n, 2n-1, 2n+1}. IEEE TRANSACTIONS ON SIGNAL PROCESSING.2002, VOL. 50, NO. 7
[26] Ma Shang, Hujianhao, Zhanglin, Ling Xiang. An Efficient RNS Parity Checker for Moduli set {2n-1, 2n+1, 22n+1} and Its Applications. (Soon be appeared on Science in China)
[27] Lu M and Chiang J S. A novel division algorithm for the Residue Number System. IEEE Trans on Computers. 1992,Vol.4: 1026-1032
[28] Suk J-H, Youn J-S and Kim H-G, et al. A parity checker for a large residue numbers based Montgomery Reduction Method. IEICE Trans on Electronics 2005,VOL.(9): 1880-1885
[29] U. Mayer-Base and T. Stouraitis. New power-of-two scaling scheme for cell-based IC design. IEEE Trans. VLSI Syst, 2003,vol. 11:446-450
[30] Neil Burgess. Scaling an RNS number using the core function
[31] N. Burgess. Scaled and unscaled residue number system to binary conversion techniques using the core function. in Proc. of 13th Symposium on Computer Arithmetic, 1997:250–257
[32] Braden Philips. Saling and Reduction in the Residue Number System with Pairs of Conjugate Moduli. IEEE, 2003, VOL.4:7803-8104
[33] U. Mayer-Base and T. Stouraitis. New power-of-two scaling scheme for cell-based IC design. IEEE Trans. VLSI Syst, 2003,vol. 11:446-450
[34] G.C. Cardarilli, A. Del Re, A. Nannarelli. Programmable Power-of-two RNS Scaler and its Application to a QRNS Polyphase Filter. IEEE,2005,VOL.8:7803-8834
[35] Riyaz A. Patel, Mohammed Benaissa, Neil Powell, and Said Boussakta,“Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition”
[36] X. Lai and J. L. Massey. A proposal for a new block encryption standard. In Advances inCryptology– EUROCRYPT’90, pages 389–404, Berlin, Germany: Springer-Verlag, 1990.
[37] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor. Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, New York, 1986.
[38] A. Hiasat,“A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form 2 n ? (2 p+ / ? 1),”The Computer J., vol. 47, no. 1, pp. 93-102, Jan. 2004
[39] R.A. Patel, M. Benaissa and S. Boussakta,“Fast Modulo 2 n ? (2 n?2+ 1)Addition: A New Class of Adder for RNS”。
[40]岳旸,马上,胡剑浩,“基于进位修正算法的2 n ? (2 n?2+ 1)模加法器设计”,2008中国通信集成电路技术与应用研讨会。
[41] R. Zimmermann,“Binary Adder Architectures for Cell-Based VLSI and Their Synthesis,”PhD thesis, Integrated Systems Laboratory, Swiss Federal Inst. of Technology, Zurich, 1997.
[42] K.M. Elleithy and M.A. Bayoumi. 1995 A systolic architecture for modulo multiplication. IEEE Transactions on Circuits and Systems–II , 42(11):725–729.
[43] S. J. Piestrak. 1993. Design of residue generators and multi-operand modular adders using carry-save adders. IEEE Transactions on Computers, 43(1):68–77.
[44] W. H. Jenkins and B. J. Leon. 1977. The use of residue number systems in the design of finite impulse response filters. IEEE Transactions on Circuits and Systems, CAS-24(4):191–201.
[45] A. R. Omondi. 1993. Computer Arithmetic Systems. Prentice-Hall, UK.
[46] B. Parhami. 2000. Computer Arithmetic. Oxford University Press, UK.
[47] M. J. Flynn and S. F. Oberman. 2001. Advanced Computer Arithmetic. Wiley, New York.
[48] Vassilis Paliouras, Konstantina Karagianni, and Thanos Stouraitis,"A Low-Complexity Combinatorial RNS Multiplier",IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 7, pp. 675~683, JULY 2001
[49] R. Zimmerman. 1999“E?cient VLSI implementation of modulo 2n±1 addition and multiplication”. In: Proceedings, 14th Symposium on Computer Arithmetic, pp.158–167.
[50] S. J. Piestrak. 1993. Design of residue generators and multi-operand modular adders using carry-save adders. IEEE Transactions on Computers, 43(1):68–77.
[51] M. Dasygenis, K. Mitroglou, D. Soudris, and A. Thanailakis ,“A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System”,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 2, MARCH 2008
[52] T. S. D. J. Soudris, V. Paliouras, and C. Goutis,“A VLSI design methodology for RNS full-adder-based inner product architectures,”IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 4, pp. 315–318, Apr. 1997.
[53]马上、胡剑浩、张林、凌翔,“一种高效的余数系统2n缩放方法及VLSI实现”,待发表
[54] A. Beaumont-Smith and C.-C. Lim, 2001.“Parallel prefix adder design”. In: Proceedings, 15th International Symposium on Computer Arithmetic.
[55] R. P. Brent and H. T. Kung, 1982. A regular layout for parallel adders. IEEE Transactions on Computers, C-31(3):260–264.
[56] M. A. Bayoumi, G. A. Jullien, and W. C. Miller, 1987. A VLSI implementation of residue adders. IEEE Transactions on Circuits and Systems, CAS-34(3):284–287.
[57] R. W. Doran, 1988. Variants on an improved carry-lookahead adder. IEEE Transactions onComputers, 37(9):1110–1113.
[58] R. E. Ladner andM. J. Fischer,“Parallel prefix computation,”J. Assoc. Computing Machinery, vol. 27, no. 4, pp. 831–8, Oct. 1980.
[59] P. M. Kogge and H. S. Stone,“A parallel algorithm for the efficient solution of a general class of recurrence equations,”IEEE Trans.Comput., vol. C-22, no. 8, pp. 786–92, Aug. 1973.
[60] S. Knowles,“A family of adders,”in Proc. 15th IEEE Symp. Comput.Arith. (ARITH-15), Vail, CO, Jun. 2001, pp. 277–81
[2] Keshab K. Parhi, VLSI Digital Signal Processing Systems Design and Implementation, John Wiley & Sons Inc., 1999.
[3] The International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, San Jose, CA, 2001).
[4] www.intel.com
[5] Jose A. B. Fortes, Future Challenges in VLSI System Desgin, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, ISVLSI’03..
[6] Ananth Grama et al., Introduction to Parallel Computing, the Benjamin Cummings Publishing company, 2003.
[7] E.赫克,王元.代数数理论讲义.北京:科学出版社,2005。
[8]胡剑浩,“基于余数系统的VLSI设计技术及其在电子科技大学的研究进展”大会特邀报告,第五届中国通信集成电路技术与应用研讨会,西安,2007。
[9] Wei Wang and M.O. Ahmad, RNS Application for Digital Image Processing, Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’04)
[10] A.S. Madhukumar and Francois Chin, Enhanced Architecture for Residue Number System-Based CDMA for High-Rate Data Transmission, IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL. 3, NO. 5, SEPTEMBER 2004.
[11] 11 Conway R. and Nelson J., Improved RNS FIR filter architectures, IEEE Trans. on circuit and systems II, Volume 51, Issue 1, Jan 2004.
[12] Lie-Liang Yang,, and Lajos Hanzo, A Residue Number System Based Parallel Communication Scheme Using Orthogonal Signaling: Part I—System Outline, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 51, NO. 6, NOVEMBER 2002, pp.1534-1546
[13] Lie-Liang Yang, and Lajos Hanzo, A Residue Number System Based Parallel Communication Scheme Using Orthogonal Signaling: Part II—Multipath Fading Channels, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 51, NO. 6, NOVEMBER 2002, pp.1547-1559
[14] Ming-Hwa Sheu, Su-Hon Lin, Chichyang Chen, and Shyue-Wen Yang, An Efficient VLSI Design for a Residue to Binary Converter for General Balance Moduli (2n-3, 2n+1, 2n-1, 2n+3), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: EXPRESS BRIEFS, VOL. 51, NO. 3, MARCH 2004
[15] Ahmad A. Hiasat, VLSI Implementation of New Arithmetic Residue to Binary Decoders, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 1, JANUARY 2005.
[16] Leonel Sousa, Efficient Method for Magnitude Comparison in RNS Based on Two Pairs of Conjugate Moduli, 18th IEEE Symposium on Computer Arithmetic(ARITH'07).
[17] Tadeusz Tomczak, Fast Sign Detection for RNS(2n-1,2n,2n+1), IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 6, JULY 2008, pp.1502-1511
[18] Ma Shang, Hu Jianhao, Zhang Lin, Ling Xiang An efficient RNS parity checker for moduli set {2 n ? 1, 2 n + 1, 22 n + 1} and its applications, Science in China Series F: Information Sciences, vol. 51, no. 8, Aug. 2008, pp.1-9.
[19] Shang Ma, Jianhao Hu, Lin Zhang, Xiang Lin, An Efficient 2n RNS Scaler and Its VLSI Implementation, ICCCAS’08
[20] Wei Wang, M.N.S. Swamy, M.O. Ahmad. Moduli Selection in RNS for Efficient VLSI Implementation. IEEE 2003,3:7803-7761
[21] Ricardo Chaves, Leonel Sousa. {2n + 1, 2n+k, 2n ? 1}: A New RNS Moduli Set Extension Proceedings of the EUROMICRO Systems on Digital System Design. IEEE 2004,3:7695-2203
[22] Henkelmaizii, W. Anlzeiev. IMPLEMENTATION OF SIGN DETECTION IN RNS USING MIXED RADIX REPRESENTATION. IEEE, 1999,99:7803-5682
[23] Wei Wang, M. N. S. Swamy, M. O. Ahmad, and Yuke Wang. A High-Speed Residue-to-Binary onverter for Three-Moduli {2k, 2k-1, 2k-1-1} RNS and a Scheme for Its VLSI Implementation . IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, 2000,VOL. 47:1564-1571
[24] Wei Wang, M. N. S. Swamy, M. Omair Ahmad, Yuke Wang. A Study of the Residue-to-Binary Converters for the Three-Moduli Sets. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: FUNDAMENTAL THEORY AND APPLICATIONS. 2003,VOL.50, NO. 2
[25] Yuke Wang, Xiaoyu Song, Mostapha Aboulhamid, Hong Shen. Adder Based Residue to Binary Number Converters for {2n, 2n-1, 2n+1}. IEEE TRANSACTIONS ON SIGNAL PROCESSING.2002, VOL. 50, NO. 7
[26] Ma Shang, Hujianhao, Zhanglin, Ling Xiang. An Efficient RNS Parity Checker for Moduli set {2n-1, 2n+1, 22n+1} and Its Applications. (Soon be appeared on Science in China)
[27] Lu M and Chiang J S. A novel division algorithm for the Residue Number System. IEEE Trans on Computers. 1992,Vol.4: 1026-1032
[28] Suk J-H, Youn J-S and Kim H-G, et al. A parity checker for a large residue numbers based Montgomery Reduction Method. IEICE Trans on Electronics 2005,VOL.(9): 1880-1885
[29] U. Mayer-Base and T. Stouraitis. New power-of-two scaling scheme for cell-based IC design. IEEE Trans. VLSI Syst, 2003,vol. 11:446-450
[30] Neil Burgess. Scaling an RNS number using the core function
[31] N. Burgess. Scaled and unscaled residue number system to binary conversion techniques using the core function. in Proc. of 13th Symposium on Computer Arithmetic, 1997:250–257
[32] Braden Philips. Saling and Reduction in the Residue Number System with Pairs of Conjugate Moduli. IEEE, 2003, VOL.4:7803-8104
[33] U. Mayer-Base and T. Stouraitis. New power-of-two scaling scheme for cell-based IC design. IEEE Trans. VLSI Syst, 2003,vol. 11:446-450
[34] G.C. Cardarilli, A. Del Re, A. Nannarelli. Programmable Power-of-two RNS Scaler and its Application to a QRNS Polyphase Filter. IEEE,2005,VOL.8:7803-8834
[35] Riyaz A. Patel, Mohammed Benaissa, Neil Powell, and Said Boussakta,“Novel Power-Delay-Area-Efficient Approach to Generic Modular Addition”
[36] X. Lai and J. L. Massey. A proposal for a new block encryption standard. In Advances inCryptology– EUROCRYPT’90, pages 389–404, Berlin, Germany: Springer-Verlag, 1990.
[37] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor. Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. IEEE Press, New York, 1986.
[38] A. Hiasat,“A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form 2 n ? (2 p+ / ? 1),”The Computer J., vol. 47, no. 1, pp. 93-102, Jan. 2004
[39] R.A. Patel, M. Benaissa and S. Boussakta,“Fast Modulo 2 n ? (2 n?2+ 1)Addition: A New Class of Adder for RNS”。
[40]岳旸,马上,胡剑浩,“基于进位修正算法的2 n ? (2 n?2+ 1)模加法器设计”,2008中国通信集成电路技术与应用研讨会。
[41] R. Zimmermann,“Binary Adder Architectures for Cell-Based VLSI and Their Synthesis,”PhD thesis, Integrated Systems Laboratory, Swiss Federal Inst. of Technology, Zurich, 1997.
[42] K.M. Elleithy and M.A. Bayoumi. 1995 A systolic architecture for modulo multiplication. IEEE Transactions on Circuits and Systems–II , 42(11):725–729.
[43] S. J. Piestrak. 1993. Design of residue generators and multi-operand modular adders using carry-save adders. IEEE Transactions on Computers, 43(1):68–77.
[44] W. H. Jenkins and B. J. Leon. 1977. The use of residue number systems in the design of finite impulse response filters. IEEE Transactions on Circuits and Systems, CAS-24(4):191–201.
[45] A. R. Omondi. 1993. Computer Arithmetic Systems. Prentice-Hall, UK.
[46] B. Parhami. 2000. Computer Arithmetic. Oxford University Press, UK.
[47] M. J. Flynn and S. F. Oberman. 2001. Advanced Computer Arithmetic. Wiley, New York.
[48] Vassilis Paliouras, Konstantina Karagianni, and Thanos Stouraitis,"A Low-Complexity Combinatorial RNS Multiplier",IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 7, pp. 675~683, JULY 2001
[49] R. Zimmerman. 1999“E?cient VLSI implementation of modulo 2n±1 addition and multiplication”. In: Proceedings, 14th Symposium on Computer Arithmetic, pp.158–167.
[50] S. J. Piestrak. 1993. Design of residue generators and multi-operand modular adders using carry-save adders. IEEE Transactions on Computers, 43(1):68–77.
[51] M. Dasygenis, K. Mitroglou, D. Soudris, and A. Thanailakis ,“A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System”,IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 55, NO. 2, MARCH 2008
[52] T. S. D. J. Soudris, V. Paliouras, and C. Goutis,“A VLSI design methodology for RNS full-adder-based inner product architectures,”IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 4, pp. 315–318, Apr. 1997.
[53]马上、胡剑浩、张林、凌翔,“一种高效的余数系统2n缩放方法及VLSI实现”,待发表
[54] A. Beaumont-Smith and C.-C. Lim, 2001.“Parallel prefix adder design”. In: Proceedings, 15th International Symposium on Computer Arithmetic.
[55] R. P. Brent and H. T. Kung, 1982. A regular layout for parallel adders. IEEE Transactions on Computers, C-31(3):260–264.
[56] M. A. Bayoumi, G. A. Jullien, and W. C. Miller, 1987. A VLSI implementation of residue adders. IEEE Transactions on Circuits and Systems, CAS-34(3):284–287.
[57] R. W. Doran, 1988. Variants on an improved carry-lookahead adder. IEEE Transactions onComputers, 37(9):1110–1113.
[58] R. E. Ladner andM. J. Fischer,“Parallel prefix computation,”J. Assoc. Computing Machinery, vol. 27, no. 4, pp. 831–8, Oct. 1980.
[59] P. M. Kogge and H. S. Stone,“A parallel algorithm for the efficient solution of a general class of recurrence equations,”IEEE Trans.Comput., vol. C-22, no. 8, pp. 786–92, Aug. 1973.
[60] S. Knowles,“A family of adders,”in Proc. 15th IEEE Symp. Comput.Arith. (ARITH-15), Vail, CO, Jun. 2001, pp. 277–81