高速ADC时钟发生器的设计与实现
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摘要
在高速ADC中,高精度的时钟是整个芯片正常工作的保证,为了解决片外时钟的噪声、延时以及频率单一等问题,就需要在高速ADC中嵌入一个高精度的时钟发生器,来满足高速ADC对于时序的要求。基于锁相环的时钟发生器是一个可产生当今系统中所需的各种频率的低成本高效率方案,能够达到对于延迟和抖动等重要参数的更严格要求,但随着时钟频率的提高,锁相环的设计难度不断加大,而且功耗问题也尤为突出,在高频情况下更是如此。因此对于时钟发生器来说,提出新的设计方案就很有实用价值。本课题就是针对这一问题,综合考虑延时、功耗、面积等各种重要因素,设计了一种适用于500M Hz pipleline ADC的时钟发生器。
本次设计采用TSMC 0.18 m m工艺实现,在延迟锁相环的基础上进行了重新设计,降低了时钟发生器的设计难度和功耗,设计主要分为三个模块:时钟缓冲电路、时钟占空比调节电路和时钟分频电路。时钟缓冲器采用差分Bicmos结构实现,可以有效的对时钟信号进行放大,提高时钟信号的驱动能力;时钟占空比调节电路采用基于延迟锁相环的改进电路来实现,主要分为频率合成器、电荷泵检测电路、延迟电路和整形器,其功能是用来调节外部时钟的占空比,以达到ADC对于时钟精度的要求;时钟分频电路主要完成对时钟信号进行分频的功能。当时钟发生器开始工作时,来自外部的时钟信号,经过时钟发生器的处理后,得到稳定的占空比为50%的时钟信号,作为采样保持电路的控制信号和其他ADC模块的时钟同步信号。
In high-speed ADC, the high-precision clock is the guarantee of the entire chip. in order to solve the proplems such as noise, delay, single frequency and so on, we have to embed a high-precision clock generator into the high-speed ADC to meet the timing requirements of the high-speed ADC. Nowadays, the clock generator based on PLL is such a proposal that can provide a variety of frequencies with lower cost and more efficient. It also can meet the requirements of the important parameters of delay and jitter. But with the increasing of clock frequency, the design of PLL is becoming more and more difficulty, and the consumption of power is particularly prominent, especially in high frequency. Therefore, It is practical to propose a new design of clock generator. To the question, the delay, power, area and other important factors are considered and a clock generator that is suitable for 500M Hz pipleline ADC is designed.
The design is achieved by TSMC 0.18 m mprocess. It is based on the delay-locked loop and redesigned to reduce the difficulty and power. The design consists of three modules: the clock buffer circuit, the duty-cycle correction circuit and frequency divider circuit. The clock buffer circuit is realized by the bicmos structure, it can efficiently zoom in the signal of clock and increase the driver ability of the signal. The duty-cycle correction circuit is based on the DLL circuit.It can be mainly divided into frequency synthesizer, charge pump detection circuit, delay circuit and shaper. It is used to adjust the duty-cycle of the clock to meet the precision requirements of ADC. The frequency divider circuit mainly completes the function of dividing frequence. A stable 50% duty -cycle clock is produced after the external clock is processed by the clock generator, and then it works as the control signals in the sample and holding circuit or the synchronization signals of other modules.
本次设计采用TSMC 0.18 m m工艺实现,在延迟锁相环的基础上进行了重新设计,降低了时钟发生器的设计难度和功耗,设计主要分为三个模块:时钟缓冲电路、时钟占空比调节电路和时钟分频电路。时钟缓冲器采用差分Bicmos结构实现,可以有效的对时钟信号进行放大,提高时钟信号的驱动能力;时钟占空比调节电路采用基于延迟锁相环的改进电路来实现,主要分为频率合成器、电荷泵检测电路、延迟电路和整形器,其功能是用来调节外部时钟的占空比,以达到ADC对于时钟精度的要求;时钟分频电路主要完成对时钟信号进行分频的功能。当时钟发生器开始工作时,来自外部的时钟信号,经过时钟发生器的处理后,得到稳定的占空比为50%的时钟信号,作为采样保持电路的控制信号和其他ADC模块的时钟同步信号。
In high-speed ADC, the high-precision clock is the guarantee of the entire chip. in order to solve the proplems such as noise, delay, single frequency and so on, we have to embed a high-precision clock generator into the high-speed ADC to meet the timing requirements of the high-speed ADC. Nowadays, the clock generator based on PLL is such a proposal that can provide a variety of frequencies with lower cost and more efficient. It also can meet the requirements of the important parameters of delay and jitter. But with the increasing of clock frequency, the design of PLL is becoming more and more difficulty, and the consumption of power is particularly prominent, especially in high frequency. Therefore, It is practical to propose a new design of clock generator. To the question, the delay, power, area and other important factors are considered and a clock generator that is suitable for 500M Hz pipleline ADC is designed.
The design is achieved by TSMC 0.18 m mprocess. It is based on the delay-locked loop and redesigned to reduce the difficulty and power. The design consists of three modules: the clock buffer circuit, the duty-cycle correction circuit and frequency divider circuit. The clock buffer circuit is realized by the bicmos structure, it can efficiently zoom in the signal of clock and increase the driver ability of the signal. The duty-cycle correction circuit is based on the DLL circuit.It can be mainly divided into frequency synthesizer, charge pump detection circuit, delay circuit and shaper. It is used to adjust the duty-cycle of the clock to meet the precision requirements of ADC. The frequency divider circuit mainly completes the function of dividing frequence. A stable 50% duty -cycle clock is produced after the external clock is processed by the clock generator, and then it works as the control signals in the sample and holding circuit or the synchronization signals of other modules.
引文
[1]H-C-Yang, L-K-Lee, and R-S-Co,“A Low Jitter 0-3-165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation”, IEEE Journal of Solid-state Circuits, vol-32, No-4, Apr- 1997.
[2]王钊,“CMOS锁相电路的设计研究”,北京大学硕士研究生学位论文,2001.
[3]Sanchez S.E.Silver M.J.Embabi S.H.K.A 2.4GHz Monolithic Fractional-N Frequency Synthesizer with robust phase switching prescaler and loop capacitance multiplier.IEEE Journal of solid-state circuits.2003.June,Vol.38(6).p.866-874.
[4]张厥盛、郑继禹、万心平。锁相技术[M]。西安:西安电子科技大学出版社,2002.
[5]Behzad Razavi,“Design of Analog CMOS Integrated Circuits”, McGraw-Hill Higher Education, 2001.
[6]I- M- Filanovsky, Yiu Fai Chan,“BiCMOS Cascaded Bandgap Voltage Reference”, IEEE 1997 Custom Integrated Circuits Conference, 1997.
[7]Roland E.Best.锁相环设计、仿真与应用。李永明等译。北京:清华大学出版社,2007.
[8]Luiz L- G- Vermaas, Carlos R- T- de Mori, Robson L- Moreno, Adriano M- Pereira, Edger Charry R-,“A Bandgap Voltage Reference Using Digital CMOS”, IEEE 1998 Custom Integrated Circuits Conference, 1998.
[9]郭建楠。CMOS电荷泵锁相环中的数字电路设计[D].西安:西安电子科技大学,2007.
[10]John A- McNeill,“Jitter in Ring Oscillators”, IEEE Journal of Solid-State Circuits, vol-32, No-6, June 1997.
[11]Frank Herzel, and Behzad Razavi,“Oscillator Jitter Due to Supply and Substrate Noise”, IEEE 1998 Custom Integrated Circuits Conference, 1998.
[12]李桂华,孙仲林,吉利久.CMOS锁相环PLL的设计研究[J].半导体杂志。2000.9:30-37.
[13]Terry Lee , Micron , and Bryan Belk . DDR SDRAM signaling Design Notes.MicroLinear Corporation,1 999(4):25—33.
[14]刘天伟,戴庆元,杨运福。一种低电压无死区鉴频鉴相器[J]。微处理机。2006(3):78-84.
[15]JEDEC DDR SDRAM Specification 64 MEG:x4,x8,x 1 6,Revision 0.9,1 999(7):42-50
[16]戴逸民著.频率合成与锁相技术.中国科学技术大学出版社,1985.
[17]杨丰林,沈绪榜.锁相环在处理器时钟设计中的应用.微电子学与计算机,2002(6):115-121.
[18]何小威,李少青,唐世民.一种用于微处理器的高频锁相环设计与实现.第十届计算机工程与工艺学术年会,2006:265.259.
[19]何小威.应用于PCI.Express的1.25GHz高性能锁相环的设计与实现.国防科学技术大学硕士学位论文,2006.
[20]陈艳。高性能电荷泵鉴相器的设计[D]。南京:东南大学,2004.
[21]李亮.FPGA中基于DLL的时钟网络的设计.西安电子科技大学学位论文,2008.
[22] Roland E.Best.锁相环设计、仿真与应用.清华大学出版,2003. [23吴玲玲。电荷泵锁相环的后端设计[D]。合肥:合肥工业大学,2004.
[24]魏建玮,张迎雪。锁相环技术综述。科技信息[学术版]。2008(36):190. [25]PLL Performance Simulation and Design 3rd Edition,2003.
[26]姜炜阳。基于DLL的高频时钟产生电路的研究与设计。上海:上海大学,2007.
[27]Behzad Razavi.Design of Analog CMOS Integrated Circuits.McGraw-Hill Companies,2002.
[28]吴宏.模拟锁相环的研究与实现.国防科技大学硕士学位沦文,2002.
[2]王钊,“CMOS锁相电路的设计研究”,北京大学硕士研究生学位论文,2001.
[3]Sanchez S.E.Silver M.J.Embabi S.H.K.A 2.4GHz Monolithic Fractional-N Frequency Synthesizer with robust phase switching prescaler and loop capacitance multiplier.IEEE Journal of solid-state circuits.2003.June,Vol.38(6).p.866-874.
[4]张厥盛、郑继禹、万心平。锁相技术[M]。西安:西安电子科技大学出版社,2002.
[5]Behzad Razavi,“Design of Analog CMOS Integrated Circuits”, McGraw-Hill Higher Education, 2001.
[6]I- M- Filanovsky, Yiu Fai Chan,“BiCMOS Cascaded Bandgap Voltage Reference”, IEEE 1997 Custom Integrated Circuits Conference, 1997.
[7]Roland E.Best.锁相环设计、仿真与应用。李永明等译。北京:清华大学出版社,2007.
[8]Luiz L- G- Vermaas, Carlos R- T- de Mori, Robson L- Moreno, Adriano M- Pereira, Edger Charry R-,“A Bandgap Voltage Reference Using Digital CMOS”, IEEE 1998 Custom Integrated Circuits Conference, 1998.
[9]郭建楠。CMOS电荷泵锁相环中的数字电路设计[D].西安:西安电子科技大学,2007.
[10]John A- McNeill,“Jitter in Ring Oscillators”, IEEE Journal of Solid-State Circuits, vol-32, No-6, June 1997.
[11]Frank Herzel, and Behzad Razavi,“Oscillator Jitter Due to Supply and Substrate Noise”, IEEE 1998 Custom Integrated Circuits Conference, 1998.
[12]李桂华,孙仲林,吉利久.CMOS锁相环PLL的设计研究[J].半导体杂志。2000.9:30-37.
[13]Terry Lee , Micron , and Bryan Belk . DDR SDRAM signaling Design Notes.MicroLinear Corporation,1 999(4):25—33.
[14]刘天伟,戴庆元,杨运福。一种低电压无死区鉴频鉴相器[J]。微处理机。2006(3):78-84.
[15]JEDEC DDR SDRAM Specification 64 MEG:x4,x8,x 1 6,Revision 0.9,1 999(7):42-50
[16]戴逸民著.频率合成与锁相技术.中国科学技术大学出版社,1985.
[17]杨丰林,沈绪榜.锁相环在处理器时钟设计中的应用.微电子学与计算机,2002(6):115-121.
[18]何小威,李少青,唐世民.一种用于微处理器的高频锁相环设计与实现.第十届计算机工程与工艺学术年会,2006:265.259.
[19]何小威.应用于PCI.Express的1.25GHz高性能锁相环的设计与实现.国防科学技术大学硕士学位论文,2006.
[20]陈艳。高性能电荷泵鉴相器的设计[D]。南京:东南大学,2004.
[21]李亮.FPGA中基于DLL的时钟网络的设计.西安电子科技大学学位论文,2008.
[22] Roland E.Best.锁相环设计、仿真与应用.清华大学出版,2003. [23吴玲玲。电荷泵锁相环的后端设计[D]。合肥:合肥工业大学,2004.
[24]魏建玮,张迎雪。锁相环技术综述。科技信息[学术版]。2008(36):190. [25]PLL Performance Simulation and Design 3rd Edition,2003.
[26]姜炜阳。基于DLL的高频时钟产生电路的研究与设计。上海:上海大学,2007.
[27]Behzad Razavi.Design of Analog CMOS Integrated Circuits.McGraw-Hill Companies,2002.
[28]吴宏.模拟锁相环的研究与实现.国防科技大学硕士学位沦文,2002.
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