CMOS单片收发机多模小数频率综合器的设计
|
摘要
随着无线通讯技术的不断发展以及多种无线通讯协议的推出,可满足多种通讯协议的单芯片全集成无线收发器芯片成为集成电路设计者研究的热点之一。这就要求无线收发机中的关键模块频率综合器提供高度稳定的、复用性强的、低相位噪声的本振信号以满足多种通讯协议需要。为此,半导体通信芯片厂商和研究所、高校等科研单位研发出了各种多模多频的频率综合器芯片或IP核。本论文就同时支持UHF RFID、WCDMA、TD-WCDMA、IEEE 802.11a/b/g协议的单芯片宽带多模多频小数分频频率综合器展开了研究,取得了以下的成果：
1、首先回顾了锁相环频率综合器的结构,阐述了delta-sigma调制器技术实现小数分频频率综合器的基本原理,以及整个环路参数和相位噪声的建模。
2、对目前几种常见的宽带频率综合器实现方案进行了分析比较,提出了一种新型的宽带频率综合器的系统方案。在该方案中,仅采用一个3-4GHz低噪声LCVCO和一个5～6GHz低功耗LC VCO实现了频率范围从0.8GHz～5.55GHz的宽带频率输出信号。
3、对于系统中的关键模块压控振荡器,采用对称LC滤波网络、高Q值的差分电感以及套筒式误差反馈放大器组成的片上LDO设计方法,对尾管噪声、LC谐振器噪声、电源噪声分别抑制来提高VCO相位噪声性能。
4、针对小数频率综合器中的Delta-sigma调制器,提出了一种三阶四比特误差反馈型增量总和调制器,其电路结构复杂度低,易于实现。该调制器已应用到了设计中,实现了较小的频率分辨率和较好的带外杂散性能。
5、采用0.13μm 1P8M RF CMOS工艺实现了一款频率范围为0.7GHz～5.55GHz的小数分频频率综合器。芯片总面积为2.2mm×2.2mm。测试结果表明：功耗为250mW时,最低输出频率700MHz,1MHz频偏处相位噪声为-128dBc/Hz;最大输出频率5.55GHz时,3MHz频偏处的相位噪声为-124dBc/Hz,可以同时满足UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g协议的频率转换要求。
With the continuous development of wireless communication technology and the introduction of a variety of wireless communication protocols, fully integrated single-chip wireless transceiver become the most popular research focus. This requires frequency synthesizer (the key module to the wireless transceiver) to provide highly stable, high reusability, low phase noise local oscillator signal to meet the needs of a variety of communication protocols. So, communications IC manufacturers and IC designers in universities and other research institutes have developed a lot of multi-mode multi-band frequency synthesizer chips or IP cores. A frequency synthesizer is proposed for the UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g in this thesis.
First, structures of phase locked loop are reviewed. The basic principles, loop parameter and phase noise of delta-sigma fractional-N frequency synthesizer are analyzed.
Then, several broadband frequency synthesizer implementation methods are compared.A new frequency synthesizer structure is proposed. A 3-4GHz low phase noise LC VCO and a 5-6GHz low power LC VCO combined with two CML prescalers make the frequency synthesizer conver output frequency range from 0.8GHz to 6GHz。
For low phase noise VCO design, three methods are adopted. On-chip LDO is utilized to suppress noise from power supply. Symmetrical noise filtering technique is used to suppress thermal noise from tail current and parasitic resistors of bonding wires.High quality factor inductor up to 16 can lower the phase noise obviously.
A third order four bits output delta-sigma modulator is implented with serveral accumulator and D flip-flops.
A frequency tuning range from 0.7GHz to 5.55GHz delta-sigma fractional-N synthesizer is implemented with 0.13μm 1P8M RFCMOS. The die size is 2.2mm×2.2mm. Measurement results indicate:total power is 250mW;the minimum frequency is 700MHz, with phase noise-128dBc/Hz@1MHz; the maxium frequency is 5.55GHz with phase noise-124dBc/Hz@3MHz;phase noise merits can meet UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g communicaiton specifications.
This thesis's work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number: 2009ZX01034-002-002-001-02).
1、首先回顾了锁相环频率综合器的结构,阐述了delta-sigma调制器技术实现小数分频频率综合器的基本原理,以及整个环路参数和相位噪声的建模。
2、对目前几种常见的宽带频率综合器实现方案进行了分析比较,提出了一种新型的宽带频率综合器的系统方案。在该方案中,仅采用一个3-4GHz低噪声LCVCO和一个5～6GHz低功耗LC VCO实现了频率范围从0.8GHz～5.55GHz的宽带频率输出信号。
3、对于系统中的关键模块压控振荡器,采用对称LC滤波网络、高Q值的差分电感以及套筒式误差反馈放大器组成的片上LDO设计方法,对尾管噪声、LC谐振器噪声、电源噪声分别抑制来提高VCO相位噪声性能。
4、针对小数频率综合器中的Delta-sigma调制器,提出了一种三阶四比特误差反馈型增量总和调制器,其电路结构复杂度低,易于实现。该调制器已应用到了设计中,实现了较小的频率分辨率和较好的带外杂散性能。
5、采用0.13μm 1P8M RF CMOS工艺实现了一款频率范围为0.7GHz～5.55GHz的小数分频频率综合器。芯片总面积为2.2mm×2.2mm。测试结果表明：功耗为250mW时,最低输出频率700MHz,1MHz频偏处相位噪声为-128dBc/Hz;最大输出频率5.55GHz时,3MHz频偏处的相位噪声为-124dBc/Hz,可以同时满足UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g协议的频率转换要求。
With the continuous development of wireless communication technology and the introduction of a variety of wireless communication protocols, fully integrated single-chip wireless transceiver become the most popular research focus. This requires frequency synthesizer (the key module to the wireless transceiver) to provide highly stable, high reusability, low phase noise local oscillator signal to meet the needs of a variety of communication protocols. So, communications IC manufacturers and IC designers in universities and other research institutes have developed a lot of multi-mode multi-band frequency synthesizer chips or IP cores. A frequency synthesizer is proposed for the UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g in this thesis.
First, structures of phase locked loop are reviewed. The basic principles, loop parameter and phase noise of delta-sigma fractional-N frequency synthesizer are analyzed.
Then, several broadband frequency synthesizer implementation methods are compared.A new frequency synthesizer structure is proposed. A 3-4GHz low phase noise LC VCO and a 5-6GHz low power LC VCO combined with two CML prescalers make the frequency synthesizer conver output frequency range from 0.8GHz to 6GHz。
For low phase noise VCO design, three methods are adopted. On-chip LDO is utilized to suppress noise from power supply. Symmetrical noise filtering technique is used to suppress thermal noise from tail current and parasitic resistors of bonding wires.High quality factor inductor up to 16 can lower the phase noise obviously.
A third order four bits output delta-sigma modulator is implented with serveral accumulator and D flip-flops.
A frequency tuning range from 0.7GHz to 5.55GHz delta-sigma fractional-N synthesizer is implemented with 0.13μm 1P8M RFCMOS. The die size is 2.2mm×2.2mm. Measurement results indicate:total power is 250mW;the minimum frequency is 700MHz, with phase noise-128dBc/Hz@1MHz; the maxium frequency is 5.55GHz with phase noise-124dBc/Hz@3MHz;phase noise merits can meet UHF RFID、WCDMA、TD-SCDMA、IEEE 802.11 a/b/g communicaiton specifications.
This thesis's work is supported by project "Key IP cores design for the embedded multi-mode multi-band transceiver" under the state key item of "core electronic devices, high-end general chips and basic software product" (Project number: 2009ZX01034-002-002-001-02).
引文
[1]ETSI 302 208-1 ERM; RFID operating in the band 865 MHz to 868 MHz with power levels up to 2 W; Part 1:Technical requirements and methods of measure-ment. http://www.ETSI.org.
[2]EPC radio-frequency identity protocols C1G2 UHF RFID protocol for communi cations at 860-960 MHz. http://www.epcglobalinc.org.
[3]Information technology-radio frequency identification (RFID) for item manage-ment-Part6:parameters for air interface communications at 860-930 MHz.
[4]张润曦,“超高频射频识别阅读器集成技术研究,”华东师范大学博士论文,2009年。
[5]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Higher-Speed Physical Layer Extension in the 2.4 GHz Band," Piscataway, New Jersey,1999.
[6]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Higher-Speed Physical Layer in the 5 GHz Band," Piscataway, New Jersey,1999.
[7]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Further Higher Data Rate Extension in the 2.4 GHz Band," Piscataway, New Jersey,2003.
[8]Pengfei Zhang, Lawrence Der, Dawei Guo, et al. "A Single-Chip Dual-band Direct-Conversion IEEE 802.11 a/b/g WLAN Transceiver in0.18-um CMOS", IEEE Journal of Solid-State Circuits, Sep.2005,40(9):1909-1921.
[9]J. Ryynanen et al. "A single-chip multi-mode receiver for GSM900, DCS 1800, PCS 1900, and WCDMA" IEEE Journal of Solid-State Circuits, Apr.2004,38(4):594-602.
[10]Massimo Brandolini, Paolo Rossi, Danilo Manstretta, and Francesco Svelto. "Toward Multistandard Mobile Terminals-Fully Integrated Receivers Requirements and Architectures ", IEEE Transcations on Microwave Theory and Techniques, March 2005,53(3):1026-1037
[11]Martin Simon, Peter Laaser, Voicu Filimon, Hans Geltinger, et al."An 802.11 a/b/g RF Transceiver in an SOC" IEEE International Solid-State Circuits Conference, Feb.2007,562-563.
[12]Adil Koukab, Yu Lei, Michel J. Declercq. " A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11 a/b/g Multi-standard Carrier Generation System" IEEE Journal of Solid-State Circuits, July 2006,41(7):1513-1521
[13]www.analog.com/zh/rfif-components/ADF4350
[14]黄德平, “应用于无线通信多模接收机的频率综合器的研究与设计”复旦大学硕士论文,2010年。
[15]陈虎,“应用于无线通信的CMOS频率综合器的研究和设计”复旦大学硕士论文,2010年。
[16]柴璐,"CMMB移动数字电视调谐器中频率综合器的研究与设计”复旦大学硕士论文,2010年。
[17]成诗伟, “2.4GHz宽环路带宽分数分频频率综合器的研究与设计”复旦大学硕士论文,2010年。
[18]孟令部, “2～2.4GHz分数分频频率综合器的设计”复旦大学硕士论文,2010年。
[19]陈丹凤“OFDM超宽带系统的频率综合器设计方法研究”复旦大学博士论文,2010年。
[20]杨丰林,'UHF RFID阅读器中delta-sigma fractional-N频率合成器的研究”,复旦大学博士论文,2006年。
[21]何伟,“多模多频无线收发机中小数频率综合器的研究”,华东师范大学硕士论文,2010年。
[22]D. Guermandi, P. Tortori, E. Franchi, and A. Gnudi, A 0.83 to 2.5GHz Continuously Tunable Quadrature VCO[J]. IEEE J.Solid-State Circuits,2005,40 (12):2620-2627.
[23]石春琦,“超高频RFID阅读器中Δ∑小数分频频率综合器的优化设计”,华东师范大学博士论文,2009年。
[24]卢磊“射频接收机中分数分频频率综合器的研究与设计”复旦大学博士论文,2010年。
[25]杨文荣,"CMOS单片集成的∑-Δ小数频率合成器设计”,上海大学博士论文,2005年。
[26]T. H. Lee, The Design of CMOS Radio Frequency Integrated Cireuits,2nd Edition,2004.
[27]T. C. Lee et al., "A stabilization technique for phase-locked frequency syn-thesizers," IEEE J. Solid-State Circuit, vol.38, no.6, p.888-894, Jun.2003.
[28]T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol.28, no.5, pp. 553-559, May 1993.
[29]Maciej Jan Borkowski, et al., "A practical Δ-Σ modulator design method based on periodical behavior analysis," IEEE Transaction on Circuits and Systems-Ⅱ: Express Briefs, vol.52, no.10, Oct.2005.
[30]陈永聪,“集成CMOS锁相环中抑制参考杂散的设计方法,”半导体学报,vol.27, no.12, Dec.2006。
[31]3GPP TS 25.101 V8.4.03rd Generation Partnership Project:Technical Specification Group Radio Aecess Network;User Equipment (UE) radio transmission and reception(FDD)(Release 8)[S],2008.
[32]TS C401V3.0.0 China Wireless Telecommunication Standard(CWTS);Working Group 1(WG1):TD-SCDMA(UE):Radio Transmission and Reception[S],1999.
[33]Specification of the Bluetooth System, Version 2.0[S]. Nov 04,2004.
[34]IEEE Std 802.11b-1999.Part 11:Wireless LAN Medium Access Control(MAC) and Physical Layer(PHY) specifieations:Higher-Speed Physical Layer Extension in the 2.4GHz Band[S].LAN/MAN Standards Committee of the IEEE Computer Society,1999.
[35]ISO/EEC 8802-11:1999/Amd 1:2000(E).Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer(PHY) specifications:High-speed Physical Layer in the 5 GHz Band.LAN/MAN Standards Committee of the IEEE.
[36]IEEE Std 802.11g-2003.Part 11:Wireless LAN Medium Access Control(MAC) and Physical Layer(PHY) spceifications:Amendment 4:Further Higher Data Rate Extension in the 2.4GHz Band.
[37]李勇,"802.11 a/b/g WLAN射频接收机中CMOS压控振荡器设计研究”华东师范大学硕士论文,2007年。
[38]D.B.Leeson, "A simple model of feedback oscillator noise spectrum," Proc. IEEE, vol.54, no.2, pp.329-330, Feb.1966.
[39]J.Craninckx and M. Steyaert, "Low-noise voltage-controlled oscillators using enhanced LC-tanks,"IEEE Trans. Circuits Syst.-II, vol.42, pp.794-904,Dec.1995
[40]Emad Hegazi, Jacob Rael, Asad Abidi, "The designer's guide to high-purity oscillators," Kluwer Academic Publishers,2005.
[41]A. Hajimiri, T.H. Lee, "A general theory of phase noise in electrical oscillators," IEEE, J. Solid-State Circuits, vol.33, no.2, pp.179-194, Feb.1998.
[42]唐长文,“电感电容压控振荡器”复旦大学博士论文,2004年。
[43]S. Levantino, C. Samori, A. Bonfanti,S.L.J. Gierkink,A. L. Lacaita and V. Boccuzzi, "frequency dependence on bias current in 5GHz CMOS VCOs:Impact on tuning range and flicker noise upconversion," IEEE J. Solid-State Circuits,vol. 37,pp.1003-1011,Aug.2002.
[44]杨丰林,"UHF RFID阅读器中delta-sigma fractional-N频率合成器的研究”,复旦大学博士论文,2006年。
[45]P. Andreani and H. Sjoland, "Tail current noise suppression in RF CMOS VCOs," IEEE J. Solid-State Circuits.vol.37,pp.342-348,Mar.2002.
[46]Shuai Xu, "Design of a Wideband and Low Phase Noise LC VCO", International Conference on Solid-State and Integrated Circuit Technology, vol.3, pp1080-1092, Nov.2010.
[47]Behzad Razavi.Design of analog CMOS integrated circuits. The Mc Graw-Hill Companies 2001:483.
[48]Ullas Singh & Michael Green, "Dynamics of high-frequency CMOS dividers," IEEE. Circuits and Systems, ISCAS 2002.
[49]S. K. Mitra著,孙洪,余翔宇等译,数字信号处理——基于计算机的方法(第二版),电子工业出版社,2005年。
[50]W. Rhee et al., "A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ-Σ modulator," IEEE J. Solid-State Circuit, vol.35, no.10, pp.1453-1460, Oct,2000.
[51]Ashok Swaminathan, Kevin J. Wang, and Ian Galton, "A wide-bandwidth 2.4GHz ISM band fractional-N PLL with adaptive phase noise cancellation", IEEE J. Solid-State Circuits, Vol.42, No.12, pp.2639-2650, Dec.2007.
[52]B. D. Muer et al.,"A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuit, vol.37, no.7, p.835-844, July 2002.
[53]T. Musch, I. Rolfes and B. Schiek, "A highly linear frequency ramp generator based on a fractional divider phase-locked loop," IEEE Transaction Instruments Measurements, vol.48, no.1,1999.
[54]B. Razavi, RF Microelectronics, Prentice Hall,2000.
[55]Floyd M. Gardner, "Charge-pump phase-lock loops", IEEE Trans, on Commu-nications, vol.28, no.11, pp.1849-1858,1980.
[56]Keliu shu, Edgar Sanchez-Sinencio, CMOS PLL synthesizer:analysis and de-sign, Springer,2005.
[2]EPC radio-frequency identity protocols C1G2 UHF RFID protocol for communi cations at 860-960 MHz. http://www.epcglobalinc.org.
[3]Information technology-radio frequency identification (RFID) for item manage-ment-Part6:parameters for air interface communications at 860-930 MHz.
[4]张润曦,“超高频射频识别阅读器集成技术研究,”华东师范大学博士论文,2009年。
[5]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Higher-Speed Physical Layer Extension in the 2.4 GHz Band," Piscataway, New Jersey,1999.
[6]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Higher-Speed Physical Layer in the 5 GHz Band," Piscataway, New Jersey,1999.
[7]Institute of Electrical and Electronics Engineers (IEEE), "Supplement to IEEE Standard for Information Technology—Telecommunications and Information Exchange between Systems—Local and Metropolitan Area Networks—Specific Requirements Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications:Further Higher Data Rate Extension in the 2.4 GHz Band," Piscataway, New Jersey,2003.
[8]Pengfei Zhang, Lawrence Der, Dawei Guo, et al. "A Single-Chip Dual-band Direct-Conversion IEEE 802.11 a/b/g WLAN Transceiver in0.18-um CMOS", IEEE Journal of Solid-State Circuits, Sep.2005,40(9):1909-1921.
[9]J. Ryynanen et al. "A single-chip multi-mode receiver for GSM900, DCS 1800, PCS 1900, and WCDMA" IEEE Journal of Solid-State Circuits, Apr.2004,38(4):594-602.
[10]Massimo Brandolini, Paolo Rossi, Danilo Manstretta, and Francesco Svelto. "Toward Multistandard Mobile Terminals-Fully Integrated Receivers Requirements and Architectures ", IEEE Transcations on Microwave Theory and Techniques, March 2005,53(3):1026-1037
[11]Martin Simon, Peter Laaser, Voicu Filimon, Hans Geltinger, et al."An 802.11 a/b/g RF Transceiver in an SOC" IEEE International Solid-State Circuits Conference, Feb.2007,562-563.
[12]Adil Koukab, Yu Lei, Michel J. Declercq. " A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11 a/b/g Multi-standard Carrier Generation System" IEEE Journal of Solid-State Circuits, July 2006,41(7):1513-1521
[13]www.analog.com/zh/rfif-components/ADF4350
[14]黄德平, “应用于无线通信多模接收机的频率综合器的研究与设计”复旦大学硕士论文,2010年。
[15]陈虎,“应用于无线通信的CMOS频率综合器的研究和设计”复旦大学硕士论文,2010年。
[16]柴璐,"CMMB移动数字电视调谐器中频率综合器的研究与设计”复旦大学硕士论文,2010年。
[17]成诗伟, “2.4GHz宽环路带宽分数分频频率综合器的研究与设计”复旦大学硕士论文,2010年。
[18]孟令部, “2～2.4GHz分数分频频率综合器的设计”复旦大学硕士论文,2010年。
[19]陈丹凤“OFDM超宽带系统的频率综合器设计方法研究”复旦大学博士论文,2010年。
[20]杨丰林,'UHF RFID阅读器中delta-sigma fractional-N频率合成器的研究”,复旦大学博士论文,2006年。
[21]何伟,“多模多频无线收发机中小数频率综合器的研究”,华东师范大学硕士论文,2010年。
[22]D. Guermandi, P. Tortori, E. Franchi, and A. Gnudi, A 0.83 to 2.5GHz Continuously Tunable Quadrature VCO[J]. IEEE J.Solid-State Circuits,2005,40 (12):2620-2627.
[23]石春琦,“超高频RFID阅读器中Δ∑小数分频频率综合器的优化设计”,华东师范大学博士论文,2009年。
[24]卢磊“射频接收机中分数分频频率综合器的研究与设计”复旦大学博士论文,2010年。
[25]杨文荣,"CMOS单片集成的∑-Δ小数频率合成器设计”,上海大学博士论文,2005年。
[26]T. H. Lee, The Design of CMOS Radio Frequency Integrated Cireuits,2nd Edition,2004.
[27]T. C. Lee et al., "A stabilization technique for phase-locked frequency syn-thesizers," IEEE J. Solid-State Circuit, vol.38, no.6, p.888-894, Jun.2003.
[28]T. A. D. Riley, M. A. Copeland and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE J. Solid-State Circuits, vol.28, no.5, pp. 553-559, May 1993.
[29]Maciej Jan Borkowski, et al., "A practical Δ-Σ modulator design method based on periodical behavior analysis," IEEE Transaction on Circuits and Systems-Ⅱ: Express Briefs, vol.52, no.10, Oct.2005.
[30]陈永聪,“集成CMOS锁相环中抑制参考杂散的设计方法,”半导体学报,vol.27, no.12, Dec.2006。
[31]3GPP TS 25.101 V8.4.03rd Generation Partnership Project:Technical Specification Group Radio Aecess Network;User Equipment (UE) radio transmission and reception(FDD)(Release 8)[S],2008.
[32]TS C401V3.0.0 China Wireless Telecommunication Standard(CWTS);Working Group 1(WG1):TD-SCDMA(UE):Radio Transmission and Reception[S],1999.
[33]Specification of the Bluetooth System, Version 2.0[S]. Nov 04,2004.
[34]IEEE Std 802.11b-1999.Part 11:Wireless LAN Medium Access Control(MAC) and Physical Layer(PHY) specifieations:Higher-Speed Physical Layer Extension in the 2.4GHz Band[S].LAN/MAN Standards Committee of the IEEE Computer Society,1999.
[35]ISO/EEC 8802-11:1999/Amd 1:2000(E).Part 11:Wireless LAN Medium Access Control (MAC) and Physical Layer(PHY) specifications:High-speed Physical Layer in the 5 GHz Band.LAN/MAN Standards Committee of the IEEE.
[36]IEEE Std 802.11g-2003.Part 11:Wireless LAN Medium Access Control(MAC) and Physical Layer(PHY) spceifications:Amendment 4:Further Higher Data Rate Extension in the 2.4GHz Band.
[37]李勇,"802.11 a/b/g WLAN射频接收机中CMOS压控振荡器设计研究”华东师范大学硕士论文,2007年。
[38]D.B.Leeson, "A simple model of feedback oscillator noise spectrum," Proc. IEEE, vol.54, no.2, pp.329-330, Feb.1966.
[39]J.Craninckx and M. Steyaert, "Low-noise voltage-controlled oscillators using enhanced LC-tanks,"IEEE Trans. Circuits Syst.-II, vol.42, pp.794-904,Dec.1995
[40]Emad Hegazi, Jacob Rael, Asad Abidi, "The designer's guide to high-purity oscillators," Kluwer Academic Publishers,2005.
[41]A. Hajimiri, T.H. Lee, "A general theory of phase noise in electrical oscillators," IEEE, J. Solid-State Circuits, vol.33, no.2, pp.179-194, Feb.1998.
[42]唐长文,“电感电容压控振荡器”复旦大学博士论文,2004年。
[43]S. Levantino, C. Samori, A. Bonfanti,S.L.J. Gierkink,A. L. Lacaita and V. Boccuzzi, "frequency dependence on bias current in 5GHz CMOS VCOs:Impact on tuning range and flicker noise upconversion," IEEE J. Solid-State Circuits,vol. 37,pp.1003-1011,Aug.2002.
[44]杨丰林,"UHF RFID阅读器中delta-sigma fractional-N频率合成器的研究”,复旦大学博士论文,2006年。
[45]P. Andreani and H. Sjoland, "Tail current noise suppression in RF CMOS VCOs," IEEE J. Solid-State Circuits.vol.37,pp.342-348,Mar.2002.
[46]Shuai Xu, "Design of a Wideband and Low Phase Noise LC VCO", International Conference on Solid-State and Integrated Circuit Technology, vol.3, pp1080-1092, Nov.2010.
[47]Behzad Razavi.Design of analog CMOS integrated circuits. The Mc Graw-Hill Companies 2001:483.
[48]Ullas Singh & Michael Green, "Dynamics of high-frequency CMOS dividers," IEEE. Circuits and Systems, ISCAS 2002.
[49]S. K. Mitra著,孙洪,余翔宇等译,数字信号处理——基于计算机的方法(第二版),电子工业出版社,2005年。
[50]W. Rhee et al., "A 1.1GHz CMOS fractional-N frequency synthesizer with a 3-b third-order Δ-Σ modulator," IEEE J. Solid-State Circuit, vol.35, no.10, pp.1453-1460, Oct,2000.
[51]Ashok Swaminathan, Kevin J. Wang, and Ian Galton, "A wide-bandwidth 2.4GHz ISM band fractional-N PLL with adaptive phase noise cancellation", IEEE J. Solid-State Circuits, Vol.42, No.12, pp.2639-2650, Dec.2007.
[52]B. D. Muer et al.,"A CMOS monolithic ΔΣ-controlled fractional-N frequency synthesizer for DCS-1800," IEEE J. Solid-State Circuit, vol.37, no.7, p.835-844, July 2002.
[53]T. Musch, I. Rolfes and B. Schiek, "A highly linear frequency ramp generator based on a fractional divider phase-locked loop," IEEE Transaction Instruments Measurements, vol.48, no.1,1999.
[54]B. Razavi, RF Microelectronics, Prentice Hall,2000.
[55]Floyd M. Gardner, "Charge-pump phase-lock loops", IEEE Trans, on Commu-nications, vol.28, no.11, pp.1849-1858,1980.
[56]Keliu shu, Edgar Sanchez-Sinencio, CMOS PLL synthesizer:analysis and de-sign, Springer,2005.
© 2004-2018 中国地质图书馆版权所有 京ICP备05064691号 京公网安备11010802017129号 地址：北京市海淀区学院路29号 邮编：100083 电话：办公室：(+86 10)66554848；文献借阅、咨询服务、科技查新：66554700 |