65nm CMOS 10MHz-1.2GHz宽带可编程锁相环设计
摘要
1932年,贝尔赛什(Bellectze)提出了同步检波理论,首次公开了对锁相环的论述。随着集成技术的发展,特别是半导体CMOS工艺的出现,锁相技术开始在更广泛的领域得到应用,宽输入与输出范围及可以精确分频的锁相环逐渐成为人们研究的热点之一。
众所周知,锁相环系统是窄带闭环反馈系统。本文在研究锁相环理论基础上,基于65nm CMOS工艺设计实现了一款输入频率10MHz-200MHz、输出频率10MHz-1.2GHz的宽带可编程锁相环。版图后Hspice仿真表明该锁相环功能正确、性能优良,能达到预定设计要求。本文的研究工作和创新点主要包括:
1.研究了电荷泵锁相环理论,对锁相环的模型、数学推导及稳定性进行了深入研究,为本课题的锁相环宽带技术研究奠定了基础,也为今后的宽带锁相环的研究提供了思路。
2.根据锁相环宽带的要求,设计了一种由多个窄带组成的宽带锁相环结构,使锁相环输入频率范围10MHz-200MHz、输出频率范围10MHz-1.2GHz。
3.为了防止VC上的抖动对锁相环的性能造成影响,设计了一种适用于单端VCO的抖动抑制电路,可以把VC抖动对锁相环的影响降低百分之七十以上。
4.研究了数模混合锁相环的版图设计技术,对模拟电路版图做了精心的匹配设计和保护,有效减少了各种噪声的干扰,提高了锁相环的性能。
5.基于65nm CMOS工艺实现了该锁相环,该锁相环的面积0.182mm~2、功耗在最坏情况下小于10mW、VCO频率范围0.9GHz-2.5GHz、输入频率10MHz-200MHz、输出频率范围10MHz-1.2GHz、前分频器可实现1-32分频、反馈分频器可实现1-32分频、后分频器可实现1-32分频、均方根与峰峰抖动在最坏情况下输入频率50MHz、输出频率200MHz时分别为250.129ps和32.125ps。
6.对设计的锁相环进行了流片及样片测试。样片的测试结果表明:本文设计的锁相环的性能指标与模拟结果一致,满足了设计要求。
In 1932, Bellectze put forward the theory of synchronous detection, and first public the discussion of Phase-Locked Loop(PLL). With the development of integrated circuit technology, especially the emergence of CMOS semiconductor technology, the phase-lock technique has been applied widely in more fields. The precise point frequency PLL with wide input and wide output range has been gradually becoming one of the hot researches field.
It is well known that, PLL is a narrowband closed-loop feedback system. This paper, based on the theory foundation of PLL, a wideband programmable PLL is implemented in standard 65nm CMOS technology, the PLL with the input frequency between 10MHz to 200MHz and the output frequency between 10MHz to 1.2GHz. The post layout Hspice simulation indicates the PLL work correctly and with excellent performance, meanwhile the PLL can meet the predetermined design requirements. The research and innovations of this paper are basically as following:
1. Study the related theory of charge-pump PLL, and investigate the PLL model, mathematical deduction, which lays the foundation of the broad technology for future research of PLL.
2. To meet the requirement of wideband of PLL, this paper designed a wideband PLL structure which is composed of several narrowband PLL, with the input frequency range between 10MHz to 200MHz, and the output frequency range between 10MHz to 1.2GHz.
3. To eliminate the performance affect from the jitter of VC, a circuit is designed that can decrease the jitter to 70% normal value for the single-ended VCO.
4. Research the art of mixed-signal layout, and device matching and guide ring are used to reduce the effect of all kinks of noise, improving the performance of PLL.
5. The PLL is implemented in standard 65nm CMOS technology. The area of the PLL is 0.182mm~2, and the power dissipation is less than 10mW at the worst case, the frequency range of VCO is between 0.9GHz to 2.5GHz, the input frequency range is between 10MHz to 200MHz, and the output frequency range is between 10MHz to 1.2GHz. The pre-divider, feedback-divider and post-divider can achieve a frequency divide of 1-32. The RMS jitter and peak-to-peak value jitter are 250.129ps and 32.125ps respectively at the worst for input frequency of 50MHz and output frequency of 200MHz.
6. The PLL was tapouted and PLL samples have been tested. The test result of sample indicates that the performance of the PLL sample is accordance with the simulated result, meeting the the design requrements.
众所周知,锁相环系统是窄带闭环反馈系统。本文在研究锁相环理论基础上,基于65nm CMOS工艺设计实现了一款输入频率10MHz-200MHz、输出频率10MHz-1.2GHz的宽带可编程锁相环。版图后Hspice仿真表明该锁相环功能正确、性能优良,能达到预定设计要求。本文的研究工作和创新点主要包括:
1.研究了电荷泵锁相环理论,对锁相环的模型、数学推导及稳定性进行了深入研究,为本课题的锁相环宽带技术研究奠定了基础,也为今后的宽带锁相环的研究提供了思路。
2.根据锁相环宽带的要求,设计了一种由多个窄带组成的宽带锁相环结构,使锁相环输入频率范围10MHz-200MHz、输出频率范围10MHz-1.2GHz。
3.为了防止VC上的抖动对锁相环的性能造成影响,设计了一种适用于单端VCO的抖动抑制电路,可以把VC抖动对锁相环的影响降低百分之七十以上。
4.研究了数模混合锁相环的版图设计技术,对模拟电路版图做了精心的匹配设计和保护,有效减少了各种噪声的干扰,提高了锁相环的性能。
5.基于65nm CMOS工艺实现了该锁相环,该锁相环的面积0.182mm~2、功耗在最坏情况下小于10mW、VCO频率范围0.9GHz-2.5GHz、输入频率10MHz-200MHz、输出频率范围10MHz-1.2GHz、前分频器可实现1-32分频、反馈分频器可实现1-32分频、后分频器可实现1-32分频、均方根与峰峰抖动在最坏情况下输入频率50MHz、输出频率200MHz时分别为250.129ps和32.125ps。
6.对设计的锁相环进行了流片及样片测试。样片的测试结果表明:本文设计的锁相环的性能指标与模拟结果一致,满足了设计要求。
In 1932, Bellectze put forward the theory of synchronous detection, and first public the discussion of Phase-Locked Loop(PLL). With the development of integrated circuit technology, especially the emergence of CMOS semiconductor technology, the phase-lock technique has been applied widely in more fields. The precise point frequency PLL with wide input and wide output range has been gradually becoming one of the hot researches field.
It is well known that, PLL is a narrowband closed-loop feedback system. This paper, based on the theory foundation of PLL, a wideband programmable PLL is implemented in standard 65nm CMOS technology, the PLL with the input frequency between 10MHz to 200MHz and the output frequency between 10MHz to 1.2GHz. The post layout Hspice simulation indicates the PLL work correctly and with excellent performance, meanwhile the PLL can meet the predetermined design requirements. The research and innovations of this paper are basically as following:
1. Study the related theory of charge-pump PLL, and investigate the PLL model, mathematical deduction, which lays the foundation of the broad technology for future research of PLL.
2. To meet the requirement of wideband of PLL, this paper designed a wideband PLL structure which is composed of several narrowband PLL, with the input frequency range between 10MHz to 200MHz, and the output frequency range between 10MHz to 1.2GHz.
3. To eliminate the performance affect from the jitter of VC, a circuit is designed that can decrease the jitter to 70% normal value for the single-ended VCO.
4. Research the art of mixed-signal layout, and device matching and guide ring are used to reduce the effect of all kinks of noise, improving the performance of PLL.
5. The PLL is implemented in standard 65nm CMOS technology. The area of the PLL is 0.182mm~2, and the power dissipation is less than 10mW at the worst case, the frequency range of VCO is between 0.9GHz to 2.5GHz, the input frequency range is between 10MHz to 200MHz, and the output frequency range is between 10MHz to 1.2GHz. The pre-divider, feedback-divider and post-divider can achieve a frequency divide of 1-32. The RMS jitter and peak-to-peak value jitter are 250.129ps and 32.125ps respectively at the worst for input frequency of 50MHz and output frequency of 200MHz.
6. The PLL was tapouted and PLL samples have been tested. The test result of sample indicates that the performance of the PLL sample is accordance with the simulated result, meeting the the design requrements.
引文
[1]蒋召宇.CMOS锁相环时钟发生器的设计与研究[D].合肥工业大学硕士学位论文,2004.
[2]杨丰林,沈绪榜,锁相环在处理器时钟设计中的应用,微电子学与计算机[J],第6期,2002.
[3] Roland E. Best,锁相环设计、仿真与应用,清华大学出版[M],2003.
[4] Hegazi E., Sjoland H., Abidi A.. A filtering technique to lower LC oscillator phase noise[J]. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1921.
[5]张民选.SoC体系结构处理器关键技术和研发现状[J].第十三届计算机工程与工艺会议论文集,西安:西北工业大学出版社,2009:149~154.
[6]杨丰林,沈绪榜.锁相环在处理器时钟设计中的应用[J].微电子学与计算机,第6期,2002.
[7] Floyd M. Gardner. Phaselock Techniques[M] Third Edition.北京:人民邮电出版社,2007:199~206.
[8] P. K. Hanumolu. analysis of charge-pump phase-locked loops[J]. IEEE Trans on Circuits and Syst, 2004, 51(9):1665~1674.
[9] Behzad Razav. A Study of Phase Noise in CMOS Oscillators[J]. IEEE Journal of Solid-State Circuits, 1996, 31(7): 331~343.
[10] A. Viterbi. Acquisition and tracking behavior of Phase-Locked Loops. California, U.S.A: Jet Propulsion Laboratary, 1959.
[11]朱思良.快速锁定技术在锁相环中应用[J].电子测量技术,2004,3:32~33.
[12] Floyd M. Gardner. Phaselock Techniques[M] Third Edition.北京:人民邮电出版社,2007:199~206.
[13] I. Young et al. A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors[J]. IEEE J. Solid-State Circuits, 1992, 27(11):1599~1607.
[14] Behzad Razavi. Design of Analog CMOS Integrated Circuits[M]. CLUMB Xi’an Jiaotong University Press, 2003.
[15] F. Herzel and B. Razavi. A study of Oscillator Jitter Due to Supply and Substrate Noise[J]. IEEE Transactions on Circuits and Systems, Part II, 1999, Jan. 46:56~62.
[16] Johns David A., Ken Martin. Analog Integrated Circuit Dsign[M].北京:机械工业出版社,2005.
[17] F. M. Gardner. Charge-pump Phase-Lock Loops[J]. IEEE Transzceions On Communications, 1980, 28: 1849~1858.
[18]胡寿松.自动控制原理[M](第四版).北京:科学出版社,2001:68.
[19]吕郁.自适应带宽时钟发生器的抖动一致性研究[D].国防科学技术大学工学硕士学位论文,2009.
[20]白创.高性能低噪声锁相环分析与设计[D].长沙:国防科学技术大学,2009.
[21] Yan Shin Tak. A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers[D]. Hong Kong: Hong Kong University of Science and Technology, 1999: 110.
[22]薛颜.1~32倍频低抖动锁相环的设计与实现[D].国防科学技术大学工程硕士学位论文,2010.
[23]何小威.1.25GHz高性能锁相环的设计与实现[D].国防科学技术大学工学硕士学位论文,2009.
[24]赵春.电荷泵锁相环的设计与实现[D].电子科技大学学位论文,2002.
[25] Alan Hastings.模拟电路版图的艺术[M](第二版).北京:电子工业出版社,2007:6.
[26] R. Jacob Baker, Harry W. Li, David E. Boyce. CMOS Circuit Design, Layout, and Simulation[D]. China Machine Press, 2006.
[27]刘剑慰.CMOS高速锁相环设计[D].南京航空航天大学学位论文,2002.
[28] R.Jacob Baker,Harry W.Li, David E.Boyce, CMOS Circuit Design, Layout, and Simulation[J], China Machine Press, 2006
[29] Phillip E. Allen. CMOS Analog Circuit Design[D] (Second Edition).北京:电子工业出版社,2008:35~36.
[30]郑涛.宽调节范围快速捕获锁相环[D].国防科学技术大学工程硕士学位论文,2010.
[31]赵振宇.锁相环中单粒子瞬变效应的分析与加固[D].长沙:国防科学技术大学, 2009.
[32]赵振宇,陈怒兴,欧阳干.超大规模集成电路ESD保护技术[J].第八届计算机工程与工艺学术年会论文,2003.S
[33]陈一辉.高速低噪声锁相环时钟发生器的设计[J].上海:复旦大学,2003:39.
[34]周红,陈晓东.高频锁相环的可测性设计[J].中科院微电子研究所,2003.
[35] Roland E. Best. Phase-Locked Loops DESIGN, SIMULATION, AND APPLICATIONS[J].北京:清华大学出版社,2007:4.
[36]雷建武.高速LVDS I/O接口电路的设计与实现[D].长沙:国防科学技术大学, 2005.
[37] Floyd M., Gardner.锁相环技术[D].北京:人民邮电出版社,2007.
[2]杨丰林,沈绪榜,锁相环在处理器时钟设计中的应用,微电子学与计算机[J],第6期,2002.
[3] Roland E. Best,锁相环设计、仿真与应用,清华大学出版[M],2003.
[4] Hegazi E., Sjoland H., Abidi A.. A filtering technique to lower LC oscillator phase noise[J]. IEEE Journal of Solid-State Circuits, 2001, 36(12): 1921.
[5]张民选.SoC体系结构处理器关键技术和研发现状[J].第十三届计算机工程与工艺会议论文集,西安:西北工业大学出版社,2009:149~154.
[6]杨丰林,沈绪榜.锁相环在处理器时钟设计中的应用[J].微电子学与计算机,第6期,2002.
[7] Floyd M. Gardner. Phaselock Techniques[M] Third Edition.北京:人民邮电出版社,2007:199~206.
[8] P. K. Hanumolu. analysis of charge-pump phase-locked loops[J]. IEEE Trans on Circuits and Syst, 2004, 51(9):1665~1674.
[9] Behzad Razav. A Study of Phase Noise in CMOS Oscillators[J]. IEEE Journal of Solid-State Circuits, 1996, 31(7): 331~343.
[10] A. Viterbi. Acquisition and tracking behavior of Phase-Locked Loops. California, U.S.A: Jet Propulsion Laboratary, 1959.
[11]朱思良.快速锁定技术在锁相环中应用[J].电子测量技术,2004,3:32~33.
[12] Floyd M. Gardner. Phaselock Techniques[M] Third Edition.北京:人民邮电出版社,2007:199~206.
[13] I. Young et al. A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors[J]. IEEE J. Solid-State Circuits, 1992, 27(11):1599~1607.
[14] Behzad Razavi. Design of Analog CMOS Integrated Circuits[M]. CLUMB Xi’an Jiaotong University Press, 2003.
[15] F. Herzel and B. Razavi. A study of Oscillator Jitter Due to Supply and Substrate Noise[J]. IEEE Transactions on Circuits and Systems, Part II, 1999, Jan. 46:56~62.
[16] Johns David A., Ken Martin. Analog Integrated Circuit Dsign[M].北京:机械工业出版社,2005.
[17] F. M. Gardner. Charge-pump Phase-Lock Loops[J]. IEEE Transzceions On Communications, 1980, 28: 1849~1858.
[18]胡寿松.自动控制原理[M](第四版).北京:科学出版社,2001:68.
[19]吕郁.自适应带宽时钟发生器的抖动一致性研究[D].国防科学技术大学工学硕士学位论文,2009.
[20]白创.高性能低噪声锁相环分析与设计[D].长沙:国防科学技术大学,2009.
[21] Yan Shin Tak. A 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers[D]. Hong Kong: Hong Kong University of Science and Technology, 1999: 110.
[22]薛颜.1~32倍频低抖动锁相环的设计与实现[D].国防科学技术大学工程硕士学位论文,2010.
[23]何小威.1.25GHz高性能锁相环的设计与实现[D].国防科学技术大学工学硕士学位论文,2009.
[24]赵春.电荷泵锁相环的设计与实现[D].电子科技大学学位论文,2002.
[25] Alan Hastings.模拟电路版图的艺术[M](第二版).北京:电子工业出版社,2007:6.
[26] R. Jacob Baker, Harry W. Li, David E. Boyce. CMOS Circuit Design, Layout, and Simulation[D]. China Machine Press, 2006.
[27]刘剑慰.CMOS高速锁相环设计[D].南京航空航天大学学位论文,2002.
[28] R.Jacob Baker,Harry W.Li, David E.Boyce, CMOS Circuit Design, Layout, and Simulation[J], China Machine Press, 2006
[29] Phillip E. Allen. CMOS Analog Circuit Design[D] (Second Edition).北京:电子工业出版社,2008:35~36.
[30]郑涛.宽调节范围快速捕获锁相环[D].国防科学技术大学工程硕士学位论文,2010.
[31]赵振宇.锁相环中单粒子瞬变效应的分析与加固[D].长沙:国防科学技术大学, 2009.
[32]赵振宇,陈怒兴,欧阳干.超大规模集成电路ESD保护技术[J].第八届计算机工程与工艺学术年会论文,2003.S
[33]陈一辉.高速低噪声锁相环时钟发生器的设计[J].上海:复旦大学,2003:39.
[34]周红,陈晓东.高频锁相环的可测性设计[J].中科院微电子研究所,2003.
[35] Roland E. Best. Phase-Locked Loops DESIGN, SIMULATION, AND APPLICATIONS[J].北京:清华大学出版社,2007:4.
[36]雷建武.高速LVDS I/O接口电路的设计与实现[D].长沙:国防科学技术大学, 2005.
[37] Floyd M., Gardner.锁相环技术[D].北京:人民邮电出版社,2007.
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