低噪声电荷泵锁相环电路设计理论与技术
摘要
锁相环发展迅速,应用广泛,使其成为当前模拟集成电路的核心技术之一。作为通讯系统应用最为广泛的一个模块,锁相环在高速处理器的时钟产生中有着广泛的应用。处理器这类大型的数字电路在其翻转过程中将产生严重的电源、衬底噪声,这些噪声及处理器本身固有的器件噪声会对锁相环的工作性能产生极大的影响。本文针对电荷泵锁相环结构,进行了深入的理论分析,从系统的角度分析了如何减少锁相环的噪声,建立了环路对锁相环各噪声源的传递函数,并据此确定了环路参数和系统结构,根据系统的响应速度、稳定性、对噪声的抑制能力等对系统参数如何确定展开了讨论。接下来优化各模块设计来减少锁相环的噪声,对鉴频鉴相器的死区、电荷泵电流匹配、电荷共享问题、片上集成螺旋电感都作了深入研究,并采用自顶向下的方法设计了一个低噪声CMOS电荷泵锁相环。根据给定的性能指标要求,完成了系统设计,电路设计直到版图设计,并最终由IC生产厂完成芯片制造。生成高速,稳定的时钟信号是本课题的目标。
PLL is developing rapidly, that make it to be the most important core technology of current analog IC. As the most widely used module in communications system, the PLL clock is much useful in a high speed processor. Processors, such large scale digital circuits, in its turnover process will have a serious power noise and substrate noise, further more, the inherent noise of the devices in processors also has great impact on phase locked loop. Aimed at charge pump PLL, the paper analysis the theory deeply, and how to reduce the noise of PLL from the view of system, and established the noise transfer function of the PLL loop, then identified loop parameters and system architecture. It also discussed about how to determine the parameters of the system according to the response speed, stability, and the capability for noise suppression. In another hand the module had been optimized to reduce the noise in PLL. The dead zone of PFD, the current match of charge pump, charge sharing issues, on chip spiral inductors are studied deeply. By adopting the top-down method, a CMOS low noise charge pump phase locked loop is designed. According to the requirements performance indicators are set. From the system design, circuit design to layout design, PLL is completed, and eventually realized by the IC chip fabrication. Generating high speed and stable clock signal is the objective of this subject.
PLL is developing rapidly, that make it to be the most important core technology of current analog IC. As the most widely used module in communications system, the PLL clock is much useful in a high speed processor. Processors, such large scale digital circuits, in its turnover process will have a serious power noise and substrate noise, further more, the inherent noise of the devices in processors also has great impact on phase locked loop. Aimed at charge pump PLL, the paper analysis the theory deeply, and how to reduce the noise of PLL from the view of system, and established the noise transfer function of the PLL loop, then identified loop parameters and system architecture. It also discussed about how to determine the parameters of the system according to the response speed, stability, and the capability for noise suppression. In another hand the module had been optimized to reduce the noise in PLL. The dead zone of PFD, the current match of charge pump, charge sharing issues, on chip spiral inductors are studied deeply. By adopting the top-down method, a CMOS low noise charge pump phase locked loop is designed. According to the requirements performance indicators are set. From the system design, circuit design to layout design, PLL is completed, and eventually realized by the IC chip fabrication. Generating high speed and stable clock signal is the objective of this subject.
引文
铩颷1]张展鹏,低噪声 CMOS 电荷泵锁相环的研究,硕士学位论文,西安交通大学,2003年3月;
[2]超高速,CMOS锁相环集成电路设计,硕士学位论文,东南大学,2002年3月;
[3]蒋召宇,CMOS锁相环时钟发生器的设计与研究,硕士学位论文,合肥工业大学,2004年3月;
[4]杨丰林,CMOS数模混合锁相环设计及应用,硕士学位论文,华中科技大学,2003年5月;
[5]周安宇,CMOS集成锁相环设计,硕士学位论文,北京工业大学,2004年5月;
[6]刘剑慰,CMOS高速锁相环设计,硕士学位论文,南京航空航天大学,2002年2月;
[7]林蔚然,低噪声的锁相环时钟产生电路设计,硕士学位论文,复旦大学,2004年4月;
[8]Roland E.Best,李永明等译,锁相环设计、仿真与应用,清华大学出版社,2007年4月;
[9]吴煊、周帅林,切换式调谐CMOS压控振荡器,东南大学国家ASIC系统工程中心,南京;
[10]潘沙、赵辉、任俊彦,1.8GHz相位噪声优化的差分压控振荡器,复旦大学专用集成电路与系统国家重点实验室,上海;
[11]王海永、林敏、李永明、陈弘毅,一种适用于2.4GHz ISM 射频波段的全集成CMOS压控振荡器,清华大学微电子研究所,北京;
[12]邬蓉、衣晓峰、唐长文、苏彦锋、洪志良,一个1.5V低相位噪声的高频率LC压控振荡器的设计,复旦大学专用集成电路与系统国家重点实验室,上海;
[13]唐路、王志功、赵文虎,一种千兆以太网控制器中VCO的设计,东南大学射频与光电集成电路研究所,江苏;
[14]赵海兵、王志功、陈莹梅、章丽、熊明珍,多相位低相位噪声 5GHz 压控振荡器的设计,东南大学射频与光电集成电路研究所,南京;
[15]陶蕤、王志功、顾峥,低噪声集成压控振荡器噪声性能分析,东南大学,南京,210094
[16]陈莹梅、王志功、朱恩、冯军、章丽,5GHz 0.18um CMOS 工艺正交输出VCO,东南大学射频与光电集成电路研究所,南京;
[17]Zhang Haiqing and Zhang Qianling,Design of 2.5GHz Low Phase Noise CMOS LC-VCO,ASIC&System State Key Laboratory,Fudan University,Shanghai 200433,China;
[18]Hsing Hao,The Design of a CMOS VCO for a Blustooth Transceiver,Electrical andComputer Engineering Department Colorado State University;
[19]Low-Power CMOS VCO with Dual-Band Local Oscillating Signal Output for 5/2.5GHzWLAN Transceivers,Institute of Microelectronics,Tsinghua University,Beijing 100084,China;
[20]Yi Xiaofeng,Fang Han,Yang Yujia,and Hong Zhiliang,A 2.4GHz Quadrature OutputFrequency Synthesizer,ASIC&System State Key Laboratory,Fudan University,Shanghai 200433,China;
[21]PIETRO ANDREANI and SVEN MATTISSON,A 2.4GHz CMOS Monolithic VCO with an MOS Varactor,Competence Center for Circuit Design,Department of applied Electronics,Lund
University,P.O.Box 118,SE-221 00 Lund,Sweden and Ericsson Mobile Communications AB,
Mobile Phones & Terminals,Scheelevagen 15,SE-221 83 Lund,Sweden;
铩颷22]L.DERMENTZOGLOU,Y.TSIATOUHAS,A.ARAPOYANNI,A Design for TestabilityScheme for CMOS LC-Tank Voltage Controlled Oscillators;
[23]AHMED H.MOSTAFA and MOURAD N.EL-GAMAL,A CMOS VCO ArchitectureSuitable for Sub-1 Volt High-Frequency(8.7-10GHz)RF Applications,Microelectronics andComputer Systems Laboratory,Department of Electrical & Computer Engineering,McGillUniversity St.,Montreal,QC,Canada H3A 2A7;
[24]WOUTER DE COCK and MICHIEL STEYAERT,A 2.5V,10GHz Fully IntegratedLC-VCO with Integrated High-Q Inductor and 30%Tuning Range,Katholieke Universiteit Leuven,Dept.ESAT-MICAS,Kasteelpark Arenberg 10,B-3001 Leuven,Belgium;
[25]Tang Zhangwen,He Jie,Jian Hongyan,and Min Hao,An Accurate 1.08GHz CMOS LCVoltage-Controlled Oscillator,State Key Laboratory ofASIC & System,Fudan University,Shanghai,200433,China;
[26]周毅,杨利,适用于高品质射频集成电感的多孔硅新型衬底制备技术,半导体学报,2005,26,(6),1182-1186;
[27]李小进,石艳玲,硅基RF平面螺旋电感的圈数对品质因子的影响,半导体学报,2003,24,(9),972-976;
[28]张志勇,体硅CMOS射频集成电路中高Q值在片集成电感的实现,微电子学,2003,33.(1),15-18;
[29]李力南,钱鹤,RF集成电感的设计与寄生效应分析,固体电子学研究与进展,2002,22,(2),153-157;
[30]冯冠中,张玉明,硅衬底上射频集成电感研究,电子器件,2005,28,(1),25-29;
[31]刘珂,菅洪彦,多电流路径抑制片上电感电流拥挤效应,半导体学报,2006,27,(9),1690-1694;
[32]李争,李哲英,射频集成电路对称型螺旋电感研究,微电子学,2007年第3期,卷37第305-305页;
[33]唐长文,电感电容压控振荡器,博士学位论文,复旦大学,2004年4月;
[34]李争,李哲英,集成电感设计优化方法,半导体技术,2007年第2期,第154-157页;
[35]李争,李哲英,硅基集成电路电感优化设计方法,北京交通大学学报,2007年第5期;
[36]Li Zheng,Li Zheying,Optimizing Approach of Spiral Inductors for Si-Based ICs.2007 7~(th)International Conference on ASIC Proceeding.Guilin,October 2007;
[37]ASITIC:Analysis and Simulation of Spiral Inductors and Transformers for ICshttp://formosa.eecs.berkely.edu,2006,1.
[2]超高速,CMOS锁相环集成电路设计,硕士学位论文,东南大学,2002年3月;
[3]蒋召宇,CMOS锁相环时钟发生器的设计与研究,硕士学位论文,合肥工业大学,2004年3月;
[4]杨丰林,CMOS数模混合锁相环设计及应用,硕士学位论文,华中科技大学,2003年5月;
[5]周安宇,CMOS集成锁相环设计,硕士学位论文,北京工业大学,2004年5月;
[6]刘剑慰,CMOS高速锁相环设计,硕士学位论文,南京航空航天大学,2002年2月;
[7]林蔚然,低噪声的锁相环时钟产生电路设计,硕士学位论文,复旦大学,2004年4月;
[8]Roland E.Best,李永明等译,锁相环设计、仿真与应用,清华大学出版社,2007年4月;
[9]吴煊、周帅林,切换式调谐CMOS压控振荡器,东南大学国家ASIC系统工程中心,南京;
[10]潘沙、赵辉、任俊彦,1.8GHz相位噪声优化的差分压控振荡器,复旦大学专用集成电路与系统国家重点实验室,上海;
[11]王海永、林敏、李永明、陈弘毅,一种适用于2.4GHz ISM 射频波段的全集成CMOS压控振荡器,清华大学微电子研究所,北京;
[12]邬蓉、衣晓峰、唐长文、苏彦锋、洪志良,一个1.5V低相位噪声的高频率LC压控振荡器的设计,复旦大学专用集成电路与系统国家重点实验室,上海;
[13]唐路、王志功、赵文虎,一种千兆以太网控制器中VCO的设计,东南大学射频与光电集成电路研究所,江苏;
[14]赵海兵、王志功、陈莹梅、章丽、熊明珍,多相位低相位噪声 5GHz 压控振荡器的设计,东南大学射频与光电集成电路研究所,南京;
[15]陶蕤、王志功、顾峥,低噪声集成压控振荡器噪声性能分析,东南大学,南京,210094
[16]陈莹梅、王志功、朱恩、冯军、章丽,5GHz 0.18um CMOS 工艺正交输出VCO,东南大学射频与光电集成电路研究所,南京;
[17]Zhang Haiqing and Zhang Qianling,Design of 2.5GHz Low Phase Noise CMOS LC-VCO,ASIC&System State Key Laboratory,Fudan University,Shanghai 200433,China;
[18]Hsing Hao,The Design of a CMOS VCO for a Blustooth Transceiver,Electrical andComputer Engineering Department Colorado State University;
[19]Low-Power CMOS VCO with Dual-Band Local Oscillating Signal Output for 5/2.5GHzWLAN Transceivers,Institute of Microelectronics,Tsinghua University,Beijing 100084,China;
[20]Yi Xiaofeng,Fang Han,Yang Yujia,and Hong Zhiliang,A 2.4GHz Quadrature OutputFrequency Synthesizer,ASIC&System State Key Laboratory,Fudan University,Shanghai 200433,China;
[21]PIETRO ANDREANI and SVEN MATTISSON,A 2.4GHz CMOS Monolithic VCO with an MOS Varactor,Competence Center for Circuit Design,Department of applied Electronics,Lund
University,P.O.Box 118,SE-221 00 Lund,Sweden and Ericsson Mobile Communications AB,
Mobile Phones & Terminals,Scheelevagen 15,SE-221 83 Lund,Sweden;
铩颷22]L.DERMENTZOGLOU,Y.TSIATOUHAS,A.ARAPOYANNI,A Design for TestabilityScheme for CMOS LC-Tank Voltage Controlled Oscillators;
[23]AHMED H.MOSTAFA and MOURAD N.EL-GAMAL,A CMOS VCO ArchitectureSuitable for Sub-1 Volt High-Frequency(8.7-10GHz)RF Applications,Microelectronics andComputer Systems Laboratory,Department of Electrical & Computer Engineering,McGillUniversity St.,Montreal,QC,Canada H3A 2A7;
[24]WOUTER DE COCK and MICHIEL STEYAERT,A 2.5V,10GHz Fully IntegratedLC-VCO with Integrated High-Q Inductor and 30%Tuning Range,Katholieke Universiteit Leuven,Dept.ESAT-MICAS,Kasteelpark Arenberg 10,B-3001 Leuven,Belgium;
[25]Tang Zhangwen,He Jie,Jian Hongyan,and Min Hao,An Accurate 1.08GHz CMOS LCVoltage-Controlled Oscillator,State Key Laboratory ofASIC & System,Fudan University,Shanghai,200433,China;
[26]周毅,杨利,适用于高品质射频集成电感的多孔硅新型衬底制备技术,半导体学报,2005,26,(6),1182-1186;
[27]李小进,石艳玲,硅基RF平面螺旋电感的圈数对品质因子的影响,半导体学报,2003,24,(9),972-976;
[28]张志勇,体硅CMOS射频集成电路中高Q值在片集成电感的实现,微电子学,2003,33.(1),15-18;
[29]李力南,钱鹤,RF集成电感的设计与寄生效应分析,固体电子学研究与进展,2002,22,(2),153-157;
[30]冯冠中,张玉明,硅衬底上射频集成电感研究,电子器件,2005,28,(1),25-29;
[31]刘珂,菅洪彦,多电流路径抑制片上电感电流拥挤效应,半导体学报,2006,27,(9),1690-1694;
[32]李争,李哲英,射频集成电路对称型螺旋电感研究,微电子学,2007年第3期,卷37第305-305页;
[33]唐长文,电感电容压控振荡器,博士学位论文,复旦大学,2004年4月;
[34]李争,李哲英,集成电感设计优化方法,半导体技术,2007年第2期,第154-157页;
[35]李争,李哲英,硅基集成电路电感优化设计方法,北京交通大学学报,2007年第5期;
[36]Li Zheng,Li Zheying,Optimizing Approach of Spiral Inductors for Si-Based ICs.2007 7~(th)International Conference on ASIC Proceeding.Guilin,October 2007;
[37]ASITIC:Analysis and Simulation of Spiral Inductors and Transformers for ICshttp://formosa.eecs.berkely.edu,2006,1.
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