量子通信中的精密时间测量技术研究
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摘要
量子信息是量子物理与信息科学相结合的交叉学科,近年来获得迅速发展,其中量子通信是发展最为成熟的方向之一。与传统保密通信不同,量子通信的安全性由量子力学的基本原理保证,从而在本质上提升了通信安全。基于卫星平台的量子通信可实现全球化广域量子通信网络。
量子通信的信息载体通常为单光子,需要准确的探测并记录下每个单光子信号的到达时间。通信双方往往相距遥远,分别拥有各自的时间基准,这就需要在通信双方之间实现高精度的时间同步。系统时间精度直接影响到量子通信实验性能指标甚至于实验的成败,如误码率、成码率、通信距离等,而时间测量精度是决定系统时间精度的关键因素之一。
本论文针对量子通信领域对时间测量的需求,对多种时间测量技术进行了研究,并实际应用于量子密钥分配实验中,取得了良好的实验结果。
本论文主要包括以下3项内容。
首先,针对近地面的量子通信实验对时间测量技术的高要求,研究了基于FPGA的高精度TDC技术,并成功应用于远距离量子通信实验等。采用基于FPGA进位链的TDC技术,设计实现了时间分辨50ps(测量精度小于30ps)的时间测量模块,并结合实验需求,将多通道TDC与随机数产生控制、量子光电控制以及数据获取模块集成在一片FPGA内,实现系统高度集成化。配合单光子探测器和量子激光器,研制了一套完整量子通信电子学系统。该套系统已成功应用于基于运动转台的40公里、基于浮空平台的20公里以及定点96公里(链路损耗高达50dB)自由空间量子密钥分发实验,从多角度全面验证了星地量子通信的可行性。在本套系统中,以高精度时间测量电路为核心,结合同步脉冲光信号和GPS信号,发展了一套可广泛适用于远距离自由空间量子通信的高精度时间同步系统。
其次,针对星地量子密钥分配实验中的空间载荷系统对时间测量技术的高可靠性要求,设计了一种宽量程高可靠的时间测量电路,可满足空间量子密钥分配实验需求。基于SRAM工艺的FPGA TDC容易受到单粒子效应等辐射损害。为此采用专用集成电路(ASIC)时间测量芯片TDC-GP1以提高可靠性。为了满足QKD实验对时间测量电路的宽量程和低死时间要求,采用“粗”“细”结合的时间内插方法,TDC-GP1芯片作为细时间测量,粗时间测量则由FPGA时钟计数器实现,这样既保持了TDC-GP1的高精度,又扩展了时间测量范围。实际电路测试表明,时间分辨率Bin Size (也简称为LSB)达到380ps,测量精度小于250ps,死时间为1.15us,测量范围为671ms,该技术已实际应用于某空间量子密钥分配载荷。
再次,为满足未来星地远距离高损耗信道的纠缠分发等量子通信实验对高精度时间测量的要求,对基于FPGA延迟链的TDC电路进行了深入研究,提出了一种新型的多链多次平均TDC结构,具有高精度、死时间小、资源占用量少等优点,还可以灵活实现死时间和资源占用量的平衡转换。在同时使用8条链,每条链连续测量4次时,时间精度RMS高达7.4ps,时间分辨Bin Size可达lps,同时死时间仅为42ns。通过理论分析、模型仿真以及实际电路测试,对多链多次平均TDC的时间性能与链数目M和连续测量次数N的关系进行了深入探讨,对实际电路中优化性能给出了指导性意见。此外,本论文还实现了一种基于FPGA的改进型快速胖树形编码电路,可完成超宽非温度码到二进制码的快速转换。该编码电路可广泛应用于基于延迟链的FPGA TDC电路中。
本论文主要创新之处在于：
1.将基于FPGA的高精度TDC技术成功应用于量子通信实验中,提高了系统集成度和灵活性,降低了成本。基于该高精度时间测量电路,发展了一套基于光信号的高精度时间同步技术,采用同步光信号和GPS信号。该同步技术可广泛应用于自由空间量子通信中,实现遥远两地或多地之间的高精度时间同步。
2.基于TDC-GP1芯片和FPGA设计实现了一种高可靠性的时间测量电路,实际应用于某星地量子密钥分配空间载荷。
3.提出了一种新型的多链多次平均结构的TDC技术,该技术可进一步提高TDC性能,可实现时间分辨Bin Size和时间精度RMS均小于10ps,还可以灵活实现死时间和资源占用量的平衡转换,该技术可广泛用于量子通信实验中。还实现了一种基于FPGA的改进的快速胖树形编码电路,可完成超宽非温度码到二进制码的快速转换,广泛应用于基于延迟链的FPGA TDC电路中。
Quantum information has been developing rapidly in recent years, which is a new interdisciplinary subject combining quantum physics and information science. Quantum communication is the most matured research direction. The fundamental laws of quantum mechanical guarantee the unconditional security of the communication, which will essentially enhance communication security. With the help of the stable low-loss transmission channel of free-space between satellites and ground, one can even realize a global quantum communication network.
The single photons are often used as information carriers in quantum communication, such as the quantum key distribution (QKD). It's necessary to detect the single photons and record their arrival time accurately. The communication parties often far away separated and have independent reference clocks. So it's essential to establish high resolution time synchronization among them. The system timing jitter can directly influence the quantum bit error rate (QBER) and the final key rate. A high precision time to digital converter (TDC) is necessary and can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate.
In this thesis, the requirement of TDC in quantum communication was analyzed. A variety of TDC techniques are researched and successfully applied in QKD and good experimental results are obtained.
This thesis mainly includes the following3items.
Firstly, A high resolution TDC based on the FPGA's carry chains used as tapped delay lines was implemented. Its high resolution (Bin size) of50ps with precision (RMS) less than50ps, low dead time (30ns) and large dynamic range (167ms) can well meet the requirement of the QKD experiment in the near ground. Taking full advantage of the FPGA's flexibility, the multi-channel TDC and some other necessary modules in the QKD system are integrated in a single FPGA, such as random data module, laser diode(LD) control module, system control logic, etc. This remarkably improves the system's integration. With single photon detectors (SPD) and quantum laser diodes, a complete electronic system for QKD was developed. Using this QKD system, three independent QKD experiments were carried out with the system operated on a turntable via a public free-space channel of length40km, a floating hot-air balloon at20km, and over a96km link with about50dB loss, respectively. The experiments provide direct and full scale verification towards ground-satellite QKD. In this system, a high resolution time synchronization system was also developed which can be widely used in QKD. The synchronization system is based on the high resolution FPGA-TDC, and the pulse per second (PPS) signals of the GPS and a synchronous laser light setup are employed.
Secondly, to meet the special requirements of payload in satellite, such as high reliability, a wide range and high resolution TDC was designed, which is applied to a actual satellite-ground QKD experiment. As the FPGA-TDC, which is based on SRAM technique, has no experience in the space environment and can be easyly damaged by single event effects (SEE), we use an ASIC chip TDC-GP1, which is more reliably. But the chip cannot meet the experiment requirements as it's short measurement range and long process time. We combined an FPGA and the TDC-GP1chip together to implement a new TDC. The time interpolation method is used; The FPGA measures the course time and the TDC-GP1measures the fine time. This new TDC's Bin Size is380ps and RMS is less than250ps, with measurement range can be expanded to671ms. The dead time is1.15us. The TDC is being used in a payload for QKD.
Thirdly, in the future satellite-ground quantum entanglement experiment with a long-distance high-loss channel, the TDC's resolution should be higher. So a in-depth research on tapped delay line TDC in FPGA was conducted. A novel multi-chain multi-measurement average TDC structure was proposed within FPGA. The new TDC is flexible to achieve a balance between the dead time and logic utilization, with higher resolution. With theoretical analysis, model simulation and bench-top tests, we researched the timing performance of the new TDC on the variety of the chain number (M) and the measurement times (N). When using8chains (M=8) and4times (N=4) measured on each chain, the RMS was tested to be7.4ps and the bin size could be as low as1ps, with the dead time is only42ns. Besides, a fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. An encoding time of8.33ns was achieved for a 276-bit non-thermometer code to a9-bit binary code conversion. The encoder could be widely used in delay chain based FPGA TDCs.
The key innovation points are listed as follows,
1. A high resolution FPGA-TDC was applied in quantum communication, which improved the system performance. Meanwhile, The system's integration was enhanced and the cost decreased. In the experiment, we also developed a high resolution time synchronization system which can be widely used in QKD.
2. A reliable TDC based on TDC-GP1and FPGA was designed, which has wide range(671ms), high resolution(380ps) and small dead time(1.15us). The TDC is being used in a payload for satellite-ground QKD.
3. A novel multi-chain multi-measurement average TDC structure was proposed, which can further improve the timing performance, resulting the bin size and RMS both less than10ps. Besides, it is flexible to achieve a balance between the dead time and logic utilization. This TDC can be widely used in QKD. A fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. This encoder could be widely applied in delay chain based FPGA TDCs.
量子通信的信息载体通常为单光子,需要准确的探测并记录下每个单光子信号的到达时间。通信双方往往相距遥远,分别拥有各自的时间基准,这就需要在通信双方之间实现高精度的时间同步。系统时间精度直接影响到量子通信实验性能指标甚至于实验的成败,如误码率、成码率、通信距离等,而时间测量精度是决定系统时间精度的关键因素之一。
本论文针对量子通信领域对时间测量的需求,对多种时间测量技术进行了研究,并实际应用于量子密钥分配实验中,取得了良好的实验结果。
本论文主要包括以下3项内容。
首先,针对近地面的量子通信实验对时间测量技术的高要求,研究了基于FPGA的高精度TDC技术,并成功应用于远距离量子通信实验等。采用基于FPGA进位链的TDC技术,设计实现了时间分辨50ps(测量精度小于30ps)的时间测量模块,并结合实验需求,将多通道TDC与随机数产生控制、量子光电控制以及数据获取模块集成在一片FPGA内,实现系统高度集成化。配合单光子探测器和量子激光器,研制了一套完整量子通信电子学系统。该套系统已成功应用于基于运动转台的40公里、基于浮空平台的20公里以及定点96公里(链路损耗高达50dB)自由空间量子密钥分发实验,从多角度全面验证了星地量子通信的可行性。在本套系统中,以高精度时间测量电路为核心,结合同步脉冲光信号和GPS信号,发展了一套可广泛适用于远距离自由空间量子通信的高精度时间同步系统。
其次,针对星地量子密钥分配实验中的空间载荷系统对时间测量技术的高可靠性要求,设计了一种宽量程高可靠的时间测量电路,可满足空间量子密钥分配实验需求。基于SRAM工艺的FPGA TDC容易受到单粒子效应等辐射损害。为此采用专用集成电路(ASIC)时间测量芯片TDC-GP1以提高可靠性。为了满足QKD实验对时间测量电路的宽量程和低死时间要求,采用“粗”“细”结合的时间内插方法,TDC-GP1芯片作为细时间测量,粗时间测量则由FPGA时钟计数器实现,这样既保持了TDC-GP1的高精度,又扩展了时间测量范围。实际电路测试表明,时间分辨率Bin Size (也简称为LSB)达到380ps,测量精度小于250ps,死时间为1.15us,测量范围为671ms,该技术已实际应用于某空间量子密钥分配载荷。
再次,为满足未来星地远距离高损耗信道的纠缠分发等量子通信实验对高精度时间测量的要求,对基于FPGA延迟链的TDC电路进行了深入研究,提出了一种新型的多链多次平均TDC结构,具有高精度、死时间小、资源占用量少等优点,还可以灵活实现死时间和资源占用量的平衡转换。在同时使用8条链,每条链连续测量4次时,时间精度RMS高达7.4ps,时间分辨Bin Size可达lps,同时死时间仅为42ns。通过理论分析、模型仿真以及实际电路测试,对多链多次平均TDC的时间性能与链数目M和连续测量次数N的关系进行了深入探讨,对实际电路中优化性能给出了指导性意见。此外,本论文还实现了一种基于FPGA的改进型快速胖树形编码电路,可完成超宽非温度码到二进制码的快速转换。该编码电路可广泛应用于基于延迟链的FPGA TDC电路中。
本论文主要创新之处在于：
1.将基于FPGA的高精度TDC技术成功应用于量子通信实验中,提高了系统集成度和灵活性,降低了成本。基于该高精度时间测量电路,发展了一套基于光信号的高精度时间同步技术,采用同步光信号和GPS信号。该同步技术可广泛应用于自由空间量子通信中,实现遥远两地或多地之间的高精度时间同步。
2.基于TDC-GP1芯片和FPGA设计实现了一种高可靠性的时间测量电路,实际应用于某星地量子密钥分配空间载荷。
3.提出了一种新型的多链多次平均结构的TDC技术,该技术可进一步提高TDC性能,可实现时间分辨Bin Size和时间精度RMS均小于10ps,还可以灵活实现死时间和资源占用量的平衡转换,该技术可广泛用于量子通信实验中。还实现了一种基于FPGA的改进的快速胖树形编码电路,可完成超宽非温度码到二进制码的快速转换,广泛应用于基于延迟链的FPGA TDC电路中。
Quantum information has been developing rapidly in recent years, which is a new interdisciplinary subject combining quantum physics and information science. Quantum communication is the most matured research direction. The fundamental laws of quantum mechanical guarantee the unconditional security of the communication, which will essentially enhance communication security. With the help of the stable low-loss transmission channel of free-space between satellites and ground, one can even realize a global quantum communication network.
The single photons are often used as information carriers in quantum communication, such as the quantum key distribution (QKD). It's necessary to detect the single photons and record their arrival time accurately. The communication parties often far away separated and have independent reference clocks. So it's essential to establish high resolution time synchronization among them. The system timing jitter can directly influence the quantum bit error rate (QBER) and the final key rate. A high precision time to digital converter (TDC) is necessary and can effectively reduce the system timing jitter, resulting in lower QBER and higher key rate.
In this thesis, the requirement of TDC in quantum communication was analyzed. A variety of TDC techniques are researched and successfully applied in QKD and good experimental results are obtained.
This thesis mainly includes the following3items.
Firstly, A high resolution TDC based on the FPGA's carry chains used as tapped delay lines was implemented. Its high resolution (Bin size) of50ps with precision (RMS) less than50ps, low dead time (30ns) and large dynamic range (167ms) can well meet the requirement of the QKD experiment in the near ground. Taking full advantage of the FPGA's flexibility, the multi-channel TDC and some other necessary modules in the QKD system are integrated in a single FPGA, such as random data module, laser diode(LD) control module, system control logic, etc. This remarkably improves the system's integration. With single photon detectors (SPD) and quantum laser diodes, a complete electronic system for QKD was developed. Using this QKD system, three independent QKD experiments were carried out with the system operated on a turntable via a public free-space channel of length40km, a floating hot-air balloon at20km, and over a96km link with about50dB loss, respectively. The experiments provide direct and full scale verification towards ground-satellite QKD. In this system, a high resolution time synchronization system was also developed which can be widely used in QKD. The synchronization system is based on the high resolution FPGA-TDC, and the pulse per second (PPS) signals of the GPS and a synchronous laser light setup are employed.
Secondly, to meet the special requirements of payload in satellite, such as high reliability, a wide range and high resolution TDC was designed, which is applied to a actual satellite-ground QKD experiment. As the FPGA-TDC, which is based on SRAM technique, has no experience in the space environment and can be easyly damaged by single event effects (SEE), we use an ASIC chip TDC-GP1, which is more reliably. But the chip cannot meet the experiment requirements as it's short measurement range and long process time. We combined an FPGA and the TDC-GP1chip together to implement a new TDC. The time interpolation method is used; The FPGA measures the course time and the TDC-GP1measures the fine time. This new TDC's Bin Size is380ps and RMS is less than250ps, with measurement range can be expanded to671ms. The dead time is1.15us. The TDC is being used in a payload for QKD.
Thirdly, in the future satellite-ground quantum entanglement experiment with a long-distance high-loss channel, the TDC's resolution should be higher. So a in-depth research on tapped delay line TDC in FPGA was conducted. A novel multi-chain multi-measurement average TDC structure was proposed within FPGA. The new TDC is flexible to achieve a balance between the dead time and logic utilization, with higher resolution. With theoretical analysis, model simulation and bench-top tests, we researched the timing performance of the new TDC on the variety of the chain number (M) and the measurement times (N). When using8chains (M=8) and4times (N=4) measured on each chain, the RMS was tested to be7.4ps and the bin size could be as low as1ps, with the dead time is only42ns. Besides, a fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. An encoding time of8.33ns was achieved for a 276-bit non-thermometer code to a9-bit binary code conversion. The encoder could be widely used in delay chain based FPGA TDCs.
The key innovation points are listed as follows,
1. A high resolution FPGA-TDC was applied in quantum communication, which improved the system performance. Meanwhile, The system's integration was enhanced and the cost decreased. In the experiment, we also developed a high resolution time synchronization system which can be widely used in QKD.
2. A reliable TDC based on TDC-GP1and FPGA was designed, which has wide range(671ms), high resolution(380ps) and small dead time(1.15us). The TDC is being used in a payload for satellite-ground QKD.
3. A novel multi-chain multi-measurement average TDC structure was proposed, which can further improve the timing performance, resulting the bin size and RMS both less than10ps. Besides, it is flexible to achieve a balance between the dead time and logic utilization. This TDC can be widely used in QKD. A fast improved fat tree encoder was implemented in the new TDC, which can finish the ultra wide non-thermometer code to binary code encoding process within just one system clock cycle. This encoder could be widely applied in delay chain based FPGA TDCs.
引文
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