高速数字式脉冲超宽带无线收发系统的研究及实现
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摘要
随着平板电脑、智能手机、数字机顶盒、数码相机、DVD、数码摄像机、HDTV等电子消费产品的广泛普及,电子产品之间的短距离高速无线通信,一直是研究的热点。脉冲超宽带(IR-UWB)系统采用极窄脉冲传输数据。这种无载波调制的通信方式具有低功耗、低复杂度的优点,一直受到学术界和科研机构的关注。当前学术界对于IR-UWB的研究主要集中在速率为10MHz以下、甚至几KHz的生物医疗、测距、定位等方面的应用。UWB可高达500Mb/s的传输速率优势,是其它短距离无线传输技术不能相比的。业界对于高速数据传输的UWB研究,主要集中在OFDM方案和DS-CDMA方案。采用这两种方案,是由于广泛应用于窄带通信的OFDM技术和DS-CDMA技术已经相当成熟；但是其缺乏创新性。本文重点研究应用于短距离高速数据传输的IR-UWB系统。由于传统IR-UWB架构对于高速传输引起的码间干扰(ISI)无法处理,不适用于高速数据传输。本文借鉴SDR的设计思想,重点提出了一种低精度、欠采样、数字式脉冲超宽带高速无线收发机系统。
数字式IR-UWB的接收机与发射机均不需要超宽带的混频器,这样可以降低射频电路设计难度。在接收机里,超宽带的射频信号经过LNA和VGA放大后,直接由ADC采用4bit以下的低精度、低于奈圭斯特的欠采样速率采样,所有的信号处理交由数字基带完成。该架构具有低功耗、低复杂度的优点。在架构研究的基础上,本文系统地研究了基于训练码的超宽带数字基带实现算法,给出了信道估计、同步、信道均衡等实现算法,并提出基于训练码的极性序列同步与门限信道估计联合算法,该算法简单有效。本文给出了一套完整的系统解决方案,包括数字基带的实现算法和射频电路的实现方法,并对系统建模和仿真,论证了欠采样、低精度、数字式IR-UWB系统的可行性。
最后,针对提出的系统方案,本文设计了一个1bit的极低精度、4224MHz欠采样速率的、BPSK调制的IR-UWB收发机系统。物理传输最高速率为132Mb/s,有效数据传输速率为114Mb/s。收发机射频电路采用SMIC0.13μm CMOS工艺实现并流片测试,电源电压为1.2V。收发机的能耗较低,在132M/b的传输速率下,分别为18.2pJ/pulse和330pJ/pulse。发射机利用RLC电路来整形频谱,通过连续调节电阻R实现脉冲参数连续可调。发射机芯片测试结果表明：脉冲频谱在3～5GHz区间符合FCC频谱规定；脉冲宽度在900ps～1600ps之间；脉冲幅度为110mV～370mV。接收机射频电路将LNA、VGA、ADC、PLL、时钟分频器等集成。ADC采用时钟交错的16路比较器并行组成,比较器的实际工作频率降为264MHz。芯片测试结果表明：LNA和VGA增益为16dB～28dB；噪声系数小于3.7dB；ADC为1bit和4224MHz。从LNA输入端到ADC的16路输出通道,测试正常,可以为数字基带提供264MHz的16路并行采样数据。数字电路将整个系统的数字基带算法集成。同时,嵌入了一个MCU软IP核,以辅助控制和编码处理。数字基带采用FPGA开发板进行功能验证,验证结果表明：在未同步的情况下,整个基带电路能够正确地自动复位；并能够正确地解调数据,数据误码率为5×10-4。整个基带系统采用SMIC0.13μm CMOS工艺实现集成,工作频率为264MHz,总功耗为902.3mW。
Along with the PAD computer, smartphone, digital set-top boxes, digital camera, DVD, digital vidicon, HDTV and other consumer electronic products widely spreading, short-distance high-speed wireless communications between electronic products, has been a hot topic. IR-UWB system employs an extreme narrow pulse to transmit data. The advantages of non-carrier modulation communication mode, which has always been a focus among academia and research institutions, are low power and low complexity. Currently, academic researches on IR-UWB are concentrated on applications mainly about the biological health, ranging found,and location,where the transimission rate is less than10MHz, even a few KHz. UWB has the advantage of transimmision rate up to500Mb/s,which other short-range wireless transmission technology are uncompared with. The UWB research about high-speed data transmission rate in industry principally focuses on OFDM and DS-CDMA schemes, which having been widely used in narrowband communication as their proven technique; but lacking innovation. This paper focuses on IR-UWB system appling on short-range high-speed data transmission. As traditional IR-UWB architecture could not handle the inter-symbol interference at high speed, it is unsuitable for high-speed data transmission. Learning from the design ideas of the SDR, this article presents a low accuracy, subsampling and digital IR-UWB system for high-speed wireless transmissions.
The receiver and transmitter of the proposed digital IR-UWB system don't need mixeres. In the receiver, the input UWB RF signal is amplified through the LNA and VGA, then ADC directly samples the RF signal at the low precision of less than4bit and the rate lowering than Nyquist rate. All the signal processing is completed by the digital baseband. The structure has the advantages of low power and low complexity. On the basis of the architecture study, this paper systematically studied digital baseband algorithm based on the training code, and gives the achieving algorithms including the channel estimation, synchronization, channel equalization and etc. This paper proposes a joint algorithm based on training code polarity sequence synchronization and threshold channel estimation. At the same time, a complete system solution, including the realization of the digital baseband algorithms and RF circuit, is given. The feasibility of digital IR-UWB system is demonstrated by the system modeling and simulation.
Finally, a lbit low precision and sampling rate at4224MHz IR-UWB transceiver is presented. The highest physical transimission rate is132Mb/s, and the effective data transmission rate is114Mb/s. The transceiver RF circuits are implemented in SMIC0.13μm CMOS process with the supply of1.2V. The energy-efficient transmitter and receiver only consume18.2pJ/pulse and330pJ/pulse to achieve a transmission at a date rate of132Mb/s, respectively. The BPSK modulation transmitter employs a RLC circuit to shape the pulse spectrum, and pulse parameters can be adjusted continuously by adjusting the resistance R. The measurement results show that the pulse spectrum of3～5GHz is consistent with the FCC spectrum. The pulse width is between900ps and1600ps, and its amplitude is between110mV and370mV. LAN, VGA, ADC, PLL and clock divider are all integrated. The ADC is composed of16time interleaving comparators, which operating at the low frequency of 264MHz. The test results show that the ADC is lbit operating at the frequency of4224MHz,and the LNA and VGA gain coefficient is16dB～28dB. And the noise figure is less than3.7dB. The16output channels of ADC receiving signal from the LNA input is match with the simulation well and can provide16bits parallel input signals samping at the frequency of264MHz to the digital baseband. The digital circuit has integrated the entire system of digital baseband algorithms and embeds an MCU soft IP core for auxiliary control and code processing.The functional verification of digital baseband is completed in FPGA development board.The results show that the baseband circuit can automatically reset in the unsynchronized case; and demodulate data correctly.The best bit error rate is5x10-4.The digital baseband system is integrated in SMIC0.13m CMOS process. The operating frequency is264MHz and the total power is902.3mW.
数字式IR-UWB的接收机与发射机均不需要超宽带的混频器,这样可以降低射频电路设计难度。在接收机里,超宽带的射频信号经过LNA和VGA放大后,直接由ADC采用4bit以下的低精度、低于奈圭斯特的欠采样速率采样,所有的信号处理交由数字基带完成。该架构具有低功耗、低复杂度的优点。在架构研究的基础上,本文系统地研究了基于训练码的超宽带数字基带实现算法,给出了信道估计、同步、信道均衡等实现算法,并提出基于训练码的极性序列同步与门限信道估计联合算法,该算法简单有效。本文给出了一套完整的系统解决方案,包括数字基带的实现算法和射频电路的实现方法,并对系统建模和仿真,论证了欠采样、低精度、数字式IR-UWB系统的可行性。
最后,针对提出的系统方案,本文设计了一个1bit的极低精度、4224MHz欠采样速率的、BPSK调制的IR-UWB收发机系统。物理传输最高速率为132Mb/s,有效数据传输速率为114Mb/s。收发机射频电路采用SMIC0.13μm CMOS工艺实现并流片测试,电源电压为1.2V。收发机的能耗较低,在132M/b的传输速率下,分别为18.2pJ/pulse和330pJ/pulse。发射机利用RLC电路来整形频谱,通过连续调节电阻R实现脉冲参数连续可调。发射机芯片测试结果表明：脉冲频谱在3～5GHz区间符合FCC频谱规定；脉冲宽度在900ps～1600ps之间；脉冲幅度为110mV～370mV。接收机射频电路将LNA、VGA、ADC、PLL、时钟分频器等集成。ADC采用时钟交错的16路比较器并行组成,比较器的实际工作频率降为264MHz。芯片测试结果表明：LNA和VGA增益为16dB～28dB；噪声系数小于3.7dB；ADC为1bit和4224MHz。从LNA输入端到ADC的16路输出通道,测试正常,可以为数字基带提供264MHz的16路并行采样数据。数字电路将整个系统的数字基带算法集成。同时,嵌入了一个MCU软IP核,以辅助控制和编码处理。数字基带采用FPGA开发板进行功能验证,验证结果表明：在未同步的情况下,整个基带电路能够正确地自动复位；并能够正确地解调数据,数据误码率为5×10-4。整个基带系统采用SMIC0.13μm CMOS工艺实现集成,工作频率为264MHz,总功耗为902.3mW。
Along with the PAD computer, smartphone, digital set-top boxes, digital camera, DVD, digital vidicon, HDTV and other consumer electronic products widely spreading, short-distance high-speed wireless communications between electronic products, has been a hot topic. IR-UWB system employs an extreme narrow pulse to transmit data. The advantages of non-carrier modulation communication mode, which has always been a focus among academia and research institutions, are low power and low complexity. Currently, academic researches on IR-UWB are concentrated on applications mainly about the biological health, ranging found,and location,where the transimission rate is less than10MHz, even a few KHz. UWB has the advantage of transimmision rate up to500Mb/s,which other short-range wireless transmission technology are uncompared with. The UWB research about high-speed data transmission rate in industry principally focuses on OFDM and DS-CDMA schemes, which having been widely used in narrowband communication as their proven technique; but lacking innovation. This paper focuses on IR-UWB system appling on short-range high-speed data transmission. As traditional IR-UWB architecture could not handle the inter-symbol interference at high speed, it is unsuitable for high-speed data transmission. Learning from the design ideas of the SDR, this article presents a low accuracy, subsampling and digital IR-UWB system for high-speed wireless transmissions.
The receiver and transmitter of the proposed digital IR-UWB system don't need mixeres. In the receiver, the input UWB RF signal is amplified through the LNA and VGA, then ADC directly samples the RF signal at the low precision of less than4bit and the rate lowering than Nyquist rate. All the signal processing is completed by the digital baseband. The structure has the advantages of low power and low complexity. On the basis of the architecture study, this paper systematically studied digital baseband algorithm based on the training code, and gives the achieving algorithms including the channel estimation, synchronization, channel equalization and etc. This paper proposes a joint algorithm based on training code polarity sequence synchronization and threshold channel estimation. At the same time, a complete system solution, including the realization of the digital baseband algorithms and RF circuit, is given. The feasibility of digital IR-UWB system is demonstrated by the system modeling and simulation.
Finally, a lbit low precision and sampling rate at4224MHz IR-UWB transceiver is presented. The highest physical transimission rate is132Mb/s, and the effective data transmission rate is114Mb/s. The transceiver RF circuits are implemented in SMIC0.13μm CMOS process with the supply of1.2V. The energy-efficient transmitter and receiver only consume18.2pJ/pulse and330pJ/pulse to achieve a transmission at a date rate of132Mb/s, respectively. The BPSK modulation transmitter employs a RLC circuit to shape the pulse spectrum, and pulse parameters can be adjusted continuously by adjusting the resistance R. The measurement results show that the pulse spectrum of3～5GHz is consistent with the FCC spectrum. The pulse width is between900ps and1600ps, and its amplitude is between110mV and370mV. LAN, VGA, ADC, PLL and clock divider are all integrated. The ADC is composed of16time interleaving comparators, which operating at the low frequency of 264MHz. The test results show that the ADC is lbit operating at the frequency of4224MHz,and the LNA and VGA gain coefficient is16dB～28dB. And the noise figure is less than3.7dB. The16output channels of ADC receiving signal from the LNA input is match with the simulation well and can provide16bits parallel input signals samping at the frequency of264MHz to the digital baseband. The digital circuit has integrated the entire system of digital baseband algorithms and embeds an MCU soft IP core for auxiliary control and code processing.The functional verification of digital baseband is completed in FPGA development board.The results show that the baseband circuit can automatically reset in the unsynchronized case; and demodulate data correctly.The best bit error rate is5x10-4.The digital baseband system is integrated in SMIC0.13m CMOS process. The operating frequency is264MHz and the total power is902.3mW.
引文
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