高精度Sigma-Delta调制器研究及ASIC实现
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摘要
过采样求和-增量(Sigma-Delta or ΣΔ) A/D转换器(ADC)是目前高精度ADC领域中最为流行的一种结构。集成电路制造工艺的飞速发展使得ΣΔADC以速度换精度的想法得以很好的实现。在音频,数字电视以及无线通信和石油勘探领域,ΣΔADC都有着广泛的应用。ΣΔADC结构在上世纪60年代早期被提出,限于当时集成电路工艺水平的限制,在开始提出后,并不被重视,直到70年代后期,随着集成电路工艺水平的进步,其速度换取精度的想法才逐渐被重视,整个80年代ΣΔADC经历了飞速发展,出现了很多的理论模型和研究论文。从原理上讲,ΣΔADC前端模拟调制器的阶数越高,其噪声调制性能就越好,然而高阶调制器具有一个严重问题,即稳定性差,信号输入范围小。通常在设计中,都是通过仿真来确定高阶调制器的稳定输入范围。虽然自结构提出以来,ΣΔADC结构模型和研究论文层出不穷,但直到目前,尚未提出一套理论体系来指导如何设计出宽输入动态范围,稳定性高的高阶调制器。如何设计高精度,高阶稳定的ΣΔADC依然是研究的热点和难点。
ΣΔADC总体结构上可分为两个部分：前端模拟调制器和后端数字滤波器。对于数字滤波器,无论是结构模型,还是实现技术都较为成熟,且只涉及到数字电路设计,相对前端模拟调制电路较为简单。在ΣΔADC中,后端数字滤波器通常分为两级,第一级滤波器主要实现数字抽取,降低采样率,通常使用较多的通过移位链实现的梳状(Comb)滤波器；第二级通常为有限冲击响应(FIR)滤波器,在完成降频的同时用以防混叠。对Σ-Δ ADC精度起着决定影响是前端模拟调制器部分,这是ΣΔDC的主要研究内容和方向。模拟调制器完成噪声调制作用,本质上是一个模拟滤波网络,通过多级级联结构,将基带噪声挤压到高频处,而后通过后端数字滤波器将这些被挤压到高频处的噪声滤除,从而实现高精度的AD变换。模拟调制器单环结构中的级联级数也被称为阶数,阶数越高,噪声调制性能越好,然而稳定性越差,稳定输入信号范围越小。目前采用较多的是单环4阶调制结构。1阶,2阶调制器是绝对稳定的,于是产生了使用1阶或2阶单环结构叠加的调制器,这被称为MASH结构,MASH结构从根本上解决了稳定性问题,但是其自身的问题是要求各单环结构之间匹配性精确,这对实际的电路制造工艺提出了极高的要求,以目前的制造工艺而言,MASH结构的噪声调制性能仍然无法匹敌单环高阶结构。研究单环高阶高稳定性的∑△模拟调制器依然是目前较为流行的一个方向。本文研究内容也集中在前端模拟调制器,主要包括如下几个方面：一是采用根轨迹图的方法分析模拟调制器稳定性问题,采用此方法,只要给出调制器噪声传递函数,即可给出调制器的稳定输入信号范围。二是在前人研究的基础上,分析提出设计高阶模拟调制器的统一方法。利用此方法可快速完成一个基本满足设计指标的调制器的噪声传递函数。三是对当前比较流行的模拟调制器结构进行了分析,在此基础上,结合具体实例,给出了如何根据设计所需的噪声性能选择结构完成具体设计。四是在所选择结构的基础上,给出了一个单环4阶∑△模拟调制器的ASIC电路具体设计和实现过程。
本文结构安排如下：
第一章为论文绪论部分,介绍了论文研究背景,ΣΔADC发展历史,论文研究内容,创新点等。
第二章着重分析∑△调制器的主要常见结构,提出结构模型,利用根轨迹图方法对高阶调制器稳定性进行了详细的分析。本章最后对部分MASH结构也进行了介绍。
第三章在前文分析的基础上,完成了一个单环4阶∑△调制器原理图设计,并对构成调制器各模块的非线性,非理想性因素进行了讨论和模型提取,使用Matlab进行了模型仿真,对原理图设计的正确性进行了验证。
第四章在第三章设计得到的原理图的基础上详细的讨论了晶体管级电路实现,给出了前仿真结果,进一步验证原理图设计的正确性。
第五章则给出了∑△调制器主要模块的版图设计以及各模块的后仿真结果,最后给出了整个∑△调制器版图设计后的后仿真结果,对整个调制器设计的正确性进行最后的确认和验证。
第六章构建测试平台对流片芯片进行了实际测试和功能验证,给出了基本测试结果。
第七章为本论文的总结和展望,给出了调制器设计中可以进行改进的方面,并提出了下一步的研究方向。
The oversampling ΣΔ (sigma-Delta) analog to digital convertors (ADCs) are currently one of the most prevailing architectures for high-resolution ADCs. The fast development of integrated circuit's manufacture process makes the thought of exchanging resolution with speed nicely implementable. ΣΔ ADCs have now widely applied to audio, digital TV, wireless communication and oil exploration. The fundamental structure of ΣΔ ADC was firstly proposed at the beginning of60s of last century, however, with the restriction of the manufacture process of integrated circuit, it was not paied much attention to. Until in later70s, with the fast improvement of the manufacture process, the idea of exchanging resolution with speed was gradually recognized. Many theory models and papers turned up in80s and ΣΔ ADC experienced a fast developing period. Principly speaking, as the order of analog modulator in ΣΔ ADC increases, the noise performance of ΣΔ ADC would be better and the structure stability would be worse. Normally, the stability characteristic is confirmed by post-simulation of modulator circuit and there is no theory system that could direct to design a high-order stability-free ΣΔ ADC. How to design a high-resolution, high-stability ΣΔ ADC is still a research hot spot and a diffcult issue.
ΣΔ ADC is divided into two parts structurely:a front-end analog modulator and a back-end digital filter. Digital filter, whether from structure or from implementation, is mature, and as it only covers ditigal circuit process, it is relatively simple compared with analog modulator. The digital filter in ΣΔ ADC is usually comprised of two stages:the first stage mainly functions as a decimator to reduce the sampling rate. Comb filter is a prevailing structure in this stage, which is usually implemented by cascaded carry chains. The second stage is normally a FIR filter, which functions mainly as an anti-aliasing filter and at the same time also a decimator against the first stage. The performance of front-end analog modulator plays a decisive influence on the whole ΣΔ ADCs, so most of the researchs on ΣΔ ADCs mainly concentrate on the front-end analog modulator. In essence, the analog modulator is also a filter, which prepells the noise of base-band to high-frequence area. These high-frequency noises will eventually be removed by back-end digital filters to achieve high-resolution then. As said above, the higher order of analog modulator, the better will be the performance, however, the worse stability of modulator. Currently, single-loop fourth-order modulator is used often. One-order and two-order modulator is unconditionally stable, thus a structure named MASH is created, which constitutes several one-order or two-order single-loops. However, MASH structure proposes a high standard for circuit matching, which under current manufacture process, is hard to achieve. Single-loop modulators are still a mainstream of researches nowadays. This dissertation thus concentrates on studies of high-order modulators and mainly includes the following issues, firstly, analyzing the stability of high-order modulators using root locus plot. With this plot, the stable signal input range will be given as long as the noise transfer function (NTF) is provided. Secondly, based on the previous researchs, the dissertation advances a standard method of designing high-order analog modulators. Based on this method, the NTF can be quickly calculated according to the required noise performance. Thirdly, a comparative analysis is made on currently prevailing modulator structures and with a concrete example; the design process is given on how to choose modulator structure based on the calculated NTF. Fourthly, based on the chosen modulator structure, the concrete ASIC circuit implementation of a single-loop fourth-order analog modulator is provided.
The structure of this dissertation is as follows:
The first chapter is the introduction of the dissertation. In this chapter, the research background is firstly given. After that, it introduces the development roadmap of EA ADCs. Then, it presents the content and the purpose of this dissertation.
The second chapter concentrates on the structure of ΣΔ modulators. It firstly proposes a structure model for ΣΔ modulators, and based on it, it then gives a deep analysis on the stability of the structures using root locus plot. At last, an introduction to the MASH structure is also presented.
The third chapter designs a single-loop fourth-order EA modulator based on the methods presented in chapter2. Non-idealities of the designed ΣΔ modulator are analyzed and simulated using Matlab.
The fourth chapter discusses the circuit implementation of the designed ΣΔ modulator. The pre-simulation results are given for each sub-module and the whole modulator.
The fifth chapter describes the layout design of each sub-module in the modulator, and simulation results are also presented. At last, the whole modulator is simulated after evaluating the parasitic parameters. Non-idealities such as voltage variation are also simulated. The simulated resultes verify that the implemented modulator is functional and achieves the required SNR.
The sixth chapter gives the test scheme and test bench for the modulator chip. Test results are obtained.
The seventh chapter summarizes the main ideas and the innovations of this dissertation, and then points out the direction of future work.
ΣΔADC总体结构上可分为两个部分：前端模拟调制器和后端数字滤波器。对于数字滤波器,无论是结构模型,还是实现技术都较为成熟,且只涉及到数字电路设计,相对前端模拟调制电路较为简单。在ΣΔADC中,后端数字滤波器通常分为两级,第一级滤波器主要实现数字抽取,降低采样率,通常使用较多的通过移位链实现的梳状(Comb)滤波器；第二级通常为有限冲击响应(FIR)滤波器,在完成降频的同时用以防混叠。对Σ-Δ ADC精度起着决定影响是前端模拟调制器部分,这是ΣΔDC的主要研究内容和方向。模拟调制器完成噪声调制作用,本质上是一个模拟滤波网络,通过多级级联结构,将基带噪声挤压到高频处,而后通过后端数字滤波器将这些被挤压到高频处的噪声滤除,从而实现高精度的AD变换。模拟调制器单环结构中的级联级数也被称为阶数,阶数越高,噪声调制性能越好,然而稳定性越差,稳定输入信号范围越小。目前采用较多的是单环4阶调制结构。1阶,2阶调制器是绝对稳定的,于是产生了使用1阶或2阶单环结构叠加的调制器,这被称为MASH结构,MASH结构从根本上解决了稳定性问题,但是其自身的问题是要求各单环结构之间匹配性精确,这对实际的电路制造工艺提出了极高的要求,以目前的制造工艺而言,MASH结构的噪声调制性能仍然无法匹敌单环高阶结构。研究单环高阶高稳定性的∑△模拟调制器依然是目前较为流行的一个方向。本文研究内容也集中在前端模拟调制器,主要包括如下几个方面：一是采用根轨迹图的方法分析模拟调制器稳定性问题,采用此方法,只要给出调制器噪声传递函数,即可给出调制器的稳定输入信号范围。二是在前人研究的基础上,分析提出设计高阶模拟调制器的统一方法。利用此方法可快速完成一个基本满足设计指标的调制器的噪声传递函数。三是对当前比较流行的模拟调制器结构进行了分析,在此基础上,结合具体实例,给出了如何根据设计所需的噪声性能选择结构完成具体设计。四是在所选择结构的基础上,给出了一个单环4阶∑△模拟调制器的ASIC电路具体设计和实现过程。
本文结构安排如下：
第一章为论文绪论部分,介绍了论文研究背景,ΣΔADC发展历史,论文研究内容,创新点等。
第二章着重分析∑△调制器的主要常见结构,提出结构模型,利用根轨迹图方法对高阶调制器稳定性进行了详细的分析。本章最后对部分MASH结构也进行了介绍。
第三章在前文分析的基础上,完成了一个单环4阶∑△调制器原理图设计,并对构成调制器各模块的非线性,非理想性因素进行了讨论和模型提取,使用Matlab进行了模型仿真,对原理图设计的正确性进行了验证。
第四章在第三章设计得到的原理图的基础上详细的讨论了晶体管级电路实现,给出了前仿真结果,进一步验证原理图设计的正确性。
第五章则给出了∑△调制器主要模块的版图设计以及各模块的后仿真结果,最后给出了整个∑△调制器版图设计后的后仿真结果,对整个调制器设计的正确性进行最后的确认和验证。
第六章构建测试平台对流片芯片进行了实际测试和功能验证,给出了基本测试结果。
第七章为本论文的总结和展望,给出了调制器设计中可以进行改进的方面,并提出了下一步的研究方向。
The oversampling ΣΔ (sigma-Delta) analog to digital convertors (ADCs) are currently one of the most prevailing architectures for high-resolution ADCs. The fast development of integrated circuit's manufacture process makes the thought of exchanging resolution with speed nicely implementable. ΣΔ ADCs have now widely applied to audio, digital TV, wireless communication and oil exploration. The fundamental structure of ΣΔ ADC was firstly proposed at the beginning of60s of last century, however, with the restriction of the manufacture process of integrated circuit, it was not paied much attention to. Until in later70s, with the fast improvement of the manufacture process, the idea of exchanging resolution with speed was gradually recognized. Many theory models and papers turned up in80s and ΣΔ ADC experienced a fast developing period. Principly speaking, as the order of analog modulator in ΣΔ ADC increases, the noise performance of ΣΔ ADC would be better and the structure stability would be worse. Normally, the stability characteristic is confirmed by post-simulation of modulator circuit and there is no theory system that could direct to design a high-order stability-free ΣΔ ADC. How to design a high-resolution, high-stability ΣΔ ADC is still a research hot spot and a diffcult issue.
ΣΔ ADC is divided into two parts structurely:a front-end analog modulator and a back-end digital filter. Digital filter, whether from structure or from implementation, is mature, and as it only covers ditigal circuit process, it is relatively simple compared with analog modulator. The digital filter in ΣΔ ADC is usually comprised of two stages:the first stage mainly functions as a decimator to reduce the sampling rate. Comb filter is a prevailing structure in this stage, which is usually implemented by cascaded carry chains. The second stage is normally a FIR filter, which functions mainly as an anti-aliasing filter and at the same time also a decimator against the first stage. The performance of front-end analog modulator plays a decisive influence on the whole ΣΔ ADCs, so most of the researchs on ΣΔ ADCs mainly concentrate on the front-end analog modulator. In essence, the analog modulator is also a filter, which prepells the noise of base-band to high-frequence area. These high-frequency noises will eventually be removed by back-end digital filters to achieve high-resolution then. As said above, the higher order of analog modulator, the better will be the performance, however, the worse stability of modulator. Currently, single-loop fourth-order modulator is used often. One-order and two-order modulator is unconditionally stable, thus a structure named MASH is created, which constitutes several one-order or two-order single-loops. However, MASH structure proposes a high standard for circuit matching, which under current manufacture process, is hard to achieve. Single-loop modulators are still a mainstream of researches nowadays. This dissertation thus concentrates on studies of high-order modulators and mainly includes the following issues, firstly, analyzing the stability of high-order modulators using root locus plot. With this plot, the stable signal input range will be given as long as the noise transfer function (NTF) is provided. Secondly, based on the previous researchs, the dissertation advances a standard method of designing high-order analog modulators. Based on this method, the NTF can be quickly calculated according to the required noise performance. Thirdly, a comparative analysis is made on currently prevailing modulator structures and with a concrete example; the design process is given on how to choose modulator structure based on the calculated NTF. Fourthly, based on the chosen modulator structure, the concrete ASIC circuit implementation of a single-loop fourth-order analog modulator is provided.
The structure of this dissertation is as follows:
The first chapter is the introduction of the dissertation. In this chapter, the research background is firstly given. After that, it introduces the development roadmap of EA ADCs. Then, it presents the content and the purpose of this dissertation.
The second chapter concentrates on the structure of ΣΔ modulators. It firstly proposes a structure model for ΣΔ modulators, and based on it, it then gives a deep analysis on the stability of the structures using root locus plot. At last, an introduction to the MASH structure is also presented.
The third chapter designs a single-loop fourth-order EA modulator based on the methods presented in chapter2. Non-idealities of the designed ΣΔ modulator are analyzed and simulated using Matlab.
The fourth chapter discusses the circuit implementation of the designed ΣΔ modulator. The pre-simulation results are given for each sub-module and the whole modulator.
The fifth chapter describes the layout design of each sub-module in the modulator, and simulation results are also presented. At last, the whole modulator is simulated after evaluating the parasitic parameters. Non-idealities such as voltage variation are also simulated. The simulated resultes verify that the implemented modulator is functional and achieves the required SNR.
The sixth chapter gives the test scheme and test bench for the modulator chip. Test results are obtained.
The seventh chapter summarizes the main ideas and the innovations of this dissertation, and then points out the direction of future work.
引文
[1]冯军,“一种16位Σ△音频ADC中调制器的设计与实现”,硕士论文,电子科技大学(成都),2006。
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[6]袁小龙,“高性能Σ△调制器,模数转换器的研究”,博士论文,浙江大学,2009.
[7]张洲洋等,“一种高速连续时间Sigma-Delta ADC设计”,现代电子技术,vol.20,2010.
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[1]H.Inose, Y.Yasuda and J.Murakami, "A telemetering system by code modulation-ΔΣ modulation," IRE Trans. Space Electron. Telemetry, vol.8, pp.204-209, Sep.1962.
[2]G.R.Ritchie, J.C.Candy and W.H.Ninke, "Interpolative digital to analog converters," IEEE Transanctions on Communications, vol.22, pp.1797-1806, Nov.1974.
[3]S.R.Norsworthy, R.Schreier and G.C.Temes, "Delta-Sigma Data Converters:Theory, Design and Implementation," IEEE Press,1997.
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